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Cirrus Logic
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CDB5374
User Manual
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Cirrus Logic CDB5374 User Manual

CDB5374
Multichannel Marine Seismic Evaluation System

Features

z Four-channel Seismic Acquisition Node
– CS5374 dual amplifier & ∆Σ modulator (2x) – CS5376A quad digital filter (1x) – CS4373A ∆Σ test DAC (1x) – Precision voltage reference – Clock recovery PLL
z On-board Microcontroller
– SPI™ interface to digital filter – USB communication with PC
z PC Evaluation Software
– Register setup & control – FFT frequency analysis – Time domain analysis – Noise histogram analysis
General Description
The CDB5374 board is used to evaluate the functionality and performance of the Cirrus Logic multichannel ma­rine seismic chip set. Data sheets for the CS5374, CS5376A, and CS4373A devices should be consulted when using the CDB5374 evaluation board.
Screw terminals connect external differential hydro­phone sensors to the analog inputs of the measurement channels. An on-board test DAC creates precision differ­ential analog signals for in-circuit performance testing without an external signal source.
The evaluation board includes an 8051-type microcon­troller with hardware SPI The microcontroller communic ates with the digital filter via SPI and with the PC evaluation software via USB. The PC software controls register and coefficient initial­ization and performs time domain, histogram, and FFT frequency analysis on captured data.
ORDERING INFORMATION
CDB5374 Evaluation Board
™ and USB serial interfaces.
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2009
(All Rights Reserved)
JAN ‘09
DS862DB1

REVISION HISTORY

Revision Date Changes
DB1 JAN 2009 Initial release.
CDB5374
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Re presentative. To find the one near est to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirru s") believe that the information contained in this document is accurate and reli a b le. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing or ders, that in formatio n be ing relied on is current and comple te. All products a re sold s ubj ect to the term s and conditions of sa le supplied at the time of order acknow ledgment, includin g those pertaining to warranty, indemni fication, and limitatio n of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the prop erty o f C irrus a nd b y furn ishing this inform ation, Cirru s grants no lice nse, expres s or implied under any patents, mask work rights, copyrights, trade marks, trad e secrets or other int ellectual property r ights. Cirr us owns the co pyrights a ssociated wit h the inf ormation contained herein and gives consent for copies to be made of the inform ation only for us e withi n your o rgani zation w ith resp ect to Cir rus in tegrate d circui ts or other p rodu cts of C irrus. This co n­sent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP­ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANT­ABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNI FY CIRRUS , ITS O FFICERS, DIRECTOR S, EMPLOY EES, DIST RIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILI TY, IN­CLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Windows, Windows XP, Windows 2000, and Windows NT are trademarks or registered trademarks of Microsoft Corporation. Intel and Pentium are registered trademarks of Intel Corporation. SPI is a trademark of Motorola, Inc. I2C (I2C) is a registered trademark of Philips Semiconductor Corporation. USBXpress is a registered trademark of Silicon Laboratorie s, Inc .
2 DS862DB1
CDB5374

TABLE OF CONTENTS

REVISION HISTORY .................................................................................................................... 2
1. INITIAL SETUP ......................................................................................................................... 5
1.1 Kit Contents ............................... ... ... ... ....................................... ... ... .... ... ... ........................ 5
1.2 Hardware Setup ............................... ....................... ...................... ....................... .............. 5
1.2.1 Default Jumper Settings ............................. ... ... ... .... ... ... ... ... .... .............................. 6
1.2.2 Default DIP Switch Settings ............................................ ..................................... 8
1.3 Software Setup ................................... ... .... ... ... ... .... ... ........................................................ 9
1.3.1 PC Requirements ............................. ... ... .... ... ... ....................................... ... ... ... .... . 9
1.3.2 Seismic Evaluation Software Installation ...................................... ... .... ... ... ... ........ 9
1.3.3 USBXpress Driver Installation ............................................................................... 9
1.3.4 Launching the Seismic Evaluation Software .............................. ......................... 10
1.4 Self-testing CDB5374 ...................... ... ... .... ... ... ... .... ... ....................................... ... ... ... ... ... 11
1.4.1 Noise test ..... .... ... ... ... ....................................... ... .... ... ...................................... ... 11
1.4.2 Distortion Test .. ... ....................................... ... ... ... .... ... ... ... ... .... ... ......................... 12
2. HARDWARE DESCRIPTION ................................................................................................. 13
2.1 Block Diagram ................................................................................................................ 13
2.2 Analog Hardware ....................... ... ... ... ... .... ... ... ... .... ...................................... .... ... ... ... ... ... 14
2.2.1 Analog Inputs ...... ... ... .... ... ... ....................................... ... ... ... .... ... ... ...................... 14
2.2.2 Differential Amplifiers .............................................. ... ... ...................................... 16
2.2.3 Delta-Sigma Modulators ..................................................................................... 17
2.2.4 Delta-Sigma Test DAC ............................... ... ... ... .... ... ... ... ... .... ............................ 18
2.2.5 Voltage Reference .............. ... ... .... ...................................... .... ... ... ... .... ... ............ 19
2.3 Digital Hardware .............................................................................................................. 20
2.3.1 Digital Filter ......................................... ... .... ...................................... .... ... ... ... ...... 20
2.3.2 Interface CPLD ................................... ... .... ... ... ... .... ... ... ...................................... 22
2.3.3 Digital Control Signals ......................... ... .... ...................................... .... ... ... ... ... ... 24
2.3.4 Microcontroller ....................... ... .... ... ... ... .... ... ....................................... ... ... ... ... ... 24
2.3.5 Phase Locked Loop .................. .... ... ... ... ............................................................. 26
2.3.6 RS-485 Telemetry .. ... .......................................................................................... 28
2.3.7 UART Connection .. ... .... ... ... ... ... .... ...................................................................... 29
2.3.8 External Connector ................... .... ... ... ... .... ... ...................................................... 30
2.4 Power Supplies ................ ... ... .... ...................................... .... ... ... ... ... .... ... ... ... ................... 30
2.4.1 Analog Voltage Regulators ........... ... ... ... .... ... ... ... .... ... ...................................... ... 30
2.4.2 Digital Voltage Regulators .................................................................................. 31
2.5 PCB Layout ..................... ... ... .... ...................................... .... ... ... ... ... ................................ 32
2.5.1 Layer Stack ...... ... ... ... .... ... ....................................... ... ... ... ... .... ... ......................... 32
2.5.2 Differential Pairs ............................ ... ... ... .... ... ... ... ....................................... ... ... ... 32
2.5.3 Bypass Capacitors . ....................................... ... ... .... ... ... ... ................................... 33
2.5.4 Dual Row Headers .............................................................................................. 34
3. SOFTWARE DESCRIPTION .................................................................................................. 35
3.1 Menu Bar ................................... ... ... ... ... .... ...................................... .... ... ... ... .... ... ............ 35
3.2 About Panel ..................................................................................................................... 36
3.3 Setup Panel ..................................................................................................................... 37
3.3.1 USB Port ...... .... ... ... ....................................... ... ... .... ... ...................................... ... 38
3.3.2 Digital Filter ......................................... ... .... ... ....................................... ... ... ... ... ... 39
3.3.3 Analog Front End ...... .... ... ... ... ... .... ... ....................................... ... ... ... .... ... ... ... ... ... 40
3.3.4 Test Bit Stream ................... ... ... .... ... ....................................... ... ... ... .... ... ... ......... 40
3.3.5 Gain/Offset ............................. ... .... ... ... ....................................... ... ... .... ... ............ 41
3.3.6 Data Capture .......................... ....................................... ... ... .... ............................ 42
3.3.7 External Macros ..... ... .... ... ... ... ... ....................................... ... .... ... ... ... .... ............... 43
3.4 Analysis Panel ................................................................................................................. 44
3.4.1 Test Select ... .... ... ... ....................................... ... ... .... ... ... ...................................... 45
DS862DB1 3
CDB5374
3.4.2 Statistics ........................ ... ... ....................................... ... ... ... .... ............................46
3.4.3 Plot Enable ............................. ... .... ... ... ... .... ... ....................................... ... ... ... ... ... 46
3.4.4 Cursor ....................... .... ... ....................................... ... ... ... ................................... 47
3.4.5 Zoom ...................................... ... .... ...................................... .... ... ... ... ...................47
3.4.6 Refresh ...................... .... ...................................... .... ... ... ... ... .... ............................ 47
3.4.7 Harmonics ..................................... ... ... ... .... ...................................... .... ... ... ... ... ... 47
3.4.8 Spot Noise ..................................................... ... ... .... ...................................... ... ... 47
3.4.9 Plot Error ....................................... ... ... ....................................... ... ... .... ... ............47
3.5 Control Panel ...................................................................................................................48
3.5.1 DF Registers ....... ... ... ....................................... ... .... ... ... ... ... ................................ 49
3.5.2 DF Commands .................................... ... .... ... ... ....................................... ... ... ... ... 49
3.5.3 SPI ......................... ... .... ...................................... .... ... ... ......................................49
3.5.4 Macros ...................... .... ...................................... .... ... ... ...................................... 50
3.5.5 GPIO ...... ... ... ....................................... ... .... ... ... ....................................... ... ... ... ... 50
3.5.6 Customize .... .... ...................................... .... ... ... ... ....................................... ... ... ... 51
3.5.7 External Macros ........ .... ... ... ... ....................................... ... ... .... ... ... ... ...................51
4. BILL OF MATERIALS ...........................................................................................................52
5. LAYER PLOTS ...................................................................................................................... 54
6. SCHEMATICS ........................................................................................................................ 62
LIST OF FIGURES
Figure 1. CDB5374 Block Diagram ...............................................................................................13
Figure 2. RC Filter External Components ..................................................................................... 16
Figure 3. CPLD Default Signal Assignments.................................................................................23
Figure 4. Differential Pair Routing.................................................................................................32
Figure 5. Quad Group Routing...................................................................................................... 33
Figure 6. Bypass Capacitor Placement.........................................................................................33
Figure 7. Dual-row Headers with Shorts ....................................................................................... 34
LIST OF TABLES
Table 1. Analog Inputs Default Jumper Settings........................................................ .... ... ... ... ... .... . 6
Table 2. VREF, SPI, SYNC, RESET Default Jumper Settings........................................................6
Table 3. Power Supplies Default Jumper Settings..........................................................................7
Table 4. Clock Inputs Default Jumper Settings ............................. .... ... ... ... ... .... ... ........................... 7
Table 5. RS-485 Default Jumper Settings.......................................................................................8
Table 6. DIP Switch Default Settings ..............................................................................................8
Table 7. Screw Terminal Input Connectors...................................................................................14
4 DS862DB1

1. INITIAL SETUP

1.1 Kit Contents

The CDB5374 evaluation kit includes:
• CDB5374 Evaluation Board
• USB Cable (A to B)
• Software Download Information Card
The following are required to operate CDB5374, and are not included:
• Bipolar Power Supply with Banana Jack Outputs (+/-12 V @ 300 mA)
• Banana Jack Cables (4x)
• PC Running Windows 2000 or XP with an Available USB Port
• Internet Access to Download the Evaluation Software
CDB5374

1.2 Hardware Setup

To set up the CDB5374 evaluation board:
• Set all jumpers and DIP switches to their default settings (see next sections).
• With power off, connect the CDB5374 power inputs to the power supply outputs. VA- = -12 V VA+ = +12 V GND = 0 V VD = +12 V
• Connect the USB cable between the CDB5374 USB connector and the PC USB port.
• Proceed to the Software Setup section to install the evaluation software and USB driver.
DS862DB1 5

1.2.1 Default Jumper Settings

DAC_OUT+ 1 **2INA+
DAC_OUT- 3 **4INA-
DAC_OUT- 5 ---------- 6INB­DAC_OUT+ 7 ---------- 8INB+ DAC_BUF+ 9 ---------- 10 INA+
DAC_BUF- 11 ---------- 12 INA-
DAC_BUF- 13 **14 INB- DAC_BUF+ 15 **16 INB+
BNC_IN+ 17 **18 INA+
BNC_IN- 19 **20 INA- BNC_IN- 21 **22 INB-
BNC_IN+ 23 **24 INB+
CDB5374
J27, J227, J327, J427
CH1, CH2, CH3, CH4
Analog Input Selections
Table 1. Analog Inputs Default Jumper Settings
J519, J19, J20
Voltage Reference Jumpers
VREF+ 1 ---------- 2
VREF- 3 ---------- 4
J56
SYNC Source Selection
SYNC_IO 1 ---------- 2 SYNC
Table 2. VREF, SPI, SYNC, RESET Default Jumper Settings
EECS 3 **4 SSI
J43
SPI Chip Select Input
SSI 1 ---------- 2 SSI
J58
RESET Source Selection
RST_PB 1 ---------- 2
RST_EXT 3 ---------- 4
6 DS862DB1
CDB5374
J10
VA- Voltage Selection
-2.5VA 1 ---------- 2 GND 3 **4
EXT_VA- 5 **6
J12
VD Input Voltage Source
EXT_VA+ 1 **2
EXT_VD 3 ---------- 4
J22
VD Voltage Selection
+3.3VD 1 ---------- 2
EXT_VD 3 **4
Table 3. Power Supplies Default Jumper Settings
J11
VA+ Voltage Selection
+2.5VA 1 ---------- 2
+5VA 3 **4
EXT_VA+ 5 **6
J13
VCORE Input Voltage Source
EXT_VA+ 1 **2
EXT_VD 3 ---------- 4
J21
VCORE Voltage Selection
+3.3VD 1 ---------- 2 +2.5VD 3 **4
EXT_VD 3 **4
J16
PLL Input Clock Selection
32.768 MHz 1 ---------- 2
16.384 MHz 3 **4
8.192 MHz 5 **6
4.096 MHz 7 **8
2.048 MHz 9 **10
1.024 MHz 11 **12
Table 4. Clock Inputs Default Jumper Settings
DS862DB1 7
CPLD, Microcontroller
Input Clock Selections
32.768 MHz 1 ---------- 2
16.384 MHz 3 **4
8.192 MHz 5 **6
4.096 MHz 7 **8
2.048 MHz 9 **10
1.024 MHz 11 **12 CLK_EXT 13 **14
J17, J18
15 **16
CDB5374
J15
I2C Data
SDA+ 1 **2
SDA- 3 **4
SDA 5 **6
GND 7 **8
J24
Clock Source
CLK+ 1 **2
CLK- 3 **4
CLK_I/O 5 **6
GND 7 **8
J14
I2C Clock
SCL+ 1 **2
SCL- 3 **4
SCL 5 **6
GND 7 **8
J23
I2C Clock Driver Enable
GND 1 ---------- 2
VD 3 **4
J25
Sync Source
SYNC+ 1 **2 SYNC- 3 **4
SYNC_I/O 5 **6
GND 7 **8
J33
Clock Driver Enable
GND 1 ---------- 2
VD 3 **4
Table 5. RS-485 Default Jumper Settings

1.2.2 Default DIP Switch Settings

BOOT 1 *-2
LGND 5 *-6
OFST 7 -*8
Table 6. DIP Switch Default Settings
J34
Sync Driver Enable
GND 1 ---------- 2
VD 3 **4
S5
* = down, - = up
3 *-4
8 DS862DB1

1.3 Software Setup

1.3.1 PC Requirements

The PC hardware requirements for the Cirrus Seismic Evaluation system are:
CDB5374
• Windows XP®, Windows 2000™, Windows NT
®
•Intel® Pentium® 600MHz or higher microprocessor
• VGA resolution or higher video card
• Minimum 64MB RAM
• Minimum 40MB free hard drive space

1.3.2 Seismic Evaluation Software Installation

Important: For reliable USB communication, the USBXpress® driver must be installed after the Seismic Evaluation Software installation but before launching the application. The USBXpress driver files are in- cluded in a sub-folder as part of the installation.
To install the Cirrus Logic Seismic Evaluation Software:
• Go to the Cirrus Logic Industrial Software web page (http://www.cirrus.com/industrialsoftware the link for “Cirrus Seismic Evaluation GUI” to get to the download page and then click the link for “Cir- rus Seismic Evaluation GUI Release Vxx” (xx indicates the version number).
• Read the software license terms and click “Accept” to download the “SeismicEvalGUI_vxx.zip” file to any directory on the PC.
• Unzip the downloaded file to any directory and a “Distribution\Volume1” sub-folder containing the in­stallation application will automatically be created.
• Open the “Volume1” sub-folder and run “setup.exe”. If the Seismic Evaluation Software has been pre­viously installed, the uninstall wizard will automatically remove the previous version during install.
• Follow the instructions presented by the Cirrus Seismic Evaluation Installation Wizard. The default in­stallation location is “C:\Program Files\Cirrus Seismic Evaluation”.
). Click
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus Logic web site with step-by-step instructions on installing the Seismic Evaluation Software.

1.3.3 USBXpress Driver Installation

Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic Evaluation Software installation but before launching the application. The USBXpress driver files are in- cluded in a sub-folder as part of the installation.
The Cirrus Logic Seismic Evaluation Software communicates with CDB5374 via USB using the USBX­press driver from Silicon Laboratories (http://www.silabs.com files are included as part of the installation package.
To install the USBXpress driver (after installing the Seismic Evaluation Software):
• Connect CDB5374 to the PC through an available USB port and apply power. The PC will detect
DS862DB1 9
). For convenience, the USBXpress driver
CDB5374
CDB5374 as an unknown USB device.
• If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manager go to the properties of the unknown USB API device and select “Update Driver”.
• Select “Install from a list or specific location”, then select “Include this location in the search” and then browse to “C:\Program Files\Cirrus Seismic Evaluation\Driver\”. The PC will recognize and install the USBXpress device driver.
• After driver installation, cycle power to CDB5374. The PC will automatically detect it and add it as a USBXpress device in the Windows Hardware Device Manager.
An application note, AN271 - Cirrus Seismic Evaluation GUI Installation Guide, is available from the Cirrus Logic web site with step-by-step instructions on installing the USBXpress driver.

1.3.4 Launching the Seismic Evaluation Software

Important: For reliable USB communication, the USBXpress driver must be installed after the Seismic Evaluation Software installation but before launching the application. The USBXpress driver files are in- cluded in a sub-folder as part of the installation.
To launch the Cirrus Seismic Evaluation Software, go to:
• Start
or:
• C:\Program Files\Cirrus Seismic Evaluation\SeismicGUI.exe
For the most up-to-date information about the software, please refer to its help file:
• Within the software: Help
or:
• C:\Program Files\Cirrus Seismic Evaluation\SEISMICGUI.HLP
Ö
Programs Ö Cirrus Seismic Evaluation Ö Cirrus Seismic Evaluation
Ö
Contents
10 DS862DB1
CDB5374

1.4 Self-testing CDB5374

Noise and distortion self-tests can be performed once hardware and software setup are complete. First, initialize the CDB5374 evaluation system:
• Launch the evaluation software and apply power to CDB5374.
• Click ‘OK’ on the About panel to get to the Setup panel.
• On the Setup panel, select Open Target on the USB Port sub-panel.
• When connected, the Board Name and MCU code version will be displayed.

1.4.1 Noise test

Noise performance of the measurement channel can be tested as follows:
• Set the controls on the Setup panel to match the picture:
DS862DB1 11
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture to collect a data record.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Noise FFT from the Test Select control to display the calculated noise statistics.
• Verify the noise performance (S/N) is 121 dB or better.

1.4.2 Distortion Test

• Set the controls on the Setup panel to match the picture:
CDB5374
• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.
• After digital filter configuration is complete, click Capture to collect a data record.
• Once the data record is collected, the Analysis panel is automatically displayed.
• Select Signal FFT from the Test Select control to display the calculated signal statistics.
• Verify the distortion performance (S/D) is 108 dB or better.
12 DS862DB1

2. HARDWARE DESCRIPTION

2.1 Block Diagram

Hydrophone
Sensor
M U X
AMP
CDB5374
CS5374
DS
Modulator
Hydrophone
Sensor
Hydrophone
Sensor
Hydrophone
Sensor
M U X
M U X
M U X
AMP
AMP
AMP
DS
Modulator
CS5374
DS
Modulator
DS
Modulator
CS5376A
Digital Filter
CS4373A
Test DAC
Microcontroller
or
Configuration
EEPROM
System
Telemetry
Figure 1. CDB5374 Block Diagram
Major blocks of the CDB5374 evaluation board include:
• CS5374 Dual Amplifier & ∆Σ Modulator (2x)
• CS5376A Quad Digital Filter
• CS4373A ∆Σ Test DAC
• Precision Voltage Reference
• Interface CPLD
• Microcontroller with USB
• Phase Locked Loop
• RS-485 Transceivers
• Voltage Regulators
DS862DB1 13
CDB5374

2.2 Analog Hardware

2.2.1 Analog Inputs

2.2.1.1 External Inputs - INA, INB, BNC
External signals into CDB5374 are typically from piezoelectric hydrophones, which are high-impedance sensors optimized to measure pressure in marine applications.
External signals connect to CDB5374 through screw terminals on the left side of the PCB. For each chan­nel (CH1, CH2, CH3, CH4), these screw terminals make connections to two external differential inputs, INA and INB. In addition, GND and GUARD connections are provided for connecting sensor cable shields, if present.
Signal Input Screw Terminal
CH1 INA J32 CH1 INB J41 CH2 INA J232 CH2 INB J241 CH3 INA J332 CH3 INB J341 CH4 INA J432 CH4 INB J441
Table 7. Screw Terminal Input Connectors
2.2.1.2 GUARD Output, GND Connection
The CS5374 hydrophone amplifier provides a GUARD signal output designed to actively drive the cable shield of a high impedance sensor with the common mode voltage of the sensor differential signal. This GUARD output on the cable shield minimizes leakage by minimizing the voltage differential between the sensor signal and the cable shield.
The GUARD signal is output to screw terminals on the left side of the PCB an d a separate GND connec­tion screw terminal for each channel is also provided if a ground connection to the sensor cable shield is preferred.
2.2.1.3 Internal Inputs - DAC_OUT, DAC_BUF
The CS4373A test DAC has two high-performance differential test outputs, a precision output (DAC_OUT) and a buffered output (DAC_BUF). These test outputs can be connected to the INA or INB inputs of any channel through the input selection jumpers.
By default, CDB5374 is populated with passive RC filter components on the INA inputs, and no filter com­ponents on the INB inputs (though the component footprints are present on the INB inputs). Because the CS4373A precision output will not tolerate significant loading, on CDB5374 the DAC_OUT signal should only jumper to the INB inputs. The CS4373A buffered outputs are less sensitive to the RC filter load and DAC_BUF can be jumper-ed to either the INA or INB inputs.
14 DS862DB1
CDB5374
2.2.1.4 Input Protection
Sensor inputs must have circuitry to protect the analog electronics from voltage spikes as hydrophones can produce large voltage spikes if located near an air gun source.
Discrete switching diodes quickly clamp the analog inputs to the power supply rails when the input voltage spikes. These diodes are reverse biased in normal operation and have low reverse bias leakage and ca­pacitance characteristics to maintain high linearity on the analog inputs.
Specification Value
Dual Series Switching Diode - ON Semiconductor BAV99LT1 Surface Mount Package Type SOT-23 Non-Repetitive Peak Forward Current (1 µs, 1 ms, 1 s) Reverse Bias Leakage (25 C to 85 C) Reverse Bias Capacitance (0 V to 5 V) 1.5 pF - 0.54 pF
2.2.1.5 Input RC Filters
Following the diode clamps is an RC filter network that bandwidth limits the sensor inputs into the ampli­fiers to “chop the tops off” residual voltage spikes not clamped by the discrete diodes. In addition , all Cirrus Logic component ICs have built in ESD protection diodes guaranteed to 2000 V HBM / 200 V MM (JEDEC standard). The small physical size of these ESD diodes restricts their current capacity to 10 mA.
2.0 A, 1.0 A, 500 mA
0.004 µA - 0.4 µA
For marine applications that use the CS3302A amplifier, the inherent capa citance of the piezoelectric sen­sor is combined with large resistors to create an analog high-pass RC filter to eliminate the low-frequency components of ocean noise.
Marine Differential Filter Specification Value
Hydrophone Group Capacitance 128 nF + 10% Differential Resistance
412 kΩ + 2 kΩ = 400 Ω
-3 dB Corner @ 6 dB/octave 40 kHz + 10%
2.2.1.6 Common Mode Bias
Differential analog signals into the CS3301A/02A amplifiers are required to be biased to the center of the power supply voltage range, which for bipolar supplies is near ground potential. This common mode bias voltage is created by buffering the voltage reference, which is nominally +2.5 V relative to the VA- power supply.
Resistors to create the common mode bias are selected based on the sensor impedance and may need to be modified from the CDB5374 defaults depending on the sensor to be used. Refer to the recommend­ed operating bias conditions for the selected sensor, which are available from the sensor manufacturer.
Specification Value
Hydrophone Se nsor Bi as Resistance
18 MΩ || 18 MΩ = 9 MΩ
DS862DB1 15
CDB5374

2.2.2 Differential Amplifiers

The CS5374 amplifiers act as a low-noise gain stage for internal or external differential analog signals.
Ana lo g Si gnals De scri pti on
INA Sensor analog input I NB Tes t DAC analog input OUT Analog outputs GUARD Amplifier guard output
Digital Signals Description
MU X[0..1 ] Input mux se lection (register bits) GA IN[0..2] Gain range selection (register bits) PW DN Pow er do wn mode enable (register bi t)
2.2.2.1 GUARD Output
The CDB5374 hydrophone amplifiers are not chopper stabilized (with 1/f noise typically buried below the low-frequency ocean noise) to achieve very high input impedance. To minimize leakage from high-imped­ance sensors connected to the CS5374 amplifier, a GUARD signal output can actively drive a sensor ca­ble shield with the common mode voltage of the sensor signal.
2.2.2.2 Analog Outputs - OUT
The analog outputs of the CS5374 differential amplifiers are externally split into rough-charge and fine­charge signals for input to the ∆Σ modulators. Analog signal traces out of the CS5374 amplifiers and into the modulators are 4-wire INR+ / INF+ / INF- / INR- quad groups, and are routed with INF+ and INF- as a traditional differential pair and INR+ and INR- as guard traces outside the respective INF+ and INF- trac­es.
INR+ INR+ INF+ INF­INR-
Figure 2. RC Filter External Components
INF+
INF-
INR-
2.2.2.3 Anti-alias RC Filters
The CS5374 ∆Σ modulator is 4th order and high-frequency input signals can cause instability. Simple sin­gle-pole anti-alias RC filters are required between the amplifier outputs and the modulator inputs to band­width limit analog signals into the modulator.
16 DS862DB1
CDB5374
The amplifier outputs are connected to external 680 Ω series resistors and a differential anti-alias RC filter is created by connecting 20 nF of high-linearity differential capacitance (2x 10 nF C0G) between each half of the rough and fine signals.

2.2.3 Delta-Sigma Modulators

A CS5374 ∆Σ modulator performs the A/D function for a differential analog input signal from the amplifier. The digital output is an oversampled ∆Σ bit streams.
Ana lo g Si gn al s De sc ri pt i on
INR 1, INF 1 Ch an nel 1 analo g rough / fi ne inp ut s INR 2, INF 2 Ch an nel 2 analo g rough / fi ne inp ut s VREF Voltage refe rence analog inputs
Digital Signals Description
MDATA[1..2] Modulator delta-sigma data outputs MFLAG[1..2] Modulator over-range flag outputs MCLK Modulator clock input MSYNC Modulator syn chronization input PWDN[1..2] Power down mode enable (register bits) OFS T Internal offset enable (register bits)
2.2.3.1 Rough-Fine Inputs - INR, INF
The modulator analog inputs are separated into rough and fine signals, each of which has an anti-alias RC filter to limit the signal bandwidth into the modulator inputs.
2.2.3.2 Offset Enable - OFST
The CS5374 ∆Σ modulator requires differential offset to be enabled to eliminate idle tones f or a terminated input. OFST is enabled by default in the CS5374 registers.
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CDB5374

2.2.4 Delta-Sigma Test DAC

The CS4373A DAC creates differential analog signals for system tests. Multiple test modes are available and their use is described in the CS4373A data sheet.
Analog Signals Description
OUT Precision differential analog output BUF Buffered differential analog output CAP Capacitor connection for internal anti-alias filter VREF Voltage reference analog inputs
Digital Signals Description
TDATA Delta-sigma test data input MCLK Clock input SYNC Synchronization input MODE[0..2] Test mode selection ATT[0..2] Attenuation range selection
2.2.4.1 Precision Output - DAC_OUT
The CS4373A test DAC has a precision output (DAC_OUT) that is routed to the input selection jumpers for each channel. This output is sensitive to loading, and on CDB5374 should only be jumper-ed into the INB inputs which do not have passive RC filter components installed. The input impedance of the INB am­plifier inputs are high enough that the precision output can be directly connected to the INB inputs of all channels simultaneously.
2.2.4.2 Buffered Output - DAC_BUF
The CS4373A test DAC has a buffered output (DAC_BUF) that is routed to the input selection jumpers for each channel. This output is less sensitive to loading than the precision outputs, and can be jumper­ed into either the INA or INB inputs without affecting performance. The buffered output can also drive a sensor attached to the input screw terminals, provided the sensor meets the impedance requirements specified in the CS4373A data sheet.
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CDB5374

2.2.5 Voltage Reference

A voltage reference on CDB5374 creates a precision voltage from the regulated analog supplies for the modulator and test DAC VREF inputs. Because the voltage reference output is generated relative to the negative analog power supply, VREF+ is near GND potential for bipolar power supplies.
Specification Value
Precision Reference - Linear Tech LT1019AIS8-2.5 Surface Mount Package Type SO-8 Output Voltage Tolerance +/- 0.05% Temperature Drift 10 ppm / degC Quiescent Current 0.65 mA Output Voltage Noise, 10 Hz - 1 kHz 4 ppm Ripple Rejection, 10 Hz - 200 Hz > 100 dB
2.2.5.1 VREF_MOD12, VREF_MOD34, VREF_DAC
The voltage reference output is provided to the CS5374 ∆Σ modulators and the CS4373A test DAC through separate low-pass RC filters. By separately filtering the voltage reference for each device, signal­dependent sampling of VREF by one device is isolated from other devices. Each vo ltage reference signal is routed as a separate differential pair from the large RC filter capacitor to control the sensitive VREF source-return currents and keep them out of the ground plane. In addition to the RC filter function, the 100 uF filter capacitor provides a large charge well to help settle voltage reference sampling transients.
RMS
2.2.5.2 Common Mode Bias
A buffered version of the voltage reference is created as a low-impedance common mode bias source for the analog signal inputs. The bias resistors connected between the buffered voltage reference and each analog signal input half depends on the sensor type and should be modified to match the sensor manu­facturer recommendations.
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CDB5374

2.3 Digital Hardware

2.3.1 Digital Filter

The CS5376A quad digital filter performs filtering and decimation of four delta-sigma bit streams from the CS5374 modulators. It also creates a delta-sigma bit stream output to create analog test signals in the CS4373A test DAC.
The CS5376A requires several control signal inputs from the external system.
Control Signals Description
RESETz Reset input, active low BOOT Microcontroller / EEPROM boot mode select TIMEB Time Break input, rising edge triggered CLK Master clock input, 32.768 MHz SYNC Master synchronization input, rising edge triggered
Configuration is completed through the SPI 1 port.
SPI1 Si gnal s De sc ri pt i on
SSIz Serial chi p select i nput, active low SCK1 Serial clock input MIS O M a st er in / sl av e out seri al d at a MO SI Mas ter out / slave in serial data SINTz Se rial acknowledge ou t put, acti ve l ow SSOz Serial chip select output (unused on CDB5374)
Data is collected through the SD port.
SD Port Signals Description
SDTKI Token input t o initiate an SD port tr ansac tion SDRDYz Data ready acknowledge, active low SDCLK Serial clock input SDDAT Serial data output SDTKO Token output (unused on CDB5374)
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Modulator ∆Σ data is input through the modulator interface.
Modulator Signals Description
MCLK Modulator clock output MCLK/2 Modulator clock output, half-speed MSYNC Modulator synchronization output MDATA[1..4] Modulator delta-sigma data inputs MFLAG[1..4] Modulator over-range flag inputs
Test DAC ∆Σ data is generated by the test bit stream generator.
Test Bit Stream Signals Description
TBSDATA Test DAC delta-sigma data output TBSCLK Test DAC clock output (unused on CDB5374)
Amplifier, modulator, and test DAC digital pins are controlled by the GPIO port.
CDB5374
GPIO Signals Description
GPIO[0..1]:MUX[0..1] Amplifier input mux selection GPIO[2..4]:GAIN[0..2] Amplifier gain / test DAC attenuation GPIO[5..7]:MODE[0..2] Test DAC mode selection GPIO[8]:PWDN Amplifier / modulator power down GPIO[9..10] Available general purpose input/output GPIO[11]:EECS Chip select for boot EEPROM
The secondary serial port (SPI 2) and boundary scan JTAG port are also on CDB5374.
SPI2 Signals Descriptio n
SCK2 Serial clock outp ut SO Serial data output SI[1..4] Serial data inputs
JTAG Signals Description
TRSTz J TAG rese t ( unu sed o n CDB5376) TMS J TAG te s t mode select (unused on CDB5376) TCK JTAG test clock input (unused on CDB5376) TDI JTA G test data input (unuse d on CDB 5376) TD O JTAG test data output (unused on CDB5376)
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CDB5374
2.3.1.1 MCLK Conversion to ACLK
The CS5376A digital filter creates the analog sampling clock used by the CS5374 ∆Σ modulators and CS4373A test DAC (MCLK). This clock has strict jitter requirements to guarantee the accu racy of analog­to-digital and digital-to-analog conversion, and so is carefully routed between the digital filter and modu­lators/test DAC.
2.3.1.2 Configuration - SPI1 Port
Configuration of the CS5376A digital filter is through the SPI 1 port by the on-board 8051 microcontroller, which receives commands from the PC evaluation software via the USB interface. Evaluation software commands can write/read digital filter registers, specify digital filter coefficients and test bit stream data, and start/stop digital filter operation. Alternately, the digital filter can automatically load configuration in­formation from an on-board serial EEPROM.
Configuration of the digital filter is selected by the BOOT signal from dip switch #1 (S5, #1). By default the BOOT signal is set low (S5, #1 - LO) to indicate configuration information is written by the microcontroller. If BOOT is set high (S5, #1 - HI), the digital filter attempts to automatically read configuration information from the serial EEPROM after reset.

2.3.2 Interface CPLD

A Xilinx CPLD is included on CDB5374 (XCR3128XL-10VQ100I) as an interface between the CS5376A digital filter and the microcontroller. By default the CPLD only passes through the interface signals, but can be reprogrammed to disconnect the on-board 8051 microcontroller and connect to another external microcontroller through the spare dual-row headers. Control signals taken off the CDB5374 board to an external microcontroller should pair with a ground return wire to maintain signal integrity.
Free software tools and an inexpensive hardware programmer for the Xilinx CPLD are available from the internet (http://www.xilinx.com port (J39) on CDB5374. Note that early versions of the Xilinx WebPack tools (7.1i SP1 and earlier) have a bug in the JEDEC programming file for the CPLD included o n CDB5374, and WebPack version 7.1i SP2 or later is required.
Included below is the default Verilog HDL file used by CDB5374 inside the interface CPLD. Comparing the input and output definitions of this file with the CPLD schematic pinout should demonstrate how sig­nals are selected and passed through from the microcontroller to the CS5374A digit al filter. Several signal connections to the CPLD are not defined in the default HDL file, but are routed to the CPLD on CDB5374 for convenience during custom reprogramming.
). The hardware programmer interfaces with the Xilinx JTAG programming
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CDB5374
/////////////////////////////////////////////////////////////////////////// // MODULE: CDB5376 top module // // FILE NAME: Top module for connecting CS5376 to C8051F320 // VERSION: 1.0 // DATE: Jan. 8, 2007 // COPYRIGHT: Cirrus Logic, Inc. // // CODE TYPE: Register Transfer Level // // DESCRIPTION: This module includes assignments for signals between // the serial port of Bismarck and the SLAB micro. // ///////////////////////////////////////////////////////////////////////////
module cdb5376 ( mosi_mc,
ssi_mc,
miso, drdy,
mosi, ssi,
////////////////// // input signals //////////////////
input sck_mc, mosi_mc, ssi_mc; input sdtki_mc, timeb_mc; input miso,drdy,sddat; input sync_mc, sync_pb, timeb_pb; input reset_pb, reset_ext; input timeb_ext, sync_ext;
sck_mc,
sdtki_mc, timeb_mc,
sddat, sync_mc, sync_pb, timeb_pb, reset_pb, reset_ext, timeb_ext, sync_ext,
miso_mc, drdy_mc, sck,
sdtki, timeb, sdclk, sync, reset );
cdb5376.v
////////////////// //output signals //////////////////
output miso_mc, drdy_mc; output sck, mosi, ssi; output sdtki,timeb,sdclk;
output sync, reset; ///////////////////////
// signal assignments ///////////////////////
assign sck = ssi_mc? 1'bz:sck_mc; assign sdclk = drdy? 1'bz:sck_mc; assign mosi = ssi_mc? 1'bz:mosi_mc; assign ssi = ssi_mc? 1'bz:ssi_mc; assign sdtki = sdtki_mc; assign drdy_mc = drdy; assign miso_mc = (drdy)? miso:sddat;
assign timeb = timeb_mc | timeb_pb | timeb_ext; assign sync = sync_mc | sync_pb | sync_ext; assign reset = reset_pb & reset_ext;
endmodule
Figure 3. CPLD Default Signal Assignments
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CDB5374

2.3.3 Digital Control Signals

The reset, synchronization, and timebreak signals to the CS5376A digital filter can be generated by push buttons, received from external inputs or generated by the on-board microcontroller. By default, the push button RESET_PB, SYNC_PB, and TIMEB_PB signals are connected through the interface CPLD to the CS5376A digital filter RESET, SYNC, and TIMEB inputs.
A four-position DIP switch on CDB5374 (S5) sets static digital control signals not normally changed during operation. The BOOT signal (S5, #1) controls how the CS5374A digital filter receives configuration data, either from a microcontroller or serial EEPROM.

2.3.4 Microcontroller

Included on CDB5374 is an 8051-type microcontroller with integrated hardware SPI and USB interf aces. This C8051F320 microcontroller is a product of Silicon Laboratories (http://www.silabs.com of the C8051F320 microcontroller are:
8051 compatibility – uses industry-standard 8051 software development tools In-circuit debugger – software development on the target hardware Internal memory – 16k flash ROM and 2k static RAM included on-chip
). Key features
Multiple serial connections – SPI, USB, I2C, and UART High performance – 25 MIPS maximum Low power – 0.6 mA @ 1 MHz w/o USB, 9 mA @ 12 MHz with USB Small size – 32 pin LQFP package, 9mm x 9mm Industrial temperature – full performance (including USB) from -40 C to +85 C Internal temperature sensor – with range violation interrupt capability Internal timers – four general purpose plus one extended capability Power on reset – can supply a reset signal to external devices Analog ADC – 10-bit, 200 kSps SAR with internal voltage reference Analog comparators – arbitrary high/low voltage compare with interrupt capability
The exact use of these features is controlled by embedded firmware. C8051F320 has dedicated pins for power and the USB connection, plus 25 general-purpose I/O pin s that
connect to the various internal resources through a programmable crossbar. Hardware connections on CDB5374 limit how the blocks can operate, so the port mapping of microcontroller resources is detailed below.
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