Cirrus Logic CDB5364 User Manual
Evaluation Board for CS5364
CDB5364
Features
! Single-Ended to Differential Analog Inputs
! 3.3 V Logic Interface
! Connection for DSP Serial I/O
! Windows®-Compatible CDB5364 Software
Supplied by Cirrus to Configure the
!
On-Board CS8406 to Generate S/PDIF and
EIAJ-340 Digital Audio
! Requires Only an Analog Signal Source, Power
Supplies and, optionally, a PC for a Complete
Analog-to-Digital-Converter Evaluation System
RS232
USB
CS5364
8051 Micro
Description
The CDB5364 evaluation board is an excellent means
for quickly evaluating the CS5364 24-bit, 192 kHz A/D
converter. Evaluation requires only a digital signal analyzer, an analog signal source, and a power supply.
On-board DIP switches configure the CS5364 in StandAlone mode, avoiding the need for a PC.
For software-based device configuration, the Control
Port mode is used by attaching a host PC to the Evaluation Board and executing the provided FlexGUI
software.
ORDERING INFORMATION
CDB5364 Evaluation Board
RCA
Jacks
http://www.cirrus.com
4
Analog
Input
Buffers
4
4
Control
I²C or SPI
CS5364 A/D
Ain+
Ain-
Clks/Data
Buffers
Audio
Clks/Data
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
FPGA
CS8406
AES/EBU
S/PDIF
Transmitter
S/PDIF
Output
Optical
Coaxial
SEPTEMBER '05
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TABLE OF CONTENTS
1. CDB5364 System Overview..................................................................................................................... 3
2. Quick-Start Guide..................................................................................................................................... 3
3. Detailed Board Features.................................................................. ........................................................ 3
3.1 Stand-Alone Evaluation ............................................................................................................ 3
3.1.1 S1 and S4 Switch Operation .................................................. ... ... .... ... ... ... ... .... ... ... ... .... . 4
3.2 Control-Port Evaluation ............................................................................................................ 5
3.3 FlexGUI Hi-Level View ............................................................................................................. 6
3.4 FlexGUI Low-Level View .......................................................................................................... 7
3.5 Bit Definitions ........................................................................................................................... 8
3.5.1 CS5364 Bits ....................................................................................................................8
3.5.2 FPGA Bits ....................................................................................................................... 8
4. CDB5364 Hardware................................................................................................................................. 9
4.1 Input and Output Connectors ................................................................................................... 9
4.2 Switches ................................................................................................................................. 10
4.3 User Configuration Jumpers .................................................................................................. 10
4.4 Reserved Factory Programming Jumpers ............................................................................. 10
4.5 Power Supply Circuitry ........................................................................................................... 11
4.6 Grounding and Power Supply Treatment ............................... ................................................ 11
4.7 FPGA Hardware ..................................................................................................................... 11
4.8 CS8406 S/PDIF Audio Transmitter ........................................................................................ 11
4.9 Serial Audio Interface ............................................................................................................. 11
4.10 Analog Input Buffer .............................. ... ... .... ... ....................................... ... ......................... 11
5. Schematics............................................................................................................................................. 12
6. Board Layout and Routing Plots ........................................................................................................... 21
7. Revision History..................................................................................................................................... 24
CDB5364
LIST OF FIGURES
Figure 1. Hi-Level FlexGUI View ................................................................................................................. 6
Figure 2. FlexGUI Low-Level Register View ............................................................................................... 7
Figure 3. FPGA Low-Level Bit View ............................................................................................................ 8
Figure 4. CS5364 (Schematic page 1) ...................................................................................................... 12
Figure 5. Clock Generation (Schematic page 2) ....................................................................................... 13
Figure 6. FPGA (Schematic page 3) ......................................................................................................... 14
Figure 7. Control Port (Schematic page 4) ................................................................................................ 15
Figure 8. Clock and Data Buffers (Schematic page 5) .............................................................................. 16
Figure 9. CD8406 S/PDIF Output (Schematic page 6) ............................................................................. 17
Figure 10. Analog Inputs 1 to 4 (Schematic page 7) ................................................................................. 18
Figure 11. Analog Inputs 5 to 8 (Schematic page 8) ................................................................................. 19
Figure 12. Power (Schematic page 9) ....................................................................................................... 20
Figure 13. Top Silkscreen ......................................................................................................................... 21
Figure 14. Top Layer ................................................................................................................................. 22
Figure 15. Bottom Layer ......................... ... ... ... ... .... ... ... ....................................... ...................................... 23
LIST OF TABLES
Table 1. CDB5364 Input and Output Connectors ....................................................................................... 9
Table 2. CDB5364 Switches ..................................................................................................................... 10
Table 3. User Jumpers .............................................................................................................................. 10
Table 4. CDB5364 Reserved Jumpers ..................................................................................................... 10
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CDB5364
1. CDB5364 SYSTEM OVERVIEW
The CDB5364 Evaluation Board provides an excellent means of quickly evaluating the CS5364. A digital audio interface transmitter (CS8406) provides an easy interface to digital audio signal analyzers, including the majority of
digital audio test equipment. Standard analog input and digital output conn ectors are included for quick and re liable
board setup. An on-board FPGA is used for confi guring the vari ous modes of the CS53 64. Graphica l User Interface
software is supplied by Cirrus Logic, which allows programming the CDB5364 when connected to a host PC run ning
Microsoft Windows
®
.
2. QUICK-START GUIDE
• Confirm that DIP switches S1 and S4 are in the closed (LO) position, pushed down to the right.
• Connect the following jumpers.
– J7 - Install 5 jumpers to the left side of J7, enabling the DIP switches to operate correctly.
– J81, J95 - Install jumpers to these positions, grounding XTI and XTO of the CS5364.
– J1 - Install a jumper at the +5 V position, allowing VA to be supplied by the +5 V supply.
• Install a 12.288 MHz canned Oscillator to socket Y1, providing a Master Timing Clock for the system.
• Install a jumper to J11 at the OSC position to enable the OSC drive buffer.
• Connect power supply common to the GND binding post. Connect +5 V, +12 V and -12 V to the binding
posts as marked on the board silkscreen
This configuration provides a completely operational 24-bit Analog-to-Digital-Converter evaluation system. The
CS5364 is operating as a Master Device in Single S peed Mod e with a 48 kHz sampling rate. Apply power and connect analog input signals of 1 Vrms maximum (full scale) to the RCA inputs jacks. S/PDIF Digital audio data is available for evaluation at the Optical and Coaxial outputs.
3. DETAILED BOARD FEATURES
The CDB5364 Evaluation Board supports both the Stand-Alone and Control Port modes of the CS5364. An FPGA
(U2) controls digital signal routing between the CS5 364, the CS8406 and the DSP I/O header. For user-friendly evaluation of the TDM interface, the FPGA will translate TDM data into PCM data and send it to the CS8406.
3.1 Stand-Alone Evaluation
In Stand-Alone mode, the CDB5364 runs without an external PC attached. In this mode, the FPGA controls
operation of the board by dynamically reading DIP switches (S1 and S4) after a cold power-up or a pushbutton board reset. Stand-Alone mode provides the most commonly used device settings. For additional
control of the CS5364, Control Port mode is used.
In Stand-Alone mode, as the DIP switches are repositioned , the FPGA sim ultaneously sets the app ropriate
pins on the CS5364 and CS8406 to keep them synchronized with regard to sampling speed and data format.
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3.1.1 S1 and S4 Switch Operation
DIP Switch S1 contains six switches that function as described below.
M1,M0 set the device Speed Mode
0x00 Single Speed Master
0x01 Double Speed Master
0x10 Quad Speed Master
0x11 Slave all speed
DIF1,DIF0 set the Digital Audio Interface Data form at
0x00 Left Justified
0x01 I²S
0x10 TDM 2-wire
0x11 TDM 4-wire
TDM1 and TDM0 support both TDM mode and PCM mode.
In TDM mode, TDM1 and TDM0 select two stereo pairs from a TDM stream, convert the data to Left-Jus-
tified PCM format then send the data to the CS8406 S/PDIF transmitter.
0x00 TDM Pair 1 (Channel 1, 2)
0x01 TDM Pair 2 (Channel 3, 4)
0x1x Reserved
CDB5364
In PCM mode, TDM1 and TDM0 select which SDOUT is sent to the CS8406.
0x00 SDOUT1 (Channel 1, 2)
0x01 SDOUT2 (Channel 3, 4)
0x1x Reserved
DIP Switch S4 contains two switches which function as described below.7
MDIV - divides the master clock by 2 when OPEN (HI).
CLKMODE - divides the master clock by 1.5 when OPEN (HI)
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3.2 Control-Port Evaluation
The CDB5364 is shipped with a Cirrus Logic designed Microsoft Windows-based program that allows full
control over the CS5364 internal registers. This software pr ogram is calle d the FlexGUI, a nd it is loade d by
executing the FlexLoader.exe file. Hardware interface to the Fl exGUI is provide d by connecting an RS-232
cable or a USB cable between a host PC and the CDB5364. Once the FlexGUI is loaded, the Evaluation
Board DIP switches are ignored, and all register settings are available for re ading and writing using software
control. Testing configurations may be quickly reproduced by using the Fle xGUI to save and restore unique
register settings.
Configure the board for Control Port op er a tion using the instructions that follow.
• Connect jumpers.
– J7 - Install 5 jumpers to the left side of J7, enabling the I²C control interface.
– J81, J95 - Install jumpers to these positions, grounding XTI and XTO of the CS5364.
– J9 - Install a jumper at the +5 V position, allowing VA to be supplied by the +5 V supply (VA may be
externally supplied at the VA binding post by moving jumper J9 to the VA EXT position).
• Add an oscillator of choice to socket Y1 to provide a Master Timing Clock for the system. A crystal may
also be used by removing the canned oscillator and jumpers J81, J95 and J11. The CDB5364 Evaluation
Board is shipped with 39 pF loading capacitors for crystal-based oscillators. Soldering pads are provided
on the board for users that require third overtone tank circuit operation or different loading capacitors.
CDB5364
• Connect the power supply common to the GND binding post. Connect +5 V, +12 V and -12 V to the bind-
ing posts as marked on the board silkscreen.
The FlexGUI provides two convenient views of the CDB5364 Evaluation Board settings. The default view is
a high-level functional mapping of settings. The second view is a lower -level register map view for progr amming at the bit level. Each view is synchronized with the other view, so that changing a setting at one level
will also change the corresponding setting in the alternate level.
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3.3 FlexGUI Hi-Level View
The Cirrus Logic FlexGUI defaults to the Hi-Level View as shown in Figure 1. This view provides functionally
grouped control over the CS5364, reducing the need to memorize the exa ct location of bit settings. Any register may be modified at any time; however, the effect of changes made to the CS53 64 is gated off u ntil the
Control Port Bit is enabled.
When switching to TDM mode, the CS8406 Clock and Date source (Board Con trol Panel) must be chang ed
prior to changing the CS5364 SAI format. This sequential orderin g re se ts th e F PG A t o a ss ur e th at it t ime d
properly with the CS5364 TDM packet stream.
CDB5364
Figure 1. Hi-Level FlexGUI View
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3.4 FlexGUI Low-Level View
The Low-level Register Map view provides direct control over the CS5364, the FPGA and GPIO settings
that change the CS5364 device address. Select the desired device tab; then select and modify any writeregister values. Register modification is always a READ-WRITE-READ operation and is usable at both the
byte or bit level. For byte-level control, type the required hex value in the desired register field numerical
box. For bit-level control, click the corresponding graphical push-button in the desired register field or use
the pull-down menu to access and change the bit values.
CDB5364
Figure 2. FlexGUI Low-Level Register View
When the CS5364 is put in Control Port mode , the DIP switches are ignored and configuration is determined
by the register bits. When placed back in Stand-Alone mode, the DIP switches regain board co ntrol. Exiting
Control Port mode is achieved by stopping the Flex GUI program. Once the prog ram is stopped, about th ree
seconds later, Stand-Alone mode is established.
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3.5 Bit Definitions
3.5.1 CS5364 Bits
The Low-Level view of the FlexGUI provides the full register set of the CS5364 under the CS5364 tab.
The CS5364 datasheet provides full details of internal register operation.
3.5.2 FPGA Bits
FPGA Register 0x00 is non-functional and only contains the revision code of the FPGA.
FPGA Register 0x01 is a functional register that provides the following functionality.
CDB5364
Figure 3. FPGA Low-Level Bit View
Fs_Range1,0 set the device Speed Mode. These bits need to be changed when using the Serial Audio
Interface of the DSP header to communicate with external equipment.
0x00 Single Speed Master
0x01 Double Speed Master
0x10 Quad Speed Master
0x11 Slave all speed
AudioFMT1,0 set the Serial Audio Interface format when attaching the Serial Audio Interface of the DSP
header to external equipment.
0x00 Left Justified
0x01 I²S
0x10 TDM 2-wire
0x11 TDM 4-wire
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