Cirrus Logic CDB5351 User Manual
Evaluation Board for CS5351
CDB5351
Features
z Demonstrates recommended layout and
grounding arrangements
z CS8406 generates S/PDIF, and EIAJ-340
compatible digital audio
z Requires only an analog signal source and
power supplies for a complete Analog-toDigital-Converter system
Description
The CDB5351 evaluation board is an excellent means
for quickly evaluating the CS5351 24-bit, stereo A/D converter. Evaluation requires a digital signal analyzer, an
analog signal source, and a power supply.
Also included is a CS8406 digital audio interface transmitter which generates S/PDIF, and EIAJ-340
compatible audio data. The digital audio data is available
via RCA phono and optical connectors.
ORDERING INFORMATION
CDB5351 Evaluation Board
ANALOG
INPUT
Cirrus Logic, Inc.
www.cirrus.com
CS5351
AES/EBU
TRANSMITTER
I/O FOR
CLOCKS
AND DATA
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
CS8406
S/PDIF
S/PDIF
OUTPUT
MAY ‘03
DS565DB3
1
TABLE OF CONTENTS
1. CDB5351 SYSTEM OVERVIEW .............................................................................................. 3
2. CS8406 DIGITAL AUDIO TRANSMITTER ............................................................................... 3
3. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 3
4. POWER SUPPLY CIRCUITRY ................................................................................................. 3
5. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 3
6. ANALOG INPUT FILTER ......................................................................................................... 3
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .......................................................................... 5
Figure 2. Differential Analog Audio Input......................................................................................... 6
Figure 3. CS5351 ............................................................................................................................ 7
Figure 4. Level Shifters ................................................................................................................... 8
Figure 5. I/O for Clocks/Data........................................................................................................... 9
Figure 6. CS8406 Digital Audio Interface ........................................................................................ 9
Figure 7. Reset Circuit................................................................................................................... 10
Figure 8. Power Circuit.................................................................................................................. 11
Figure 9. Top Layer Silkscreen ..................................................................................................... 12
Figure 10. Top Layer ..................................................................................................................... 13
Figure 11. Bottom Layer ................................................................................................................ 14
CDB5351
LIST OF TABLES
Table 1. System Connections ........................................................................................................4
Table 2. CDB5351 Jumper and Switch Settings ............................................................................ 4
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain
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sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for
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this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other
intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of
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to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.
2 DS565DB3
CDB5351
1. CDB5351 SYSTEM OVERVIEW
The CDB5351 evaluation board is an excellent means of quickly evaluating the CS5351. The CS8406 digital audio interface transmitter provides an easy interface to digital audio signal analyzers including the
majority of digital audio test equipment.
The CDB5351 schematic has been partitioned into 7 schematics shown in Figure 2 through Figure 8.Each
partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system dia-
gram also includes the interconnections between the partitioned schematics.
2. CS8406 DIGITAL AUDIO TRANSMITTER
The system generates and encodes standard S/PDIF data using a CS8406 Digital Audio Transmitter
(See Figure 6). The outputs of the CS8406 are RS422 compatible differential line drivers. The CS8406
supports both Left Justified and I
the CS8406 is included in the CS8406 datasheet.
3. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, J13.
The schematic for the clock/data input/output is shown in Figure 5.
The CDB5351 allows some flexibility as to the generation of the clocks. When the CS5351 and CS8406
are in slave mode, the SCLK and LRCK must be provided via the header, J13. MCLK must be generated
from the on board oscillator, Y1. This oscillator is socketed to allow other frequency oscillators to be used.
2
S data formats, as determined by the DIP switch, S2. A description of
4. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts (-12V, +12V, VD, VL, GND, +5 V),
see Figure 8. -12V and +12V supply the input amplifiers while the VD input supplies the VD pin of the
CS5351. VL supplies power to the VL pin of the CS5351 and to the level shifter circuits. The +5 V input
supplies power to the +5 V digital circuitry and the VA pin of the CS5351.
5. GROUNDING AND POWER SUPPLY DECOUPLING
The CS5351 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 3 details the power distribution used on this board. The decoupling capacitors are located
as close to the CS5351 as possible. Extensive use of ground plane fill in the evaluation board yields large
reductions in radiated noise.
6. ANALOG INPUT FILTER
The CDB5351 implements a single-ended analog input buffer, as shown in Figure 2. Note that there is no
attenuation associated with the input buffer, so a 1 Vrms input applied at the RCA connectors will provide
a full-scale 1 Vrms input to the CS5351.
DS565DB3 3
CDB5351
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
-12V Input -12V power for the input op-amps
+12V Input +12V power for the input op-amps
VD Input +3.3V to +5V power for the CS5351
VL Input +2.5V to +5V power for the CS5351
GND Input Ground connection from power supply
+5V Input + 5 Volt power
AINL Input Analog input left channel
AINR Input Analog input right channel
Optical Output Output Digital audio output
Coax Output Output Digital audio output
Table 1. System Connections
JUMPER/SWITCH PURPOSE POSITION FUNCTION SELECTED
J7 VD Power Source ADJ
*+3.3V
+5V
J8 VL Power Source ADJ
*+3.3V
+5V
J13 Input/Output for
clocks/data
S1 Reset for the CDB5351 - -
S2 CDB5351 Configuration M1/M0 Open
--
*ClosedHiLow
ADC *Open
Closed
HPF
DIV Open
IO_HDR Open
DIF Open
8406 Open
Open
*Closed
*Closed
*Closed
*Closed
*Closed
Power from the Binding Post (J3)
Power from the +3.3V Regulator
Power from the +5V Supply
Power from the Binding Post (J4)
Power from the +3.3V Regulator
Power from the +5V Supply
CS5351 in Master mode
CS5351inSlavemode
High-pass filter is disabled
High-pass filter is enabled
MCLK is divided by two internally by the
CS5351
MCLK is not divided internally by the
CS5351
Header J3 is an input for clocks
Header J3 is an output for clocks and
data
Digital interface format set to I
Digital interface format set to Left Justified
CS8406 in Master mode
CS8406inSlavemode
2
S
Table 2. CDB5351 Jumper and Switch Settings
* denotes default factory settings
4 DS565DB3
CDB5351
R
O
T
A
7
L
L
I
G
I
C
F
S
AUDIO
CS8406
DIGITAL
FIG 6
INTERFACE
CRYSTAL
O
RESET
CIRCUIT
CLOCKS
AND DATA
FIG 5
Figure 1. System Block Diagram and Signal Flow
I/O FOR
FIG 4
LEVEL
SHIFTER
FIG 7
3
G
I
CS5351
F
T
U
P
N
I
G
2
O
G
L
I
A
F
N
A
DS565DB3 5
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