Evaluation Board for CS5345
CDB5345
Features
z Single-ended Analog Inputs
z Single-ended Analog Outputs
z CS8406 S/PDIF Digital Audio Transmitter
z Header for Optional External Software
Configuration of CS5345
z Header for External PCM Serial Audio I/O
z 3.3 V Logic Interface
z Pre-defined Software Scripts
z Demonstrates Recommended Layout and
Grounding Arrangements
z Windows
to Configure CS5345 and Inter-board
Connections
ORDERING INFORMATION
CDB5345 Evaluation Board
®
Compatible Software Interface
Description
The CDB5345 evaluation board is an excellent means
for evaluating the CS5345 ADC. Evaluation requires an
analog signal source and analog/digital analyzer, and
power supplies. A Windows
must be used to evaluate the CS5345.
System timing for the I²S, Left-Justified and Right-Justified interface formats can be provided by the CS5345,
the CS8406, or by a PCM I/O stake header with an external source connected.
RCA phono jacks are provided for the CS5345 analog inputs and outputs. Digital data input is available via RCA
phono or optical connectors to the CS8406.
The Windows
®
software provides a GUI to make configuration of the CDB5345 easy. The software
communicates through the PC’s serial port to configure
the control port registers so that all features of the
CS5345 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
®
PC compatible computer
I
Cirrus Logic, Inc.
www.cirrus.com
Passive Input Filter
Active Input Filter
Microphone Input
Control Port Interface
M
U
X
CS5345
FPGA
Sub-clocks and Data
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
Active Output Filter
Test Points
Master Clock
Canned
Oscillator
Header
CS8406
FEB ‘05
DS658DB1
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4
1.1 Power ..... ....................................... ... ... ... ....................................... ... .... ... ... ........................4
1.2 Grounding and Power Supply Decoupling ......................................................................... 4
1.3 CS5345 Audio ADC ...........................................................................................................4
1.4 CS8406 Digital Audio Transmitter ......................................................................................4
1.5 FPGA .................................................................. .... ... ... ... .... ... ... ........................................ 4
1.6 Canned Oscillator ......................................... ... ... .... ... ... ... ....................................... ... ........ 4
1.7 External Control Headers ...................................................................................................5
1.8 Analog Inputs ............ .... ... ... ....................................... ... ... .... ..............................................5
1.9 Analog Outputs ....................................................................... ... ... ... .... ... ... ........................5
1.10 Serial Control Port ............................................................................................................ 5
1.11 USB Control Port ............................................................................................................. 5
2. SYSTEM CLOCKS AND DATA ................................................................................................ 6
2.1 Clock Routing ................................... ... ... ....................................... ... .... ... ...........................6
2.2 Data Routing ............. .... ... ... ... .... ...................................... .... ... ... ... ... .... ..............................6
3. PC SOFTWARE CONTROL ..................................................................................................... 7
3.1 CDB5345 Controls Tab ....... ... .... ... ... ... .......................................... ..................................... 7
3.2 Register Maps Tab ..................................... ... ... ... .... ... ... ....................................... ... ... ... ..... 8
3.3 Pre-Configured Script Files . ... .... ... ... ... ... .... ... ... ....................................... ... ... .... ... ... ... ... .....8
3.3.1 Oscillator Clock - ADC Ch 1 In to In to SPDIF & PGA Out .............................. .... . 8
3.3.2 Oscillator Clock - ADC Ch 2 In to In to SPDIF Out .................... ... ... .... ... ... ... ... .....9
4. FPGA REGISTER QUICK REFERENCE ...............................................................................10
5. FPGA REGISTER DESCRIPTION .........................................................................................11
6. CDB CONNECTORS, JUMPERS, AND SWITCHES .............................................................13
7. CDB BLOCK DIAGRAM ..................................................................................................... 15
8. CDB SCHEMATICS ............................................................................................................... 16
9. CDB LAYOUT ........................................................................................................................ 24
10. REVISION HISTORY ............................................................................................................ 27
CDB5345
2 DS658DB1
LIST OF FIGURES
Figure 1. CDB5345 Controls Tab.................................................................................................... 7
Figure 2. Register Maps Tab........................................................................................................... 8
Figure 3. Block Diagram................................................................................................................ 15
Figure 4. CS5345.......................................................................................................................... 16
Figure 5. Analog Inputs................................................................................................................. 17
Figure 6. Analog Outputs.............................................................................................................. 18
Figure 7. S/PDIF Output................................................................................................................ 19
Figure 8. Control Port.................................................................................................................... 20
Figure 9. FPGA............................................................................................................................. 21
Figure 10. Discrete Clock Routing and Level Shifting................................................................... 22
Figure 11. Power........................................................................................................................... 23
Figure 12. Silk Screen................................................................................................................... 24
Figure 13. Topside Layer.............................................................................................................. 25
Figure 14. Bottom side Layer........................................................................................................ 26
LIST OF TABLES
Table 1. MCLK Source.................................................................................................................. 11
Table 2. Subclock Source............................................................................................................. 12
Table 3. CS8406 SDIN Source.....................................................................................................12
Table 4. System Connections.............................................................. ... ... ... .... ... ... ... .... ............... 13
Table 5. System Jumper Settings..................................................................... ... ... ... .... ... ............14
Table 6. Revision History.............................................................................................................. 27
CDB5345
DS658DB1 3
CDB5345
1. SYSTEM OVERVIEW
The CDB5345 evaluation board is an excellent means for evaluating the CS5345 ADC. Analog and digital audio signal interfaces are provided, an on-board FPGA is used for easily configuring the evaluation platform, and a 9-pin
serial cable is included for use with the supplied Windows
The CDB5345 schematic set is shown in Figures 4 through 11. The CDB5345 is assembled on the printed wire
board designed for the CDB4245, with a number of components un-populated. These un-populated components
have been removed from the included schematic set for clarity. For a complete schematic set, see the CDB4245
data sheet.
1.1 Power
Power must be supplied to the evaluation board through the red +5.0V binding post. On-board regulators
provide 3.3 V, 2.5 V, and 1.8 V supplies. Appropriate supply levels for powering VA, VD, VLS, and VLC are
set by a series of jumpers (see Table 5 on page 14). All voltage inputs must be referenced to the single black
binding post ground connector (see Table 4 on page 13).
WARNING: Please refer to the CS5345 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS5345 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 3 on page 15 provides an overview of the connections to the CS5345. Figure 12 on page 24
shows the component placement. Figure 13 on page 25 shows the top layout. Figure 14 on page 26 shows
the bottom layout. The decoupling capacitors are located as close to the CS5345 as possible. Extensive use
of ground plane fill in the evaluation board yields large reductions in radiated noise.
®
configuration software.
1.3 CS5345 Audio ADC
A complete description of the CS5345 is included in the CS5345 product data sheet.
The required configuration settings of the CS5345 are made in its control port registers, accessible through
the CS5345 tab of the Cirrus Logic FlexGUI softwar e.
Clock and data source selections are made through the control port of the FPGA. Basic routing selections
can be made using the CS5345 Controls tab in the GUI software application. Advanced options are accessible through the Board Configuration sub-tab on the Register Maps tab of the Cirrus Logic FlexGUI software. Refer to the FPGA register descriptions sections beginning on page 11.
1.4 CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter (Figure 7 on page 19) and a discussion of the digital audio
interface are included in the CS8406 data sheet.
The CS8406 converts the PCM data generated by the CS5345 to the standard S/PDIF data stream. The
CS8406 can operate in either master or slave mode, accepts 128 Fs, 256 Fs, 384 Fs, and 512 Fs master
clocks on the OMCK input pin, and can operate in the Left-Justified, I²S, Right-Justified 16-bit, and RightJustified 24-bit interface formats.
The most common operations of the CS8406 may be controlled via the CDB5345 Controls tab in the GUI
software application. Advanced option s are accessibl e through the CS8406 sub-tab on the Register Maps
tab of the Cirrus Logic FlexGUI software.
1.5 FPGA
The FPGA handles both clock and data routing on the CDB5345. Clock and data routing selections made
via the CDB5345 Controls tab in the GUI will be handled by the FPGA with no user interv ention required.
For advanced information regarding the internal registe rs and oper ation of the F PGA, see sections 4 and 5
beginning on page 10.
1.6 Canned Oscillator
A canned oscillator, Y1, is available to provide a master clock source to the CDB5345.
4 DS658DB1
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with
a 12.2880 MHz crystal oscillator populated.
1.7 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the headers J10, and
J17.
The 8-pin, 2 row header, J10, provides access to the serial audio signals required to interface to the serial
audio port of the CS5345 with a DSP (see Figure 10 on page 22).
The direction of the signals on header J10 can be configured using the controls located within the Board
Controls group box on the CDB5345 Controls tab in the provided GUI software.
The 15-pin, 3 row header, J17, allows the user bidirectional access to the SPI/I
removing all the shunt jumpers from the “PC” position. The user ma y then choose to connect a ribbon cable
to the “EXTERNAL CONTROL” position. A single “GND” row for the ribbon cable’s ground connection is provided to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user
choose to use the CDB for the I
2
C power rail.
1.8 Analog Inputs
RCA connectors supply the CS5345 analog inputs through single-ended, unity gain, active or passive circuits. Refer to the CS5345 data sheet for the ADC full-scale level.
A 4-pin CD-ROM type header is provided for easily connecti ng the analog outputs from a CD-ROM drive to
the analog inputs of the CS5345.
CDB5345
2
C control signals by simply
1.9 Analog Outputs
The CS5345 PGA analog outputs are routed through a two-pole active filter. The output of the filter is connected to RCA jacks for easy evaluation.
1.10 Serial Control Port
A graphical user interface is included with the CDB5345 to allow easy manipulation of the registers in the
CS5345, CS8406, and FPGA. See the device-specific data sheets for the CS5345 and CD8406 internal register descriptions. The internal register map for the FPGA is located in section 4 on page 10.
Connecting a cable to the RS-232 connector (J42) and launching the Cirrus Logic FlexGUI software (FlexLoader.exe) will enable the CDB5345.
Refer to “PC Software Control” on page 7 for a description of the Graphical User Interface (GUI).
1.11 USB Control Port
The USB control port connector (J37) is currently unavailable.
DS658DB1 5
CDB5345
2. SYSTEM CLOCKS AND DATA
The CDB5345 implements comprehensive clock routing capabilities. Configuration of the clock routing can be easily
achieved using the controls within the Board Controls group box on the CDB5345 Controls tab in the GUI software
application.
2.1 Clock Routing
The master clock signal (MCLK) may be sourced from the canned oscillator (Y1) or the PCM1 I/O header
(J10)
The sub-clock signals (SCLK and LRCK) may be sourced from the CS5345 in m aster mode, th e CS8406 in
master mode, or the PCM1 I/O header.
Clock routing configuration is a chieved using the MCLK Source and Subclock Source controls within the
Board Controls group box on the CDB5345 Controls tab in the GUI software application.
2.2 Data Routing
The serial data output of the CS5345 is routed to both the CS8406 S/PDIF transmitter and the PCM1 I/O
header. No user configuration of the serial data routing is required.
6 DS658DB1
CDB5345
3. PC SOFTWARE CONTROL
The CDB5345 is shipped with a Microsoft Windows® based graphical user interface which allows control over the
CS5345, CS8406, and FPGA. The board control software communicates with the CDB5345 over the RS-232 interface using the PC’s COM1 port.
To use the board control software, the contents of the included CD-ROM should fir st be copied to a directory on the
PC’s local disk. If applied, the Read Only attribute should be removed from all files. Once the appropriate cable has
been connected between the CDB5345 and the host PC, load FlexLoader.exe from the Software directory. When
the software loads, all devices will be reset to their default reset state.
The GUI’s File menu provides the ability to save a nd load script file s contain ing all o f t he registe r setting s. Pr e-configured script files are provided for basic functionality. Refer to “Pre-Configured Script Files” on page 8 for details.
3.1 CDB5345 Controls Tab
The CDB5345 Controls tab provides a high-level intuitive interface to many of the configuration options of
the CS5345 and CDB5345. The controls within the ADC/PGA Controls grou p box control the inter nal registers of the CS5345. The controls within the Board Cont rols group box co ntrol the board level clock and data
routing on the CDB5345.
Figure 1. CDB5345 Controls Tab
DS658DB1 7
3.2 Register Maps Tab
The Register Maps tab provides low level control over the register level settings of the CS5345, CS8406,
and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise or bytewise. For bit-wise, click the appropriate push button for the desired bit. Fo r byte-wise, the desired h ex value
can be typed directly in the register address box in the register map.
CDB5345
Figure 2. Register Maps Tab
3.3 Pre-Configured Script Files
Pre-configured script files are provided with the CDB5345 to allow easy initial board bring-up. The board
configurations stored within these files are described in sections 3.3.1 - 3.3.2.
3.3.1 Oscillator Clock - ADC Ch 1 In to In to SPDIF & PGA Out
Using the pre-configured script file named “Oscillator Clock - ADC Ch 1 In to SPDIF & PGA Out.txt”, an analog input signal applied to channel 1 of the CS5345 input multiplexer will be digitized by the ADC, transmitted in S/PDIF format by the CS8406, and will be output through the active output filter and RCA jacks.
The canned oscillator is the source of MCLK. The CS5345 is the sub-clock master to the CS8406 and the
PCM1I/O header.
8 DS658DB1
CDB5345
3.3.2 Oscillator Clock - ADC Ch 2 In to In to SPDIF Out
Using the pre-configured script file named “Oscillator Clock - ADC Ch 2 In to SPDIF Out.txt”, an analog input
signal applied to channel 2 of the CS5345 input multiplexer will be digitized by the ADC and transmitted in
S/PDIF format by the CS8406. No signal will be output through the active output filter and RCA jacks.
The canned oscillator is the source of MCLK. The CS5345 is the sub-clock master to the CS8406 and the
PCM1I/O header.
DS658DB1 9
CDB5345
4. FPGA REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function 7 6 5432 1 0
01h
02h
03h
04h
05h
Code Rev. ID
MCLK Source
Subclock
Source
Reserved
Transmitter
SDIN Source
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0
xxxxxx x x
Reserved Reserved Reserved Reserved Reserved Reserved Reserved MCLK
001000 0 0
Reserved Reserved Reserved Reserved Reserved Reserved SUBCLK1 SUBCLK0
000100 0 1
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
000000 0 0
Reserved Reserved Reserved CS8406 Reserved Reserved Reserved Reserved
000100 0 1
10 DS658DB1
CDB5345
5. FPGA REGISTER DESCRIPTION
5.1 CODE REVISION ID - ADDRESS 01H
76543210
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0
Function:
Identifies the revision of the FPGA code. This register is Read-Only.
5.2 MCLK SOURCE CONTROL - ADDRESS 02H
76543210
Reserved Reserved Reserved Reserved Reserved Reserved Reserved MCLK
5.2.1 MCLK SOURCE (BIT 0)
Default = 0
Function:
This bit selects the source of the CS5345 MCLK signal. Table 1 shows the available settings.
Table 1. MCLK Source
MCLK MCLK Source
0 Canned Oscillator
1 M1 position on PCM1 I/O Header
DS658DB1 11
CDB5345
5.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H
76543210
Reserved Reserved Reserved Reserved Reserved Reserved SUBCLK1 SUBCLK0
5.3.1 SUBCLOCK SOURCE (BITS 1:0)
Default = 01
Function:
This bit selects the source of the CS5345 SCLK and LRCK signals. Table 2 shows the available settings.
Table 2. Subclock Source
SUBCLOCK1 SUBCLOCK Subclock Source
0 0 - CS5345 is Master
- PCM I/O Header Subclocks are Output from CS5345
0 1 - CS5345 is Slave to CS8406
- PCM I/O Header Subclocks are Output from CS8406
1 0 - CS5345 is Slave to Header
11 Reserved
- CS8406 is Slave to CS5345
- CS8406 is Master
- CS8406 is Slave to Header
- PCM I/O Header Subclocks are an Input
5.4 TRANSMITTER SDIN SOURCE CONTROL - ADDRESS 05H
76543210
Reserved Reserved Reserved CS8406 Reserved Reserved Reserved Reserved
5.4.1 CS8406 SDIN SOURCE (BIT 4)
Default = 0
Function:
These bit selects the source of the CS8406 SDIN signal. Table 3 shows the available settings.
Table 3. CS8406 SDIN Source
CS8406 CS8406 SDIN Source
0Reserved
1 CS5345 SDOUT
12 DS658DB1
6. CDB CONNECTORS, JUMPERS, AND SWITCHES
Reference
CONNECTOR
+5V J1 Input
GND J2 Input
S/PDIF TX J15 Output
S/PDIF TX OPT2 Output
RS232 I/O J42 Input/Output
USB I/O J37 Input/Output
PCM1 I/O J10 Input/Output
CONTROL J17 Input/Output
MICRO JTAG J36 Input/Output
FPGA-JTAG J18 Input/Output
MICRO RESET S2 Input
PROGRAM FPGA S1 Input
PINA
PINB
AINA
AINB
MICIN1
MICIN2
AOUTA
AOUTB
Designator INPUT/OUTPUT SIGNAL PRESENT
+5.0 V Power Supply
Ground Reference
CS8406 digital audio output via coaxial cable
CS8406 digital audio output via optical cable
Serial connection to PC for SPI / I2C control port signals
USB connection to PC for SPI / I2C control port signals.
Not Available.
I/O for Serial Audio Clocks & Data
I/O for external SPI / I2C control port signals.
I/O for programming the micro controller (U46).
I/O for programming the FPGA (U35).
Reset for the micro controller (U46).
Reset for the FPGA (U35).
J38
J39
J40
J41
J21
J34
J14
J16
Input RCA phono jacks for analog input signal to CS5345. Pas-
sive input filter.
Input RCA phono jacks for analog input signal to CS5345. Active
input buffer.
Input
Output
1/8“ TRS jacks for microphone input.
RCA phono jacks for PGA analog outputs. Active output
buffer.
Table 4. System Connections
CDB5345
DS658DB1 13
JUMPER PURPOSE POSITION FUNCTION SELECTED
J3 Selects the source of voltage for the VLC
supply.
J4 Selects the source of voltage for the VD
supply
J5 Selects the source of voltage for the VLS
supply.
J6 Selects the source of voltage for the VA
supply
J19
J20
J22 - J33 Maps the passive and active input circuits
Select the input type for channel 4 of the
CS5345 ADC input multiplexer.
to the CS5345 input multiplexer channels.
*Default factory settings
+1.8 V
+2.5 V
+3.3 V
+5 V*
+3.3 V
+5 V*
+1.8 V
+2.5 V
+3.3 V
+5 V*
+3.3 V
+5 V*
Line Input*
Mic Input
Passive Filter*
Active Filter
Voltage source is +1.8 V regulator.
Voltage source is +2.5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Voltage source is +1.8 V regulator.
Voltage source is +2.5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Select RCA input multiplexer as source.
Select TRS inputs as source.
Passive filter mapped to input MUX channel.
Active filter mapped to input MUX channel.
CDB5345
Table 5. System Jumper Settings
14 DS658DB1
7. CDB BLOCK DIAGRAM
CDB5345
Canned
Test Points
Active Output Filter
Master Clock
CS5345
Oscillator
Header
CS8406
FPGA
Sub-clocks and Data
Figure 3. Block Diagram
X
U
M
Passive Input Filter
DS658DB1 15
Active Input Filter
Microphone Input
Control Port Interface
8. CDB SCHEMATICS
CDB5345
Figure 4. CS5345
16 DS658DB1
CDB5345
Figure 5. Analog Inputs
DS658DB1 17
CDB5345
Figure 6. Analog Outputs
18 DS658DB1
CDB5345
Figure 7. S/PDIF Output
DS658DB1 19
CDB5345
Figure 8. Control Port
20 DS658DB1
CDB5345
Figure 9. FPGA
DS658DB1 21
CDB5345
Figure 10. Discrete Clock Routing and Level Shifting
22 DS658DB1
CDB5345
Figure 11. Power
DS658DB1 23
9. CDB LAYOUT
CDB5345
Figure 12. Silk Screen
24 DS658DB1
CDB5345
Figure 13. Topside Layer
DS658DB1 25
CDB5345
Figure 14. Bottom side Layer
26 DS658DB1
10.REVISION HISTORY
Revision Date Changes
DB1 February 2005 Initial Release
Table 6. Revision History
CDB5345
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the infor-
mation is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain
the latest version of relevant information t o verify, before placing orders, that inf ormation being relied on is curre nt and complete. All products are
sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification,
and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any item s, or f or i nf ring eme nt of patents or o t her r ig hts of t hird partie s. Th is do cum ent i s th e p roper t y o f Cirrus and by furnishing
this information, Cirrus g rants no license, express or implied under an y patents, mask work rights, cop yrights, trademarks, tr ade secrets or other
intellectual property rights. Cirr us own s th e copy ri gh ts associ at ed w ith t he inf o rmati o n con tained he re in an d gi ves co nse nt for c opi e s to be mad e of
the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend
to other copying such as copyin g for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERT AIN APPLICA TIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED
OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY,
AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND
MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER
OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRIT ICAL APPL ICATIONS, CUSTOMER AGREES,
BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY , INCLUDING A TT ORNEYS' FEES AND COSTS, THA T MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE
USES.
Cirrus Logic, Cirrus, the Cirr us Logic log o designs, an d Popguard are tradema rks of Cirru s Logic, Inc. All other br and and prod uct names in this doc ument may be trademarks or service mar ks of their respective owners.
Windows is a registered trademark of Microsoft Corporation.
DS658DB1 27
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