Evaluation Board for CS43L22
CDB43L22
Features
Analog Passthrough Input
– Four Stereo Line Input Jacks
– Channel Mixer
Analog Output
– Stereo Headphone Jack w/ HP Detect
Capability
– Speaker Output via Differential Stereo
PWM Terminals and Audio Jacks
8- to 96-kHz S/PDIF Interface
– Optical and RCA S/PDIF Input Jacks
– CS8416 Digital Audio Receiver
I/O Stake Headers
– External Control Port Accessibility
– External DSP Serial Audio I/O Accessibility
Multiple Power Supply options via Battery or
External Power Supplies.
1.8 V to 3.3 V Logic Interface
Description
Using the CDB43L22 evaluation board is an ideal way
to evaluate the CS43L22. Use of the board requires an
analog/digital signal source, an analyzer and power
supplies. A Windows
required in order to configure the CDB43L22.
System timing can be provided by the CS8416, by the
CS43L22 with supplied master clock, or via an I/O stake
header with a DSP connected. 1/8th inch audio jacks
are provided for the analog passthrough inputs and
HP/Line outputs. Two pairs of banana jacks and an additional pair of 1/8th inch audio jacks are provided to
monitor the stereo differential speaker PWM output
from the CS43L22. Digital input connections are via
RCA phono or optical connectors to the CS8416
(S/PDIF Rx).
The Windows-based software GUI provided makes
configuring the CDB43L22 easy. The software communicates through the PC’s USB port to configure the
board and FPGA registers so that all features of the
CS43L22 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
PC-compatible computer is also
FlexGUI S/W Control - Windows
®
Compatible
– Pre-Defined & User-Configurable Scripts
USB
µ controller
PLL
FPGA
SRC
http://www.cirrus.com
S/PDIF Input
(CS8416)
Clk/Data
(CS8421)
ORDERING INFORMATION
CDB43L22 Evaluation Board
Reset
I2C Interface
Oscillator
(socket)
CS43L22
PSIA Input
Header
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
External System
Input Header
Reset
Analog
Passthrough
Input
Speaker
Outputs
Analog Output
(Line + Headphone)
OCTOBER '07
DS792DB1
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................. 4
1.1 Power ............................................................................................................................................... 4
1.2 Grounding and Power Supply Decoupling ....................................................................................... 4
1.3 FPGA ............................................................................................................................................... 4
1.4 CS43L22 .......................................................................................................................................... 4
1.5 CS8416 Digital Audio Receiver ........................................................................................................ 5
1.6 Oscillator .......................................................................................................................................... 5
1.7 I/O Stake Headers ........................................................................................................................... 5
1.8 Analog Inputs ................................................................................................................................... 5
1.9 Analog Outputs ................................................................................................................................ 5
1.10 Control Port Connectors ................................................................................................................ 6
1.11 USB Connector .............................................................................................................................. 6
2. QUICK START GUIDE ........................................................................................................................... 7
3. CONFIGURATION OPTIONS ................................................................................................................. 8
3.1 SPDIF In to Headphone or Line Out ................................................................................................ 8
3.2 SPDIF In to Stereo Speaker Out ...................................................................................................... 9
3.3 SPDIF In to Mono Speaker Out ..................................................................................................... 10
4. SOFTWARE MODE CONTROL ........................................................................................................... 11
4.1 Board Configuration Tab ................................................................................................................ 12
4.2 Passthrough, Power and Serial Audio Interface Configuration Tab ............................................... 13
4.3 DSP Engine Tab ............................................................................................................................ 14
4.4 Analog and PWM Output Volume Tab ...........................................................................................15
4.5 Register Maps Tab ......................................................................................................................... 16
5. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 17
6. JUMPER SETTINGS ........................................................................................................................... 18
7. CDB43L22 BLOCK DIAGRAM ............................................................................................................ 19
8. CDB43L22 SCHEMATICS ................................................................................................................... 20
9. CDB43L22 LAYOUT ............................................................................................................................ 24
10. PERFORMANCE PLOTS ................................................................................................................... 29
11. REVISION HISTORY .......................................................................................................................... 31
CDB43L22
LIST OF FIGURES
Figure 1.SPDIF In to Headphone or Line Out ............................................................................................. 8
Figure 2.SPDIF In to Stereo Speaker Out ................................................................................................... 9
Figure 3.SPDIF In to Mono Speaker Out .................................................................................................. 10
Figure 4.Board Configuration Tab ............................................................................................................. 12
Figure 5.Passthrough, Power and Serial Audio Interface Configuration Tab ............................................ 13
Figure 6.DSP Engine Tab ......................................................................................................................... 14
Figure 7.Analog and PWM Output Volume Tab ........................................................................................ 15
Figure 8.Register Maps Tab - CS43L22 ................................................................................................... 16
Figure 9.Block Diagram ............................................................................................................................. 19
Figure 10.CS43L22 & Analog I/O (Schematic Sheet 1) ............................................................................ 20
Figure 11.S/PDIF & Digital Interface (Schematic Sheet 2) .......................................................................21
Figure 12.Micro & FPGA Control (Schematic Sheet 3) .............................................................................22
Figure 13.Power (Schematic Sheet 4) ...................................................................................................... 23
Figure 14.Silk Screen ................................................................................................................................ 24
Figure 15.Top-Side Layer ......................................................................................................................... 25
Figure 16.GND (Layer 2) ........................................................................................................................... 26
Figure 17.Power (Layer 3) ........................................................................................................................ 27
Figure 18.Bottom-Side Layer .................................................................................................................... 28
Figure 19.FFT - S/PDIF Input to HP Output @ -1 dBFS ........................................................................... 29
Figure 20.FFT - S/PDIF Input to HP Output @ -60 dBFS ......................................................................... 29
2 DS792DB1
Figure 21.THD+N vs. HP Output Power ................................................................................................... 29
Figure 22.Freq. Resp. - S/PDIF Input to HP Output .................................................................................. 29
Figure 23.THD+N - S/PDIF Input to HP Output ........................................................................................ 29
Figure 24.Dynamic Range- S/PDIF Input to HP Output ............................................................................ 29
Figure 25.FFT - S/PDIF In to Speaker Out @ 0 dBFS ..............................................................................30
Figure 26.FFT - S/PDIF In to Speaker Out @ -60 dBFS ........................................................................... 30
Figure 27.Frequency Response - S/PDIF In to Speaker Out .................................................................... 30
Figure 28.THD+N - S/PDIF In to Speaker Out .......................................................................................... 30
Figure 29.THD+N vs. Output Power (Stereo) ........................................................................................... 30
Figure 30.THD+N vs. Output Power (Mono) ............................................................................................. 30
LIST OF TABLES
Table 1. SPDIF In to Headphone or Line Out Performance Plots ............................................................... 8
Table 2. SPDIF In to Stereo Speaker Out Performance Plots .................................................................... 9
Table 3. SPDIF In to Mono Speaker Out Performance Plots .................................................................... 10
Table 4. System Connections ................................................................................................................... 17
Table 5. Jumper Settings .......................................................................................................................... 18
CDB43L22
DS792DB1 3
CDB43L22
1. SYSTEM OVERVIEW
The CDB43L22 platform provides analog and digital interfaces to the CS43L22 and allows for external DSP and
®
I²C
interconnects. On-board power regulators are provided so that an external power supply upto +5 V can be used
to provide power for the digital and analog cores of the CS43L22. On-board peripherals are powered from the USB
connection which also serves as an interface to a PC. The CDB43L22 is configured using Cirrus Logic’s Windowscompatible FlexGUI software to read/write to device registers.
This section describes the various components on the CDB43L22 and how they are used. Section 2 on page 7 is a
simplified quick connect guide provided for user convenience and can be used to set up the board quickly with the
CS43L22 in its startup default configuration. Section 3 on page 8 describes the various configuration options in
which the board can be used. Section 4 “Software Mode Control” on page 11 provides further configuration details
and describes software functionality. The CDB43L22 schematic set is shown in Figures 7 through 18. Section 5 on
page 17 provides a description of all stake headers and connectors, including the default factory settings for all jump-
ers.
1.1 Power
Power is supplied to the evaluation board via the USB connection or by applying +5.0 V to TP2. Jumper J34
allows the user to select the power source. Power (VP) and ground (GND) for the CS43L22 is supplied via
binding posts J35 and J4 (respectively) or by standard AAA batteries in locations BT1, BT2 and BT3. The
voltage provided to the binding posts can be in the range of +2.7 V to +5.25 V. On-board regulators and
jumpers allow the user to connect the CS43L22’s supplies to +1.8 V, 2.5 V or +3.3 V for VL and +1.8 V or
2.5 V for VD, VA and VA_HP. All voltage inputs are referenced to ground using the black binding post J4.
Stake headers J47, J52, J53 and J74 provide a convenient way to measure supply currents to the CS43L22
for VA_HP, VL, VD and VA supplies respectively. The current can be easily calculated by measuring the
voltage drop across the parallel resistors with its associated jumper removed.
NOTE: Stake headers J47, J48, J52, J53 and J74 must be shunted with the supplied jumpers during normal
operation.
WARNING: Please refer to the CS43L22 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS43L22 requires careful attention to power supply and grounding arrangements to optimize performance. The CDB43L22 demonstrates these optimal arrangements. Figure 9 on page 19 provides an overview of the connections to the CS43L22. Figure 14 on page 24 shows the component placement, Figure 15
on page 25 shows the top layout, and Figure 18 on page 28 shows the bottom layout. Power supply decou-
pling capacitors are located as close as possible to the CS43L22. Extensive use of ground plane fill helps
reduce radiated noise.
1.3 FPGA
The FPGA controls digital signal routing between the CS43L22, CS8416, SRC, PLL and the I/O stake header. It also provides routing control of the system master clock from an on-board oscillator and the CS8416.
The Cirrus FlexGUI software provides full control of the FPGA’s routing and configuration options. Section 4
“Software Mode Control” on page 11 provides configuration details.
1.4 CS43L22
A complete description of the CS43L22 can be found in the CS43L22 product data sheet.
4 DS792DB1
The CS43L22 is configured using the Cirrus FlexGUI. The device configuration registers are accessible via
the “Register Maps” tab of the Cirrus FlexGUI software. This tab provides low-level control of each bit. For
easier configuration, additional tabs provide high-level control. Section 4 “Software Mode Control” on
page 11 provides configuration details.
1.5 CS8416 Digital Audio Receiver
A complete description of the CS8416 receiver and a discussion of the digital audio interface can be found
in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream from the optical or RCA connector into PCM data that
is input to the CS43L22.
Selections are made by using the “Board Configuration” tab of the Cirrus FlexGUI software. Section 4 “Soft-
ware Mode Control” on page 11 provides configuration details.
1.6 Oscillator
The socketed on-board oscillator can be selected as the system master clock source by using the selections
on the “Board Configuration” tab of the Cirrus FlexGUI. Section 4 “Software Mode Control” on page 11 provides configuration details.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The device footprint on the
board will accommodate full- or half-can-sized oscillators.
CDB43L22
1.7 I/O Stake Headers
The evaluation board has been designed to allow interfacing with external systems via a serial port header
(reference designation J8) and a control port header (reference designation J109). The serial port header
provides access to the serial audio signals required to interface with a DSP (Figure 10 on page 20).
The control port header provides bidirectional access to the I²C control port signals by simply removing all
the shunt jumpers from the “USB” position. The user may then connect a ribbon cable connector to the “Ext
Sys Connect” pins for external control of board functions. A single row of “GND” pins are provided to maintain signal ground integrity. Two unpopulated pull-up resistors are also available should the user choose to
use the CDB43L22 logic supply (VL) externally.
1.8 Analog Inputs
Four stereo jack connectors can be used to supply AC coupled line-level analog inputs to the CS43L22 for
testing the device in passthrough mode.
Figure 10 on page 20 illustrates how the analog passthrough inputs are connected and routed. Table 5 on
page 18 details the jumper selections. The CS43L22 data sheet specifies the allowed full scale input voltage
level.
1.9 Analog Outputs
The CDB43L22 has a stereo headphone/line output jack (J40) and a dedicated stereo headphone (HP) output jack (J21) to monitor the CS43L22’s ground centered analog output. The dedicated HP jack (J21) has
circuitry that drives the SPKR/HP pin low when a stereo jack is inserted thereby allowing users to test the
CS43L22’s HP detect capability. Stake headers (J3 and J9) are provided to allow the user to select either
a 16 Ω or a 32 Ω load for the headphone amplifier output. Stake headers( J1 and J2) are also provided to
allow one to filter HP/Line outputs from the board. HP jack J21 can be used to connect a real headphone to
provide an actual headphone load while performance measurements are taken on HP jack J40. When con-
DS792DB1 5
necting headphones to either output jack, the on-board resistive load should be disconnected by removing
the jumpers on each stake header(J3 and J9).
The CDB43L22 also has A/B speaker output banana jacks (2 per A or B channel) and 1/8“ jack outputs (1
per A or B channel). Stake headers J15 and J19 allow one to short the differential outputs of Channel A and
B together, in order to monitor MONO PWM output from the CS43L22. The red banana jacks designate the
positive speaker terminal connection and the black jacks designate the negative terminal connection.
1.10 Control Port Connectors
The graphical user interface for the CDB43L22 (Cirrus Logic Flex GUI) allows the user to configure the
CS43L22 registers and other component registers via the on-board I²C control bus. The GUI interfaces with
the CDB via the USB connection to a PC. Section 4 “Software Mode Control” on page 11 provides a description of the Graphical User Interface (GUI).
1.11 USB Connector
Connecting a USB port cable from a PC to the USB connector on the board and launching the Cirrus
FlexGUI software enables one to use the CDB43L22. Note: The USB port connection also provides DC
power to the board (except for VP). The minimum current required is approximately 300 mA. It may, therefore, be necessary to connect the CDB43L22 directly to the USB port on the PC as opposed to a hub or
keyboard port where current may be limited.
CDB43L22
6 DS792DB1
CDB43L22
2. QUICK START GUIDE
The following figure is a simplified quick start up guide made for user convenience. The following start up guide configures the board with a 1.8 V power supply to VL, VA, VA_HP and VD. The user may choose from steps 9 through
13 depending on the desired measurement. Refer to Section 3 on page 8 for details on how the various components
on the board interface with each other in different board configuration modes. Refer to Section 4 on page 11 for
descriptions on control settings in the Cirrus FlexGUI software.
8
Connect USB to board.
Ope n Flex GU I softwa re
on PC and load quick
setup script.
*See section 3 for quick
setup descriptions.
9
Provide S/PDIF
input to board via
J61 or OPT3.
10
PCM digital audio input can
also be provided to the
board via header J78.
Shunt bottom 2 pins to
receive board power from
USB +5 V DC power.
7
Shunt the left 2 pins on all rows
of headers J8 and J109.
Connect a ribbon cable to right 2
pins of all rows if external system
connect is required.
Set VL to 1.8 V by
34
shunting top 2 pins.
5
Shunt left 2 pins of
jumpers J16, J13,
J20, J11, J17, J14,
J23 and J12.
Provide analog line level inputs via AIN1,
11
CDB43L22
CS43L22
AIN2 , AIN3, A IN4 for tes ting the p art in
passthrough mode.
13
Receive differential left and right channel
PWM speaker output via binding posts or
30 kHz filtered signal for measurements
via stereo jacks J18 and J6.
*Refer to section 3 for quick setup
descriptions.
12
Shunt left two pins on
J1 and J2.
Monitor Headphone/
Line Output via stereo
jacks J40, J21.
*Refer to section 3
and 4 for software
and hardware
configuration settings.
6
Shunt J74, J47,
J53, J52 and J48.
2
Select the value of
VA, VA_HP and VD
as 1.8 V by shunting
the top 2 pins of J25,
J36 and J28
respectiv ely.
1
Connect power source of 4.5 V between
VP and GND or connect 3 1.5 V AAA
batteries on back of board with correct
polarities. Specify the power source by
shunting appropriate pins on J5.
DS792DB1 7
CDB43L22
3. CONFIGURATION OPTIONS
In order to configure the CDB43L22 for making performance measurements, one needs to use Cirrus Logic’s Windows compatible FlexGUI software to program the various components on the board. This section serves to give a
deeper understanding of the on-board circuitry and the digital clock and data signal routing involved in the different
configuration modes of the CDB43L22. The section also has the expected performance characteristics which are
observed when using the board in the respective configuration mode.
3.1 SPDIF In to Headphone or Line Out
The CS43L22’s stereo headphone/line output performance can be tested by loading the “SPDIF In to
Headphone or Line Out” quick setup file provided with the software package. The script configures the
digital clock and data signal routing on the board as shown in Figure 1.
Stereo audio outputs can be monitored on the 1/8” jacks J21 or J40. HP jack J21 can be used to connect a
real headphone to provide an actual headphone load while performance measurements are taken on HP
jack J40. Digital S/PDIF input can be provided on the optical (OPT2) or RCA (J68) jacks. Jumpers J8 and
J9 can be used to select output loads and jumpers J1 and J2 can be used to select filtered or unfiltered
outputs. Refer to Section 4 on page 11 for details on software configuration.
FPGACS43L22
MCLK
LRCK
SCLK
SDIN
CS8416
S/PDIF Rx
RX.RMCK
RX.LRCK
RX.SCLK
RX.SDOUT
S/PDIF
IN
(MASTER)
(SLAVE)
HP/LINE_OUTA
HP/LINE_OUTB
32 Ω
32 Ω
J9
16 Ω
16 Ω
J3
J21
HP
Connec t
HP/ Line
J1
Output
J40
J2
Figure 1. SPDIF In to Headphone or Line Out
Table 1 shows the expected performance characteristics one should expect when using the CDB43L22 for
SPDIF In to Headphone or Line Out measurements.
Plot Location
FFT - S/PDIF Input to HP Output @ -1dBFS Figure 19 on page 29
FFT - S/PDIF Input to HP Output @ -60dBFS Figure 20 on page 29
THD+N vs. HP Output Power Figure 21 on page 29
Frequency Response- S/PDIF Input to HP Output @ 0dBFS Figure 22 on page 29
THD+N - S/PDIF Input to HP Output Figure 23 on page 29
Dynamic Range- S/PDIF Input to HP Output @ -60dBFS Figure 24 on page 29
Table 1. SPDIF In to Headphone or Line Out Performance Plots
8 DS792DB1
3.2 SPDIF In to Stereo Speaker Out
The CS43L22’s stereo differential PWM speaker output performance can be tested by loading the “SPDIF
In to Stereo Speaker Out” quick setup file provided with the software package. The script configures the
digital clock and data signal routing on the board as shown in Figure 2.
Stereo output jacks J6 and J18 can be used to monitor filtered PWM output for measurement purposes. The
figure shows how a real speaker or a speaker model should attach to the binding posts during performace
tests. Digital S/PDIF input can be provided on the optical (OPT2) or RCA (J68) jacks. Refer to Section 4 on
page 11 for details on software configuration.
CDB43L22
MCLK
LRCK
SCLK
SDIN
(SLAVE)
Pin 4 – SPKOUTA+
Pin 6 – SPKOUTA-
Pin 7 – SPKOUTB+
Pin 9 – SPKOUTB-
FPGACS43L22
CS8416
S/PDIF Rx
RX.RMCK
RX.LRCK
RX.SCLK
RX.SDOUT
S/PDIF
IN
(MASTER )
30 kH z fil ter for
meas urement
J15
J19
30 kH z fil ter for
meas urement
J6
Spkr B
J18
15 µH
8 ΩSpkr A
15 µH
Tes t Load
15 µH
8 Ω
15 µH
Figure 2. SPDIF In to Stereo Speaker Out
OR
+
+
-
Speaker
-
Measurement for
Ch. A
Real
Load
Measurement for
Ch. B
Table 2 shows the expected performance characteristics one should expect when using the CDB43L22 for
SPDIF In to Stereo Speaker Out measurements.
Plot Location
FFT - S/PDIF In to Speaker Out @ 0 dBFS Figure 25 on page 30
FFT - S/PDIF In to Speaker Out @ -60 dBFS Figure 26 on page 30
Frequency Response- S/PDIF In to Speaker Out Figure 27 on page 30
THD+N - S/PDIF In to Speaker Out Figure 28 on page 30
THD+N vs. Output Power- S/PDIF In to Speaker Out Figure 29 on page 30
Table 2. SPDIF In to Stereo Speaker Out Performance Plots
DS792DB1 9
3.3 SPDIF In to Mono Speaker Out
The CS43L22’s mono differential PWM speaker output performance can be tested by loading the “SPDIF
In to Mono Speaker Out” quick setup file provided with the software package. The script configures the
digital clock and data signal routing on the board as shown in Figure 2.
Stereo output jacks J6 and J18 can be used to monitor filtered PWM output for measurement purposes. The
figure shows how a real speaker or a speaker model should attach to the binding posts during performace
tests. Please note how ONLY the tip from the stereo jacks is used to attach the mono differential channel
to the measurement device. Digital S/PDIF input can be provided on the optical (OPT2) or RCA (J68) jacks.
Refer to Section 4 on page 11 for details on software configuration.
CDB43L22
MCLK
LRCK
SCLK
SDIN
(SLAVE)
Pin 4 – SPKOUTA+
Pin 6 – SPKOUTA+
Pin 7 – SPKOUTA-
Pin 9 – SPKOUTA-
FPGACS43L22
CS8416
S/PDIF Rx
RX.RMCK
RX.LRCK
RX.SCLK
RX.SDOUT
(MASTER)
J6
Spkr A
J15
J19
Spkr B
J18
Figure 3. SPDIF In to Mono Speaker Out
S/PDIF
IN
15 µH
4 Ω
15 µH
Tes t Load
OR
+
+
Measure-
ment
Real
Speaker
Load
-
Device
-
Table 3 shows the expected performance characteristics one should expect when using the CDB43L22
for SPDIF In to Mono Speaker Out measurements.
Plot Location
THD+N vs. Output Power- S/PDIF In to Speaker Out Figure 30 on page 30
Table 3. SPDIF In to Mono Speaker Out Performance Plots
10 DS792DB1
CDB43L22
4. SOFTWARE MODE CONTROL
The CDB43L22 may be used with the Microsoft Windows®-based FlexGUI graphical user interface, allowing software control of the CS43L22, FPGA and CS8416 registers. The latest control software may be downloaded from
www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided as follows:
1. Download and install the FlexGUI software as instructed on the Website.
2. Connect and apply power to the +5.0 VP binding post.
3. Connect the CDB to the host PC using a USB cable.
4. Launch the Cirrus FlexGUI. Once the GUI is launched successfully, all registers are set to their default reset
state.
5. Refresh the GUI by clicking on the “Update” button. The default state of all registers are now visible.
For standard set-up:
6. Set up the signal routing in the “Board Configuration” tab as desired.
7. Set up the CS43L22 in the “Passthrough, Power and Serial Audio Interface Configuration”, “DSP Engine”
and “Analog and PWM Output Volume” tab as desired.
8. Begin evaluating the CS43L22.
For quick set-up, the CDB43L22 may, alternatively, be configured by loading a predefined sample script file:
9. On the File menu, click "Restore Board Registers..."
10. Browse to Boards\CDB43L22\Scripts\.
11. Choose any one of the provided scripts to begin evaluation.
To create personal scripts files:
12. On the File menu, click "Save Board Registers..."
13. Enter any name that sufficiently describes the created setup.
14. Choose the desired location and save the script.
15. To load this script, follow the instructions from step 9 above.
DS792DB1 11
4.1 Board Configuration Tab
The “Board Configuration” tab provides high-level control of signal routing on the CDB43L22. This tab also
includes basic controls that allow “quick setup” in a number of simple board configurations. Status text detailing the CS43L22’s specific configuration appears directly below the associated control. This text may
change depending on the setting of the associated control. A description of each control group is outlined
below:
CS43L22 Basic Configuration - Includes controls for configuring the interface format, clocking functions and
analog input signal routing in the CS43L22. See Section 4.2 through Section 4.4 for more controls in the
CS43L22.
CS8416 S/PDIF Receiver Control - Register controls for setting up the CS8416.
Clock Source and Routing Selection - Includes controls used to configure the value and source of the mas-
ter, frame and bit clocks which are sent to the CS43L22.
Update - Reads all registers in the FPGA, CS43L22 and the CS8416 and shows the current values in the
GUI.
Reset - Resets FPGA to default routing configuration.
CDB43L22
Figure 4. Board Configuration Tab
12 DS792DB1
4.2 Passthrough, Power and Serial Audio Interface Configuration Tab
The “Passthrough, Power and Serial Audio Interface Configuration” Tab provides high-level control of the
CS43L22 passthrough, power control and serial port register settings. Status text detailing the CS43L22’s
specific configuration is shown in parenthesis or appears directly below the associated control. This text will
change depending on the setting of the associated control. A description of each group is outlined below.
See the CS43L22 data sheet for complete register descriptions.
Power Control - Register controls for powering down each section within the CS43L22.
Analog Passthrough Configuration - Controls for the input mixer (summing amp) and analog passthrough
settings.
Serial Port Configuration - Controls for all settings related to the serial I/O data and clocks on the board.
Update - Reads all registers in the CS43L22 and reflects the current values in the GUI.
Reset - Resets the CS43L22.
CDB43L22
Figure 5. Passthrough, Power and Serial Audio Interface Configuration Tab
DS792DB1 13
4.3 DSP Engine Tab
The “DSP Engine” tab provides high-level control of the SDIN (PCM) data volume level, the PCM mix volume level and the overall DAC/PWM channel volume level. DAC/PWM channel Limiter, Tone Control and
Beep Generator control functions are also provided. Status text detailing the CS43L22’s specific configuration is shown in parenthesis or inside the control group of the affected control. This text will change depending on the setting of the associated control. A description of each control group is outlined below. See the
CS43L22 datasheet for complete register descriptions.
Digital Volume Control - Digital volume controls and adjustments for the SDIN data and overall channel volume. Mute, gang, invert and de-emphasis functions are also available.
Limiter - Configuration settings for the Limiter.
Tone Control - Bass and treble volume controls and filter corner frequencies.
Beep Generator - On/Off time, frequency, volume, mix and repeat beep functions.
Update - Reads all registers in the CS43L22 and reflects the current values in the GUI.
Reset - Resets the CS43L22.
CDB43L22
Figure 6. DSP Engine Tab
14 DS792DB1
4.4 Analog and PWM Output Volume Tab
The “Analog and PWM Output Volume” tab provides high-level control of the CS43L22 PWM outputs,
HP/Line output volume levels and charge pump frequency. This tab also provides controls for the PWM output including speaker volume and PWM gain. Temperature and Battery monitoring controls for the
PWM/Speaker outputs are also on this tab. Status text detailing the CS43L22’s specific configuration is
shown in read-only edit boxes, in parenthesis or appears directly below the associated control. This text will
change depending on the setting of the associated control. A description of each control group is outlined
below. See the CS43L22 datasheet for complete register descriptions.
Headphone/Line Analog Output - Volume controls and adjustments for the DAC channel (outside of the
DSP). The modulation index and gain settings make up the parameters that determine the full scale headphone/line output level.
PWM Output - Volume, mute, power down and other functional controls for the PWM speaker outputs.
Temperature and Battery Monitor/Control - Battery Compensation, Thermal Foldback, Temperature Shut-
down and Battery Monitor for the PWM/Speaker outputs.
CDB43L22
Figure 7. Analog and PWM Output Volume Tab
DS792DB1 15
4.5 Register Maps Tab
The Register Maps tabs provide low-level control of the CS43L22, CS8416, CS8421, FPGA and GPIO register settings. Register values can be modified bit-wise or byte-wise. “Left-clicking” on a particular register
accesses that register and shows its contents at the bottom. The user can change the register contents by
using the push-buttons, by selecting a particular bit and typing in the new bit value or by selecting the register in the map and typing in a new hex value.
CDB43L22
Figure 8. Register Maps Tab - CS43L22
16 DS792DB1
CDB43L22
5. SYSTEM CONNECTIONS AND JUMPERS
CONNECTOR REF INPUT/OUTPUT SIGNAL PRESENT
VP J35 Input +2.7 V to +5.25 V Power Supply.
GND J4 Input Ground Reference.
USB J94 Input/Output USB connection to PC for I²C control port signals.
S/PDIF OPTICAL IN OPT3 Input CS8416 digital audio input via optical cable.
S/PDIF COAX IN J61 Input CS8416 digital audio input via coaxial cable.
I/O Header J8 Input/Output I/O for Clocks & Data directly to/from the CS43L22.
S/W CONTROL J109 Input/Output I/O for external I²C control port signals.
MICRO JTAG J110 Input/Output I/O for programming the micro controller (U84).
FPGA JTAG J75 Input/Output I/O for programming the FPGA (U5).
MICRO RESET S4 Input Reset for the micro controller (U84).
FPGA PROGRAM S2 Input Reload Xilinx program into the FPGA from Flash (U14).
H/W BOARD RESET S1 Input Reset for the CS43L22(U1).
AIN1
AIN2
AIN3
AIN4
A(RC LPF)
B(RC LPF)
SPEAKER ASPEAKER A+
SPEAKER BSPEAKER B+
HP/Line Output J40 Output Stereo 1/8” jack for line outputs. When headphones are plugged in to HP
HP Connect J21 Output Stereo headphone jack for Headphone outputs.
I/O HDR J78 Input/Output I/O for clocks and input for DAC SDIN. Signals are passed through the
J33
J37
J45
J50
J6
J18
J60
J59
J101
J99
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
1/8” audio jacks for analog passthrough input signal to CS43L22.
1/8” audio jacks for Line or MIC analog passthrough input signals to
CS43L22.
30 kHz LPF version of the signal on speaker binding posts (Used for measurement purposes only).
Full Bridge speaker outputs.
Connect (on J21), this output may be used for performance measurement.
FPGA for muxing with the S/PDIF input.
Table 4. System Connections
DS792DB1 17
CDB43L22
6. JUMPER SETTINGS
JMP LABEL PURPOSE POSITION FUNCTION SELECTED
J31 VL
J36 VA_HP
J25 VA
J28 VD
J52
J47
J74
J53
J48 VP Current measurement *SHUNTED VP supply to CS43L22 is selected.
J13
J14
J16
J17
J11
J12
J20
J23
J15 MONO
J19 MONO
J3 HP B LOAD
J9 HP A LOAD
J1 LEFT CH
J2 RIGHT CH
J22 HP DETECT
J34 Board Power
J5 VP
VL
+VA_HP
VA
VD
[No Label]
[No Label]
[No Label]
[No Label]
Selects source of voltage for the
VL supply
Selects source of voltage for the
Selects source of voltage for the
Selects source of voltage for the
Applies a filtered or a non-filtered
version of the SPKA- signal to J60
Applies a filtered or a non-filtered
version of the SPKA+ signal to J59
Applies a filtered or a non-filtered
Applies a filtered or a non-filtered
version of the SPKA- signal to J99
Applies a short between SPKOUT
MONO function is enabled in the
Applies a short between SPKOUT
MONO function is enabled in the
Selects between a filtered or non
Selects between a filtered or non
Selects the control source for the
Selects either External or Battery
power for VP and for the buck reg-
VA_HP supply
VA supply
VD supply
Current Measurement
version of the SPKB- signal to
A+ and A-. (Used only after
B+ and B-. (Used only after
Selects 32 or 16 Ω load for
HP/LINE_OUTB (DAC out)
Selects 32 or 16 Ω load for
HP/LINE_OUTA (DAC out)
HP/LINE_OUTA signal.
HP/LINE_OUTB signal.
Selects either USB or External
+5 V power for the board
ulators that powers VA, VA_HP
J101
CS43L22)
CS43L22)
filtered version of the
filtered version of the
SPKR/HP pin
and VD
Table 5. Jumper Settings
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
+3.3V Voltage source is +3.3 V regulator.
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
*SHUNTED 1 Ω series resistor is shorted.
OPEN 1 Ω series resistor in power supply path.
*1 - 2 SPKOUTA- output routed to J60.
2 - 3 SPKOUTA- output not routed to J60.
*1 - 2 SPKOUTA+ output routed to J59.
2 - 3 SPKOUTA+ output not routed to J59.
*1 - 2 SPKOUTB- output routed to J101.
2 - 3 SPKOUTB- output not routed to J101.
*1 - 2 SPKOUTB+ output routed to J99.
2 - 3 SPKOUTB+ output not routed to J99.
*OPEN
SHUNTED
*OPEN
SHUNTED Channel - to J99 and J101 respectively.
1 - 2 16 Ω load selected.
2 - 3 32 Ω load selected.
1 - 2 16 Ω load selected.
2 - 3 32 Ω load selected.
1 - 2 Non-filtered HP/LINE_OUTA to HP/Line Jack.
*2 - 3
1 - 2 Non-filtered HP/LINE_OUTA to HP/Line Jack.
*2 - 3
1 - 2 FPGA.
*2 - 3 HP Jack.
1 - 2 External +5 V power.
*2 - 3
*1 - 2 External from J35.
2 - 3
Channel A+ and A- to J59 and J60 respectively.
Channel + to J59 and J60 respectively.
Channel B+ and B- to J99 and J101 respectively.
Filtered HP/LINE_OUTA to HP/Line Jack.
Filtered HP/LINE_OUTA to HP/Line Jack.
USB generated +5 V power. (USB hub must be
capable of greater than 300 mA)
Battery from BT1-BT3 (bottom side)
18 DS792DB1
DS792DB1 19
7. CDB43L22 BLOCK DIAGRAM
USB
µ controller
S/PDIF Input
(CS8416)
PLL
Reset
Oscillator
FPGA
I2C Interface
(socket)
CS43L22
Analog
Passthrough
Input
Speaker
Outputs
Analog Output
(Line + Headphone)
Reset
Clk/Data
SRC
(CS8421)
PSIA Input
Header
Figure 9. Block Diagram
External System
Input Header
CDB43L22
20 DS792DB1
8. CDB43L22 SCHEMATICS
Figure 10. CS43L22 & Analog I/O (Schematic Sheet 1)
CDB43L22
DS792DB1 21
Figure 11. S/PDIF & Digital Interface (Schematic Sheet 2)
CDB43L22
22 DS792DB1
Figure 12. Micro & FPGA Control (Schematic Sheet 3)
CDB43L22
DS792DB1 23
Figure 13. Power (Schematic Sheet 4)
CDB43L22
24 DS792DB1
9. CDB43L22 LAYOUT
CDB43L22
CS43L22
Figure 14. Silk Screen
CDB43L22
DS792DB1 25
Figure 15. Top-Side Layer
CDB43L22
26 DS792DB1
Figure 16. GND (Layer 2)
CDB43L22
DS792DB1 27
Figure 17. Power (Layer 3)
CDB43L22
28 DS792DB1
Figure 18. Bottom-Side Layer
CDB43L22
CDB43L22
+0
+0
+0
+3
40
40
10.PERFORMANCE PLOTS
Test conditions (unless otherwise specified): Measurement bandwidth is 20 Hz to 20 kHz (unweighted);
VA=VD=VA_HP=1.8V; Sample Frequency = 48 kHz; HP test load: R
-10
-20
-30
-40
-50
-60
d
B
-70
r
A
-80
-90
-100
-110
-120
-130
-140
20 20k50 100 200 500 1k 2k 5k 10k
Figure 19. FFT - S/PDIF Input to HP Output @ -1 dBFS Figure 20. FFT - S/PDIF Input to HP Output @ -60 dBFS
-5
-10
*Note 2
-15
-20
-25
-30
-35
-40
d
-45
B
r
-50
A
-55
-60
-65
-70
-75
-80
-85
-90
-95
10m 100m20m 30m 40m 50m 60m 70m 80 m 90m
Figure 21. THD+N vs. HP Output Power Figure 22. Freq. Resp. - S/PDIF Input to HP Output
-
-42.5
-45
-47.5
-50
-52.5
-55
-57.5
-60
-62.5
-65
-67.5
d
-70
B
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
20 20k50 100 200 500 1k 2k 5k 10k
Figure 23. THD+N - S/PDIF Input to HP Output Figure 24. Dynamic Range- S/PDIF Input to HP Output
Hz
Gain
1.1430
1.000
0.8399
0.7099
0.6047
W
Hz
= 16 Ω.
L
-10
-20
-30
-40
-50
-60
d
B
-70
r
A
-80
-90
-100
-110
-120
-130
-140
20 20k50 100 200 500 1k 2k 5k 10k
+2.75
+2.5
+2.25
+2
+1.75
+1.5
+1.25
+1
+0.75
+0.5
d
+0.25
B
-0
r
-0.25
A
-0.5
-0.75
-1
-1.25
-1.5
-1.75
-2
-2.25
-2.5
-2.75
-3
20 20k50 100 200 500 1k 2k 5k 10k
-
-45
-50
-55
-60
-65
-70
-75
d
B
-80
r
A
-85
-90
-95
-100
-105
-110
-115
-120
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Hz
Hz
DS792DB1 29
CDB43L22
10
10
10
+0
-5
-10
-15
-20
-25
-30
-35
-40
d
-45
B
-50
r
-55
A
-60
-65
-70
-75
-80
-85
-90
-95
-100
20 20k50 100 200 500 1k 2k 5k 10k
Hz
+0
-10
-20
-30
-40
-50
-60
d
B
-70
r
A
-80
-90
-100
-110
-120
-130
-140
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 25. FFT - S/PDIF In to Speaker Out @ 0 dBFS Figure 26. FFT - S/PDIF In to Speaker Out @ -60 dBFS
+5
+4.5
+4
+3.5
+3
+2.5
+2
+1.5
+1
d
+0.5
B
-0
r
-0.5
A
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
20 20k50 100 200 500 1k 2k 5k 10k
Hz
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 27. Frequency Response - S/PDIF In to Speaker Out Figure 28. THD+N - S/PDIF In to Speaker Out
5
2
VP = 2.5 V
1
0.5
%
0.2
0.1
0.05
0.02
0.01
200m 1.2400m 600m 800m 1
VP = 3.7 V
W
= 5.0 V
V
P
5
= 2.5 V
V
P
2
VP = 3.7 V
1
0.5
%
0.2
0.1
0.05
0.02
0.01
0 2200m 400m 600m 800m 1 1.2 1.4 1.6 1.8
W
V
= 5.0 V
P
Figure 29. THD+N vs. Output Power (Stereo) Figure 30. THD+N vs. Output Power (Mono)
30 DS792DB1
11.REVISION HISTORY
Revision Changes
DB1 Initial Release
CDB43L22
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
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supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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Windows
DS792DB1 31
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