Cirrus Logic CDB4382 User Manual
Evaluation Board for CS4382
CDB4382
Features
! Demonstrates recommended layout and
grounding arrangements
! CS8414 receives S/PDIF, & EIAJ-340
compatible digital audio
! Headers for external audio input for either
PCMorDSD
! Requires only a digital signal source and
power supplies for a complete Digital-toAnalog-Converter system
Inputs for Clocks
and Data
Description
The CDB4382 evaluation board is an excellent means
for quickly evaluating the CS4382 24-bit, eight channel
D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the
CS4382 (for control port mode only) and a power supply.
Analog line level outputs are provided via RCA phono
jacks.
The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog
converter and will accept S/PDIF, and EIAJ-340 compatible audio data. The evaluation board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4382 Evaluation Board
Control
Port
CS8414
Digital Audio
Interface
Inputs for DSD
Data and Clock
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Analog
Outputs
CS4382
MUTE
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
DS514DB2
SEPT ‘01
1
TABLE OF CONTENTS
1. CS4382 DIGITAL TO ANALOG CONVERTER ......................................................................... 3
2. CS8414 DIGITAL AUDIO RECEIVER .......................................................................................3
3. INPUT/OUTPUT FOR CLOCKS AND DATA ............................................................................3
4. POWER SUPPLY CIRCUITRY .................................................................................................3
5. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................. 3
6. CONTROL PORT SOFTWARE ................................................................................................3
7. DSD OPERATION .....................................................................................................................4
8. ANALOG OUTPUT FILTER ......................................................................................................4
9. ERRATA ....................................................................................................................................5
LIST OF FIGURES
Figure 1. Instrumentation Amplifier Configuration...........................................................................4
Figure 2. System Block Diagram and Signal Flow ..........................................................................6
Figure 3. CS4382 ............................................................................................................................ 7
Figure 4. CS8414 Digital Audio Receiver........................................................................................8
Figure 5. PCM Input Header ........................................................................................................... 9
Figure 6. DSD Input Header..........................................................................................................10
Figure 7. Control Port Interface.....................................................................................................11
Figure 8. Channel Pair 1 Outputs and Mute.................................................................................. 12
Figure 9. Channel Pair 2 Outputs and Mute.................................................................................. 13
Figure 10. Channel Pair 3 Outputs and Mute................................................................................ 14
Figure 11. Channel Pair 4 Outputs and Mute................................................................................ 15
Figure 12. Power Supply Connections..........................................................................................16
Figure 13. Silkscreen Top .............................................................................................................17
Figure 14. Top Side.......................................................................................................................18
Figure 15. Bottom Side..................................................................................................................19
CDB4382
LIST OF TABLES
Table 1. System Connections ........................................................................................................4
Table 2. CDB4382 Jumper Settings................................................................................................5
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those
components in a standard I2C system.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this
document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and
limitationof liability. No responsibility is assumedby Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale
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Thenamesof products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which
may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found
2
at http://www.cirrus.com
.
CDB4382 SYSTEM OVERVIEW
CDB4382
The CDB4382 evaluation board is an excellent
means of quickly evaluating the CS4382. The
CS8414 digital audio interface receiver provides an
easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to
supply either PCM or DSD clocks and data through
headers for system development.
The CDB4382 schematic has been partitioned into
10 schematics shown in Figures 3 through 12. Each
partitioned schematic is represented in the system
diagram shown in Figure 2. Notice that the system
diagram also includes the interconnections between the partitioned schematics.
1. CS4382 DIGITAL TO ANALOG CONVERTER
A description of the CS4382 is included in the
CS4382 datasheet.
and data. The schematic for the clock/data input is
shown in Figure 5.
Header J16 allows the evaluation board to accept
externally generated DSD data and clock. The
schematic for the clock/data input is shown in
Figure 6. A synchronous MCLK must still be provided via header J15. Please see the CS4382
datasheet for more information.
4. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by seven
binding posts (GND, +5V, VLS, VLC, VD, +18V
and -18V), see Figure 12. The VLC and VLS supplies can be jumpered to the +5V binding post for
ease of use. VD and VA should be set to the recommended values stated in the CS4382 datasheet.
+18V and -18V supply power to the op-amps and
can be +/-5 to +/-18 volts (must be +/-18 V when
filter 2 is selected).
2. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 4. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock
(FSYNC), and a 256 Fs master clock. The CS8414
data format has been configured for I
ation of the CS8414 and a discussion of the digital
audio interface is included in the CS8414
datasheet.
The evaluation board has been designed such that
the input can be either optical or coax, see Figure 4.
However, both inputs cannot be driven simultaneously.
2
S. The oper-
3. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow
interfacing to external systems via the 18-pin headers, J15 and J16. Header J15 allows the evaluation
board to accept externally generated PCM clocks
WARNING
maximum allowable voltages levels. Operation
outside of this range can cause permanent damage
to the device.
: Refer to the CS4382 datasheet for
5. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4382 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 3 details the connections to
the CS4382 and Figures 13 & 14, 15 show the component placement and top and bottom layout. The
decoupling capacitors are located as close to the
CS4382 as possible. Extensive use of ground plane
fill in the evaluation board yields large reductions
in radiated noise.
6. CONTROL PORT SOFTWARE
The CDB4382 is shipped with Windows 95/98/ME
based software for interfacing with the CS4382
control port via the DB25 connector, J1 (Windows
NT and 2000 not currently supported). The software can be used to communicate with the CS4382
3
CDB4382
in either SPIor I2C mode; however, in SPI mode
the CS4382 registers are write-only.
7. DSD OPERATION
The CDB4382 supports Direct Stream Digital
(DSD) operation through the header for external
clocks and data, J16. The CS4382 must be placed
into the DSD mode and headers J6 and J14 must be
set accordingly. See Table 2 for more information.
8. ANALOG OUTPUT FILTER
The analog output filter on the CDB4382 has been
designed to add flexibility when evaluating the
CS4382. The output filter was designed in an optional two stage format, with the first optional stage
being an instrumentation amplifier design and the
second is a 2-pole butterworth filter.
The 2-pole filter is designed to have the in-band
impedance matched between the positive and negative legs. It also provides a balanced to single ended conversion for standard un-balanced outputs.
overall dynamic range of the system. The gain of
this stage is determined from the following equation:
Gain 1
The resistor designated by R
2 R()
-----------+=
R
2
(see Figure 1) can be
2
adjusted to change the gain of the Instrumentation
amp, and the feedback resistors on the two sides of
the instrumentation amp ‘R’ must be equal.
A resistor divider has been placed before the RCA
jack which brings the signal level back to 2 Vrms
(selectable per channel with jumpers J21 to J28).
Note: This resistor divider may introduce more distortion from the second filter stage’s op-amp..
The instrumentation amplifier is optionally inserted by changing the FILT jumpers to position 2 (selectable per channel by J37 & 38, J39 & 40, etc.).
This instrumentation amplifier incorporates a 5x
gain (+14dB) which effectively lowers the noise
Figure 1. Instrumentation Amplifier Configuration
contribution of the 2-pole filter which improves the
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
+5V Input + 5 Volt power
VD Input + 2.5 to +5V power for the CS4382 digital supply
VLS Input + 1.8 to +5V power for the CS4382 serial interface
VLC Input + 1.8 to +5V power for the CS4382 control interface
-18V Input -18 to -5V negative supply for the op-amps
+18V Input +5 to +18V positive supply for the op-amps
GND Input Ground connection from power supply
SPDIF INPUT - J2 Input Digital audio interface input via coax
SPDIF INPUT - OPTO-1 Input Digital audio interface input via optical
PCM INPUT - J15 Input Input for master, serial, left/right clocks and serial data
DSD INPUT - J16 Input Input for DSD data and clock
PC Port Input/Output
EXT CTRL I/O Input/Output
OUTA1 to OUTB4 Output Channels 1A to 4B line level analog outputs
Parallel connection to PC for SPI / I
2
I/O for SPI / I
C control port signals
2
C control port signals
Table 1. System Connections
4
CDB4382
9. ERRATA
been placed according to the schematic and not the
silkscreen
CDB4382 Revision B.0
The CDB4382 revision B.0 has the following errata. The silk-screens for Z4 and Z5 are reversed.
The cathode band marks on the silkscreen are facing the wrong direction. The zener devices have
JUMPER /
SWITCH PURPOSE POSITION FUNCTION SELECTED
J3 Selects source of voltage for the
VLC supplies
J7 Selects source of voltage for the
VLS supplies
J41 Selects source of voltage for the
VD supply
J6 Clock Source Select *CS8414
J14 Input Mode Select *PCM
J4 Stand-Alone/Control Port Select SA
J9 M0/AD0/CS HI
J10 M1/SDA/CDIN *HI
J11 M2/SCL/CCLK *HI
J12 M3/DSD_CLK HI
FILT Filter select *1
R135 to
R142
Mute Enables *SHUNTED
CDB4382 Revision C.0
The CDB4382 revision C.0has no errata at the time
of this publication.
VLC
*+5V
VLS
*+5V
*VD
+5V
External
DSD
*CP
*LO
LO
LO
*LO
2
OPEN
Voltage source is VLC binding post
Voltage source is +5V binding post
Voltage source is VLS binding post
Voltage source is +5V binding post
Voltage source is VD binding post
Voltage source is +5V binding post
CS8414 provides PCM inputs to CS4382
PCM or DSD inputs are provided externally
Selects PCM input mode
Selects DSD input mode (via J16)
Stand-Alone Mode (No PC required)
Control Port Mode (PC required)
See CS4382 datasheet for details
See CS4382 datasheet for details
See CS4382 datasheet for details
See CS4382 datasheet for details
Selects standard 2-pole filter
Inserts instrumentation-amp
Enables the external mute circuit for each
channel when 0 Ohm is present (default)
*Default Factory Settings
Table 2. CDB4382 Jumper Settings
5
6
Control Port
Figure 7
Reset
Circuit
Channels 1A & 1B
Outputs and Mute
Figure 8
MCLK
8414 Digital
Audio Receiver
Figure 4
SCLK1
LRCK1
SDATA1
SDATA2
SDATA3
SDATA4
CS4382
Figure 3
Channels 2A & 2B
Outputs and Mute
Figure 9
Channels 3A & 3B
Outputs and Mute
Figure 10
Channels 4A & 4B
Outputs and Mute
Figure 11
PCM Inputs
Figure 5
SCLK2
LRCK2
DSD1A
DSD1B
DSD2A
DSD2B
DSD3A
DSD3B
DSD4A
DSD4B
DSD_CLK
DSD Inputs
Figure 6
Figure 2. System Block Diagram and Signal Flow
CDB4382
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