supplies for a complete Digital-to-analog
converter system
®
Description
The CDB4365 evaluation board is an excellent means
for quickly evaluating the CS4365 24-bit, 48-pin, 6channel D/A converter. Evaluation requires an analog
signal analyzer, a digital signal source, a PC for controlling the CS4365 (only required for control port mode),
and a power supply. Analog line-level outputs are provided via RCA phono jacks.
The CS8416 digital audio receiver IC provides the system timing necessary to operate the digital-to-analog
converter and will accept S/PDIF and EIAJ-340-compatible audio data. The evaluat ion board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
Figure 53.Silkscreen Top .......................................................................................................................... 27
Figure 54.Top Side .................................................................................................................................... 28
Figure 55.Bottom Side .............................................................................................................................. 29
LIST OF TABLES
Table 1. System Connections .................................................................................................................... 5
The CDB4365 evaluation board is an excellent means of quickly evaluating the CS4365. The CS8416 digital audio
interface receiver provides an easy interface to digi tal audio signal sources including the majority of dig ital audio test
equipment. The evaluation board also allows th e user to supply external PCM or DSD clocks and data through PCB
headers for system development.
The CDB4365 uses the CDB4385 as a base PCB board. For this reason, the re may be additional circui try on board
which is not populated as it has no function for this device.
The CDB4365 schematic has been partitioned into 9 schematics shown in Figure 44 through 52. Each partitioned
schematic is represented in the system diagram shown in Figure Figure 43 on page 17. Notice that the system diagram also includes the interconnections between the partitioned schematics.
1. CS4365 DIGITAL-TO-ANALOG CONVERTER
A description of the CS4365 is included in the CS4365 datasheet.
2. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver
(Figure 48). The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs master clock. The CS8416 data format is fixed to I²S. The operatio n of the CS8416 and a discu ssion of the digital audio
interface are included in the CS8416 datasheet.
The evaluation board has been designed such that the input can be either optical or coaxial (See Figure 48). However, both inputs cannot be driven simultaneously.
Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed)
for inputs Fs≤96 kHz and 128 (open) for Fs≥64 kHz. The 8416 must be manually reset using ‘HW RST’ (S2) or
through the software when this switch is changed.
3. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via headers J11 and J7. H eader
J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the
clock/data input is shown in Figure 49. Switch position 6 of S1 selects the source as either CS8416 (o pen) or header
J11 (closed).
Header J7 allows the evaluation board to accept externally generated DSD data and clocks. The sch ematic for the
clock/data input is shown in Figure 50. A synchronous MCLK must still be provided via Header J11. Switch position
8 of S1 selects either PCM (open) or DSD (closed).
Please see the CS4365 datasheet for more info rm at ion .
4. INPUT FOR CONTROL DATA
The evaluation board can be run in either a stand-alon e mode or with a PC. Stand-alone mod e uses the CS4365 in
hardware mode and the mode pins are configured u sing switch positions 1 through 5 of S1. PC mode uses software
to setup the CS4365 through I²C
serial or USB port is attached and the CDB4365 software is running.
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using the PC’s serial or USB ports. PC mode is automatically selected when the
Header J15 offers the option for external input of RST and SPI
factory to use the on-board microcont roller in conjunction with the supplied software. To use an external control
4DS670DB3
™/I²C clocks and data. The board is setup from the
CDB4365
source, remove the shunts on J15 and place a ribbon cable so the signal lines are on the ce nter row and the grounds
are on the right side. R116 and R119 should be populated with 2-kΩ resistors when using an external I²C source
that does not already provide pull-ups.
5. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four binding posts: GND, +5V, +12V, and -12V (See Figure 52). The
‘+5V’ terminal supplies VA and the rest of the +5-V circuitry on the board. The +3.3-V circuitry is powered from a
regulator. The +2.5 volts required for VD is also prov ided from an on-boar d regulator. The +5 -V supply should be
set within the recommended values for VA stated in the CS4365 datasheet.
WARNING
cause permanent damage to the device.
: Refer to the CS4365 datasheet for maximum allowable voltage levels. Operation outside this range can
6. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high-performance converter, the CS4365 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 44 details the connections to the CS4365 and Figures 53, 54, and 55
show the component placement and top and bottom layout. The decoupling capacitors are located as close to the
CS4365 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated
noise.
7. ANALOG OUTPUT FILTERING
The analog output on the CDB4365 has been designed according to the CS4365 datasheet. This output circuit includes an active 2-pole, 50-kHz filter which uses the multiple-feedback topology.
CONNECTORINPUT/OUTPUTSIGNAL PRESENT
+5VInput+ 5 V power
GNDInputGround connection from power supply
+12VInput+12 V positive supply for the on-board filtering
-12VInput-12 V negative supply for the on-board filtering
S/PDIF IN - J9InputDigital audio interface input via coax
S/PDIF IN - OPT1InputDigital audio interface input via optical
PCM INPUT - J11InputInput for master, serial, left/right clocks and serial data
DSD INPUT - J7InputInput for DSD serial clock and DSD data
OUTA1-B3OutputRCA line level analog outputs
Table 1. System Connections
DS670DB35
JUMPER /
SWITCHPURPOSEPOSITIONFUNCTION SELECTED
J15Selects source of control data
J16JT AG micro programming-Reserved for factory use only
S2Resets CS8416 and CS4365The CS8416 must be reset if switch S1 is changed
CS4365 mode settings M0-M41-5
S1
Sets clock source6
Sets MCLK ratio of CS84167
Selects PCM or DSD mode8For PCM input set to *Open, for DSD set to Closed
*shunts on Left
shunts removed
*Default Factory Settings
*Control from PC and on-board microcontroller
External control input using center and right columns
Default: M0, M4 open (HI)
M1, M2, M3 closed (LO)
Sets clock source for CS4365
*open = RX(CS8416), closed = EXT
Selects 128x (open) or 256x
output for CS8416
(*closed) MCLK/LRCK ratio
Table 2. CDB4365 Jumper Settings
CDB4365
(J11)
6DS670DB3
CDB4365
8. PERFORMANCE PLOTS
The plots in the following section were acheived using an Audio Precision System 2700 and a ra ndomly chosen production CDB4365. In some cases the performance may be limited by the CDB4365. All measurements were taken
at room temp using the standard AP filter options (20 Hz to 22 kHz) with default board settings and nominal
datasheet voltages applied unless otherwise no te d.
The impulse response plots were taken both pre-and post filtering as the off-chip filter wa s degrading the performance at higher sample rates. The pre-filter impulse response plots were taken directly at the output pins of the
DAC (with the analog filter still connected) to show the effect of the CDB’s analog filtering on the impulse response
(as the analog filtering adds its own signature to the impulse response of the DAC, and in the case of the higher
sampling rates it was band-limiting it).