Cirrus Logic CS4341A-KS, CDB4341A Datasheet
CS4341A
24-Bit, 192 kHz Stereo DAC with Volume Co ntro l
Features
101 dB Dynamic Range
-91 dB THD+N
+3.3 V or +5 V Power Supply
50 mW with 3. 3V supply
Low Clock Jitter Sensitivity
Filtered Line Level Outputs
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
ATAPI Mixing
Digital Volume Control with Soft Ramp
– 94 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
Up to 200 kHz Sample Rates
Automatic Mode Detection for Samp le Rates
between 4 and 2 0 0kHz
Pin Compatible with the CS4341
Description
The CS4341A is a complete stereo digital-to-analog system including digital interpolation, fourth-order deltasigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter.
The CS4341A accepts data at all standard audio sample
rates up to 192 kHz, consumes very little power, operates over a wide power supply range and is pin
compatible with the CS4341, as described in section 3.1.
These features are ideal for DVD audio players.
ORDERING INFORMATION
CS4341A-KS 16-pin SOIC, -10 to 70 °C
CDB4341A Evaluation Board
RST
SCLK
LRCK
SDIN
SCL/CCLK MUTECAD0/C S
Inte r fa c e
Serial Audio
SDA/CDIN
Control Port
Interface
Preliminary Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
http://www.cirrus.com
External
Mute Control
Volume Contro lInterpolation Filter Analog Filter
Mixer
Volume Contro lInterpola t ion Filte r ∆Σ
÷2
MCLK
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
∆Σ
DAC
DAC
Analog Filter
AOU TA
AOUT B
DS582PP1
AUG ‘02
1
CS4341A
TABLE OF CONTENTS
1. PIN DESCRIPT IO N ....... ................ ........................ ........................ ....................... .....................5
2. TYPICAL CONNECTION DIAGRAM ............................................ .. ..... ..... .. ..... .. ..... .. ..... ... .... ..6
3. APPLICATIONS ................................... ........................ ........................ .....................................7
3.1 Upgrading from the CS4341 t o the CS4341A ....................................................................7
3.2 Sample Rate Range/Operational Mode Detect ..................................................................7
3.2.1 Auto-Detect Enabled .............................................................................................7
3.2.2 Auto-Detect Disabled ............................................................................................7
3.3 System Clocking ................................................................................................................ 8
3.4 Digital Interface Format ......................................................................................................8
3.5 De-Em phasis Control ... .. ...................... .. .. ...................... .. .. ...................... .. .. ......................9
3.6 Recommended Power-up S equenc e .................................................................................9
3.7 Popguard
3.7.1 Power-up .............................................................................................................10
3.7.2 Power-down ........................................................................................................10
3.7.3 Discharge Time ...................................................................................................10
3.8 Grounding and Powe r Supply Arrangements ..................................................................10
3.9 Control Port Interface .......................................................................................................11
3.9.1 MAP Auto Increment ...........................................................................................11
3.9.2 I2C Mode . . ...........................................................................................................11
3.9.3 SPI Mode ............................................................................................................13
3.10 Memory Address Pointer (MAP) ..............................................................................14
3.10.1 INCR (Auto Map Increment Enable) ..... ..... .. .......... .. ..... .. ....... ..... ..... .. ....... ..... .. ..... ..... ..14
3.10.2 MAP (Memory Address Pointer)..................................................................................14
®
Transient Control ...........................................................................................10
3.9.2a I2C Write ..............................................................................................11
3.9.2b I2C Read ..............................................................................................12
3.9.3a SPI Write ..............................................................................................13
4. REGISTER QUICK REFERENCE ............ ........................ ........................ ....................... .......14
Contacting Cirrus Logic Support
F or a co mp lete listing of Direct S a le s, D is tribu tor, a n d Sale s R e p res e n tativ e co n ta cts , vis it the C irru s Lo g ic w e b site a t:
http://www .cirrus.com /corpo rate/contacts /sales.cfm
IMPORTANT NOTICE
"Preliminary" product information describes prod u cts that are in pr oduction, but for wh ic h full c hara c terization data is not yet available. "Advance" product infor-
mation describes products that are in development and subject t o development changes. Ci r r u s Logic, In c . an d i ts su b sid ia r i es ("C i rru s ") b elie ve th a t the information contained in thi s document is accurate and reli able. However, the infor mation is subj ect to change without noti ce and is provi ded "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the l atest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products a re sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibili ty i s assume d by Cirrus for the use of this information, including use of this
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obtained from the competent authorit i es of the Chinese Government if any of the products or technologi es descri bed in this material is s ubject to the PRC Foreign
Trade Law and is to be exported or taken out of t he PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LI FE-SUPPORT DEVICES O R SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I
those components in a standard I
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and pr oduct names in this docume nt may be trademarks or service marks of their respective owners.
2
C components of Cirrus Logi c, Inc., or one of its sublicensed Associated Companies co nveys a license under th e Phillips I2C Patent Rights to use
2
C system.
2 DS582PP1
CS4341A
5. REGISTER DESCRIPTION ........................... ........................ ....................... ........................ ..15
5.1 Mode Control 1 (address 00h).......................................................................................... 15
5.2 Mode Control 2 (address 01h).......................................................................................... 15
5.3 Tr ansition and Mixing Control (address 02h).................................................................... 17
5.4 Channel A Volume Control (address 03h)........................................................................ 20
5.5 Channel B Volume Control (address 04h)........................................................................ 20
6. CHARACTERISTICS AND SPECIFICATIONS ......................................................................21
ANALOG CHARACTERISTICS (CS4341A -KS)..................................................................... 21
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................23
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ..........................................26
SWITCHING SPECIFICA TIO NS - CONTROL PORT INT ERFA CE......... ................ .............. 27
SWITCHING SPECIFICA TIO NS - CONTROL PORT INT ERFA CE......... ................ .............. 28
DC ELECTRICAL CHARACTERISTICS................................................................................29
DIGITAL INPUT CHARACTERISTICS...................................................................................29
DIGITAL INTERFACE SPECIFICATIONS.............................................................................29
THERMAL CHARACTERISTICS AND SPECIFICATIONS....................................................29
RECOMMENDED OPERATING SPECIFICATION .............................................................. 30
ABSOLUTE MAXIMUM RATINGS......................................................................................... 30
7. PARAMETER DEFI NITIONS ....................... ....................... ................. ....................... ............ 31
Total Harmonic Distortion + Noise (THD+N).......................................................................... 31
Dynamic Range ......................................................................................................................31
Interchannel Isolation ............................................................................................... ..............31
Interchannel Gain Mismatch................................................................................................. ..31
Gain Error...............................................................................................................................31
Gain Drift................................................................................................................................ 31
8. REFERENC ES ..................................... ........................ ........................ ................................... 31
9. PACKAGE DIMENSI O NS ... ................ ............................... ........................ ............................ 32
LIST OF FIGURES
Figure 1. Typical Connection Diagram .......................................................................................... 6
Figure 2. I
Figure 3. Left Justified up to 24-Bit Data ....................................................................................... 9
Figure 4. Right Justified Data ........................................................................................................ 9
Figure 5. De-Emphasis Curve ....................................................................................................... 9
Figure 6. Control Port Timing, I2C Mode .................................................................................... 12
Figure 7. Control Port Timing, SPI mode .............................. .. ....... ....... ..... ....... ....... ....... ..... .......13
Figure 8. ATAPI Block Diagram ..................................................................................................19
Figure 9. Output Test Load ......................................................................................................... 22
Figure 10. Maximum Loading ........................................................................................................ 22
Figure 11. Single-Speed Stopband Rejection ............................................................................... 24
Figure 12. Single-Speed Transition Band ..................................................................................... 24
Figure 13. Single-Speed Transition Band (Detail) ......................................................................... 24
Figure 14. Single-Speed Passband Ripple ...................................................................................24
Figure 15. Double-Speed Stopband Rejection .............................................................................. 24
Figure 16. Double-Speed Transition Ban d .................................................................................... 24
Figure 17. Double-Speed Transition Ban d (Detail) ....................................................................... 25
Figure 18. Double-Speed Passband Ripple .................................................................................. 25
Figure 19. Serial Input Timing ....................................................................................................... 26
Figure 20. Control Port Timing - I2C Mode ...................................................................................27
Figure 21. Control Port Timing - SPI Mode ................................................................................... 28
2
S Data .........................................................................................................................8
DS582PP1 3
LIST OF TABLES
Table 1. CS4341A Auto-Detect .......................................................................................................... 7
Table 2. CS4341A Mode Select .........................................................................................................7
Table 3. Single-Speed Mode Standard Frequencies..........................................................................8
Table 4. Double-Speed Mode Standard Frequencies........................................................................8
Table 5. Quad- Speed Mode Standard Frequencies ...........................................................................8
Table 7. ATAPI Decode....................................................................................................................18
Table 8. Example Digital Volume Settings .......................................................................................20
CS4341A
4 DS582PP1
1. PIN DESCRIPTION
RST MUTEC
SDIN AOUTA
161
152
CS4341A
SCLK VA
LRCK AGND
MCLK AOUTB
SCL/CCLK REF_GND
SDA/CDIN VQ
AD0/CS
Pin Name # Pin Description
RST
SDIN
SCLK
LRCK
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
FILT+
VQ
REF_GND
AOUTR
AOUTL
AGND
VA
MUTEC
Reset (Input) - Powers down device when enabled.
1
Serial Audio Data (Input) - Input for two’s complement serial audio data.
2
Serial Clock (Input) -Serial cloc k f or the serial audio interface.
3
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
4
serial audio data line.
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
5
Serial Control Port Clock (Input) - Serial clock for the control port interface.
6
7
Serial Control Data I/O
Address Bit / Chip Select (Input) - Chip address bit in I
8
the chip in SPI mode.
Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir-
9
cuits.
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
10
Reference Ground (Input) - Ground reference for the internal sampling ci rc uits.
11
Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac-
12
teristics table.
15
Analog Ground (Input) - Ground reference.
13
Power (Input) - Positive power for the analog, digital, control port interfa ce, and serial audio
14
interface sections.
Mute Control (Output) - Control signal for optional mute circuit.
16
143
134
125
116
107
98
(Input/Output)
FILT+
- Input/Output for I2C data. Input for SPI data.
2
C Mode. Control signal used to select
DS582PP1 5
2. TYPICAL CONNECTION DIAGRAM
CS4341A
Serial Audio
Data
Processor
ExternalC lock
Micro-
Controlled
Configuration
2
3
4
5
6
7
8
1
SDIN
SCLK
LRCK
CS4341A
MCLK
SCL/CC LK
SDA/C DIN
AD0/CS
RST
AGND
14
VA
13
0.1 µF
AO UT A
MUTEC
FILT+
VQ
REF_GND
AO UT B
12
15
16
9
10
11
3.3 µF
+
10 k
.1 µF
3.3 µF
+
10 k
1µF
560
1µF
560
+3.3V or +5.0V
Ω
C
+
1µF
0.1 µF
Ω
C
C=
OPTIONAL
MUTE
CIRCUIT
R 560
+
L
π
4
Fs(R
L
560 )
Audio
Output A
R
L
Audio
O utput B
R
L
+
Ω
+
Ω
Figure 1. Typical Connection Diagram
6 DS582PP1
CS4341A
3. APPLICATIONS
3.1 Upgrading from the CS4341 to the CS4341A
The CS4341A is pin and functionally compatible with all CS4341 designs, operating at the standard audio
sample rates, that use pin 3 as a serial clock input. In addition to the features of the CS4341, the CS4341A
supports standard sample rates up to 192 kHz, as well as automatic mode detection for sample rates between 4 and 200 kHz. The automatic speed mode detection feature allows sample rate changes between
single, double and quad-speed modes without external intervention.
The CS4341A does not support an internal serial clock mode or sample rates between 50 kHz and 84 kHz
(unless otherwise stated), as does the CS4341.
3.2 Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will
depend on whether the Auto-Detect Defeat bit is enabled/disabled.
3.2.1 Auto-Detect Enabled
The Auto-Detect feature is enable d by default in the control port register 5.1. In this state, the
CS4341A will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK
frequency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified
range for each mode are not supported.
Input Sample Rate (FS)MODE
4kHz - 50kHz Single Speed Mode
84kHz - 100kHz Double Speed Mode
170kHz - 200kHz Quad Speed M ode
Table 1. CS4341A Auto-Detect
3.2.2 Auto-Detect Disabled
The Auto-Detect feature can be defeated via the control port register 5.1. In this state, the CS4341A
will not auto-detect the correct mode based on the input sample rate (Fs). The operational mode
must be set appropriately if Fs falls within one of the ranges illustrated in Table 2. Please refer to
section 5.1.1 for implementation details. Sample rates outside the specified range for each mode
are not supported.
MC1 MC0 Input Sample Rate (FS)MODE
0 0 4kHz - 50kHz Single Speed Mode
0 1 50kHz - 100kHz Double Speed Mode
1 0 100kHz - 200kHz Quad Speed Mode
Table 2. CS4341A Mode Select
DS582PP1 7
CS4341A
3.3 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)
clocks. The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK according to specified ratios. The s pecified ratios of MCLK to LRCK for each Speed Mode, along
with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 3-5.
Sample Rate
(kHz)
32 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 11.2896 16.9344 22.5792 33.8688 45.1584
48 12.2880 18.4320 24.5760 36.8640 49.1520
256x 384x 512x 768x 1024x*
MCLK (MHz)
Table 3. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64 8.1920 12.2880 16.3840 24.5760 32.7680
88.2 11.2896 16.9344 22.5792 33.8688 45.1584
96 12.2880 18.4320 24.5760 36.8640 49.1520
128x 192x 256x 384x 512x*
MCLK (MHz)
Table 4. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
176.4 22.5792 33.8688 45.1584
192 24.5760 36.8640 49.1520
128x 192x 256x*
MCLK (MHz)
Table 5. Quad-Speed Mode Standard Frequencies
* Requires MCLKDIV bit = 1 in the Mode Control 1 register (address 00h).
3.4 Digital Interface Format
The device will accept audio samples in several digital interface formats. The desired format is selected
via the DIF0, DIF1 and DIF2 bits in the Mode Control 2 register (see section 5.2.2) . For an illustration of
the required relationship between LRCK, SCLK and SDIN, see Figures 2-4.
LRCK
SCLK
SDIN +3 +2 +1+5 +4
MSB
-1 -2 -3 -4 -5
Left Channel
LSB
MSB
-1 -2 -3 -4
Figure 2. I2S Data
8 DS582PP1
Right Channel
+3 +2 +1+5 +4
LSB
CS4341A
LRCK
SCLK
SDIN +3 +2 +1+5 +4
MSB
-1 -2 -3 -4 -5
Left Channel
LSB
MSB
-1 -2 -3 -4
Right Channel
+3 +2 +1+5 +4
LSB
Figure 3. Left Justified up to 24-Bit Data
LRCK
SCLK
SDIN
MSB
Left Channel
LSB MSB
32 clocks
-6 -5 -4 -3 -2 -1-7+1 +2 +3 +4 +5
Figure 4. Right Justified Data
LSB -6 -5 -4 -3 -2 -1-7 MSB
Right Channel
+1 +2 +3 +4
+5
3.5 De-Emphasis Control
The device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48
kHz de-emphasis filter. Figure 5 shows the de-emphasis curve for Fs equa l to 44 .1 kH z. Th e fre que ncy
response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see
section 5.2.3 for the desired de-emphasis control.
NOTE: De-emphasis is only available in Single-Speed Mode.
Gain
dB
T1=50 µs
0dB
-1 0d B
3.18 3 kHz 10 .61 kH z
Figure 5. De-Emphasis Curve
3.6 Recommended Power-up Sequence
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to
the appropriate frequences, as discussed in section 3.2. In this state, the control port is reset to its
default settings and VQ will remain low.
2. Bring RST high. The device will remain in a low power s tate with VQ low.
3. Load the desired register settings while keeping the PDN bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximatel y 50µS
when the POR bit is set to 0. If the POR bit is set to 1, see section 3.7 for a complete description
of power-up timing.
F1 F2
T2 = 15 µs
Frequency
DS582PP1 9
CS4341A
3.7 Popguard® Transient Control
The CS4341A uses Popguard® technology to minimize the effects of output transients during power-up
and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters.
It is activated inside the DAC when the PDN bit or the RST pin is enabled/disabled and requires no other
external control, aside from choosing the appropriate DC-blocking capacitors.
3.7.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTL a nd AOU TR, are clampe d to
AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and
audio output begins. This gradual voltage ramping allows time f or the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.
3.7.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state by enabling
RST or PDN. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows
the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the
device may be turned off and the system is ready for the next power-on.
3.7.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking
capacitors have fully discharged before turning on the power or exiting the power-down state. If
not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the
device must remain in the power-down state is rela ted to the value of the DC -blocking capacitance.
For example, with a 3.3 µ F capacitor, the minimum power-down time will be approximately 0.4
seconds.
3.8 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4341A requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended
power arrangements, with VA connected to a clean supply. If the ground planes are split between digital
ground and analog ground, REF_GND & AGND should be connected to the analog ground plane.
Decoupling capacitors should be as clos e to the DAC as possible, with the low value ceramic capacitor
being the closest. To further minimze impedance, these capacitors should be located on the same layer as
the DAC.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0. 1µF, must
be positioned to minimize the electrical path from FILT+ to REF_GND (and VQ to REF_GND), and
should also be located on the same layer as the DAC. The CDB4341A evaluation board demonstrates the
optimum layout and power supply arrangements.
10 DS582PP1
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