Cirrus Logic CDB42L56 User Manual
Evaluation Board for CS42L56
USB
µ controller
CS42L56
S/PDIF Rx
(CS8416)
S/PDIF Tx
(CS8406)
FPGA
Oscillator
(socket)
I2C Interface
Reset
Reset
PLL
Tx SRC
(CS8421)
Analog Outputs
(Line + Headphone)
Analog Inputs
(Line + MIC)
External System
I/O Header
Rx SRC
(CS8421)
PSIA I/O Header
USB/
RS232
S/PDIF
Dout
S/PDIF
Din
CDB42L56
Features
Analog Line and Microphone Level Inputs
– 6 RCA and 3 Stereo 1/8” Jacks
– Compatible with Single-Ended and Pseudo-Diff.
Input Configurations
Analog Line and Headphone Outputs
– Stereo 1/8” Headphone Jack w/Input Detection
– 4 RCA Jacks for Headphone/Line Outputs
8 to 96 kHz S/PDIF Interface
– CS8416 Digital Audio Receiver
– CS8406 Digital Audio Transmitter
I/O Stake Header Accessibility
– External Control Port Headers
– External Direct and Buffered Serial Audio I/O
Headers
Multiple Power Supply options via USB, Battery or
External Power Supplies.
1.8 V to 3.3 V Selectable Logic Interface
FlexGUI S/W Control - Windows
– Pre-Defined & User-Configurable Scripts
®
Compatible
Description
The CDB42L56 is the ideal evaluation platform solution to test
and evaluate the CS42L56.The CS42L56 is a highly integrated, 24-bit, ultra-low power stereo codec based on multi-bit
delta-sigma modulation suitable for low power portable applications. Use of the board requires an analog/digital signal
source, an analyzer and power supplies. A Windows PC-compatible computer is also needed in order to configure the
CS42L56 and the board.
System timing can be provided by the CS8416 (on-board), by
the CS42L56 supplied with a master clock, by the on-board
crystal oscillator or via an I/O stake header with a DSP
connected.
th
RCA phono connectors and stereo 1/8
provided for CS42L56 analog inputs and HP/Line outputs.
Digital I/O connections are provided via RCA phono or optical
connectors to the CS8416 and CS8406 (S/PDIF Rx and Tx).
The CDB42L56 is programmed via the PC’s USB using Cirrus
Logic’s Microsoft
®
Windows®-based software (FlexGUI). The
evaluation board may also be configured to accept external
timing and data signals for operation in a user application
during system development.
ORDERING INFORMATION
CDB42L56 Evaluation Board
inch audio jacks are
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2014
(All Rights Reserved)
FEB '14
DS851DB1
CDB42L56
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................................. 4
1.1 Control Port and Board Configuration .............................................................................................. 4
1.2 Power ............................................................................................................................................... 4
1.3 Digital Input ....................................................................................................................................... 4
1.3.1 CS8416 S/PDIF Digital Audio Receiver .................................................................................. 4
1.3.1.1 CS8421 Sample Rate Converter (Tx SRC to CS42L56) ............................................. 5
1.4 Digital Output .................................................................................................................................... 5
1.4.1 CS8406 S/PDIF Digital Audio Transmitter .............................................................................. 5
1.4.2 CS8421 Sample Rate Converter (Rx SRC from CS42L56) .................................................... 5
1.5 FPGA ................................................................................................................................................ 5
1.6 Oscillator ........................................................................................................................................... 6
1.7 PLL ................................................................................................................................................... 6
1.8 I/O Stake Headers ............................................................................................................................ 6
1.9 CS42L56 Audio Codec ..................................................................................................................... 6
1.10 Analog Inputs .................................................................................................................................. 6
1.11 Analog Outputs ............................................................................................................................... 7
2. QUICK-START GUIDE ........................................................................................................................... 8
3. CONFIGURATION OPTIONS ................................................................................................................. 9
3.1 S/PDIF In to Analog Out and Analog In to S/PDIF Out .................................................................... 9
3.2 PSIA In to Analog Out and Analog In to PSIA Out ......................................................................... 10
4. SOFTWARE MODE CONTROL ........................................................................................................... 11
4.1 Board Configuration Tab ................................................................................................................ 12
4.2 Codec Configuration Tab ................................................................................................................ 13
4.3 Codec Analog Input Volume Tab .................................................................................................... 14
4.4 Codec DSP Engine Tab ................................................................................................................. 15
4.5 Codec Analog Output Volume Tab ................................................................................................. 16
4.6 Register Maps Tab ......................................................................................................................... 17
5. JUMPER SETTINGS AND SYSTEM CONNECTIONS ........................................................................ 18
6. PERFORMANCE PLOTS ..................................................................................................................... 21
7. CDB42L56 BLOCK DIAGRAM ............................................................................................................ 27
8. CDB42L56 SCHEMATICS ................................................................................................................... 28
9. CDB42L56 LAYOUT ............................................................................................................................ 33
10. REVISION HISTORY .......................................................................................................................... 38
LIST OF FIGURES
Figure 1. Quick-Start Board Layout ............................................................................................................. 8
Figure 2. S/PDIF In to Analog Out and Analog In to S/PDIF Out ................................................................ 9
Figure 3. PSIA In to Analog Out and Analog In to PSIA Out ..................................................................... 10
Figure 4. Board Configuration Tab ............................................................................................................ 12
Figure 5. Codec Configuration Tab ........................................................................................................... 13
Figure 6. Codec Analog Input Volume Tab ............................................................................................... 14
Figure 7. Codec DSP Engine Tab ............................................................................................................. 15
Figure 8. Codec Analog Output Volume Tab ............................................................................................ 16
Figure 9. Register Maps Tab - CS42L56 .................................................................................................. 17
Figure 10. THD+N vs. Freq. - Analog In to Digital Out .............................................................................. 21
Figure 11. THD+N vs. Amplitude - Analog In to Digital Out ......................................................................21
Figure 12. FFT - Analog In to Digital Out @ -1 dBFS ............................................................................... 21
Figure 13. FFT - Analog In to Digital Out @ -60 dBFS ............................................................................. 21
Figure 14. FFT - Analog In to Digital Out - No Input ................................................................................. 22
Figure 15. FFT Crosstalk - Analog In to Digital Out
@ -1 dBFS ................................................................................................................................................ 22
Figure 16. Freq. Response - Analog In to Digital Out ............................................................................... 22
2 DS851DB1
CDB42L56
Figure 17. Fade-to-Noise Linearity - Analog In to Digital Out ................................................................... 22
Figure 18. THD+N vs. Freq. - Digital In to HP Out .................................................................................... 22
Figure 19. THD+N vs. Amplitude - Digital In to HP Out ............................................................................ 22
Figure 20. THD+N vs. Volume - Digital In to HP Out ................................................................................ 23
Figure 21. FFT - Digital In to HP Out @ 0 dBFS ....................................................................................... 23
Figure 20. FFT - Digital In to HP Out @ -60 dBFS .................................................................................... 23
Figure 21. FFT - Digital In to HP Out - No Input ........................................................................................ 23
Figure 22. FFT - Digital In to HP Out - No Input Wideband ......................................................................23
Figure 23. FFT Crosstalk - Digital In to HP Out @ 0 dBFS .......................................................................23
Figure 24. Freq. Response - Digital In to HP Out ..................................................................................... 24
Figure 25. Fade-to-Noise Linearity- Digital In to HP Out ........................................................................... 24
Figure 26. THD+N vs. Freq. - Digital In to Line Out .................................................................................. 24
Figure 27. THD+N vs. Amplitude - Digital In to Line Out .......................................................................... 24
Figure 28. THD+N vs. Volume - Digital In to Line Out .............................................................................. 25
Figure 29. FFT Crosstalk - Digital In to Line Out @ 0 dBFS .....................................................................25
Figure 28. FFT - Digital In to Line Out @ 0 dBFS ..................................................................................... 25
Figure 29. FFT - Digital In to Line Out @ -60 dBFS .................................................................................. 25
Figure 30. FFT - Digital In to Line Out - No Input ...................................................................................... 25
Figure 31. FFT - Digital In to Line Out - No Input Wideband ..................................................................... 25
Figure 32. Freq. Response - Digital In to Line Out .................................................................................... 26
Figure 33. Fade-to-Noise Linearity- Digital In to Line Out ......................................................................... 26
Figure 34. Block Diagram .......................................................................................................................... 27
Figure 35. CS42L56 & Analog I/O (Schematic Sheet 1) ........................................................................... 28
Figure 36. S/PDIF & Digital Interface (Schematic Sheet 2) ......................................................................29
Figure 37. PLL, oscillator and external I/O connections (Schematic Sheet 3) .......................................... 30
Figure 38. Microcontroller and FPGA (Schematic Sheet 4) ...................................................................... 31
Figure 39. Power (Schematic Sheet 5) ..................................................................................................... 32
Figure 40. Silk Screen ............................................................................................................................... 33
Figure 41. Top-Side Layer ........................................................................................................................ 34
Figure 42. GND (Layer 2) .......................................................................................................................... 35
Figure 43. Power (Layer 3) ....................................................................................................................... 36
Figure 44. Bottom Side Layer ................................................................................................................... 37
LIST OF TABLES
Table 1. Analog Input Configuration Jumper and Resistor Settings ........................................................... 7
Table 2. System Connections ................................................................................................................... 18
Table 3. Jumper Settings .......................................................................................................................... 19
DS851DB1 3
CDB42L56
1. SYSTEM OVERVIEW
The CDB42L56 evaluation platform provides analog and digital interfaces to the CS42L56 and allows for external
DSP and I²C
an external +5 V supply. On-board voltage regulators provide power to the digital and analog cores of the CS42L56.
The CDB42L56 is configured using Cirrus Logic’s Windows-compatible FlexGUI software to read/write to device
registers.
This section describes the various components on the CDB42L56 and how they are used with the CS42L56. Section
2 on page 8 is a simplified quick connect guide provided for user convenience and may be used to quickly configure
the CS42L56. Section 3 on page 9 describes some of the configurations available for transmitting and receiving audio signals. Section 4 on page 11 provides software configuration details. Section 5 on page 18 provides a descrip-
tion of all stake headers and connectors, including the default factory settings of all jumpers. Section 6 on page 21
provides typical performance plots. The CDB42L56 schematic and layout set is shown in Figures 35 through 44.
1.1 Control Port and Board Configuration
interconnects to the board. On-board peripherals are powered either from the USB connection or from
The CDB42L56 evaluation board must be programmed using the Windows compatible software (Cirrus Logic FlexGUI) provided. This software allows the user to program the registers of all the programmable components on the board using an I²C interface.
The GUI interfaces with an on-board micro controller through either the USB or the serial port connector.
For a detailed explanation on software controls, refer to Section 4 on page 11.
Alternatively, the I²C interface to the CS42L56 can be directly accessed through an I/O header (J109) to
accept external timing and signals in a user application during system development.
1.2 Power
Power is supplied to the evaluation board through either the +5.0 V test points or the VBUS supply from the
USB. NOTE: The minimum current required for board operation is approximately 300 mA. It may therefore
be necessary to connect the CDB42L56 directly to the USB port on the PC as opposed to a hub or keyboard
port where the current might be limited.
Jumpers connect the CS42L56’s supplies to a low dropout regulated voltage of +1.8 V, +2.5 V or +3.3 V for
VL and +1.8 V or +2.5 V for VLDO, VA and VCP. A selection for a 1.8 V supply from a buck regulator is also
available, providing a more efficient means of evaluating the CS42L56’s performance when powered from
batteries (3 AAA battery connectors are available on the bottom side of the CDB).
For current measurement purposes only, a 1 ohm series resistor is connected to each supply. The current
is easily calculated by measuring the voltage drop across this resistor. NOTE: The stake headers connected
in parallel with these resistors must be shunted with the supplied jumper during normal operation.
WARNING: Please refer to the CS42L56 data sheet for allowable voltage levels.
1.3 Digital Input
1.3.1 CS8416 S/PDIF Digital Audio Receiver
The CS8416 S/PDIF receiver converts an incoming S/PDIF data input stream into PCM data for the
CS42L56 (through the “Transmit” (Tx) Sample Rate Converter (SRC)).
A complete description of the CS8416 (Figure 36 on page 29) and a discussion of the digital audio interface can be found in the CS8416 data sheet.
4 DS851DB1
Configuration of the CS8416 is made using controls in the “Board Configuration” tab of the Cirrus FlexGUI
software. Section 3. “Configuration Options” on page 9 and Section 4. “Software Mode Control” on page 11
provide configuration examples and software details.
1.3.1.1 CS8421 Sample Rate Converter (Tx SRC to CS42L56)
The CS8421 Tx SRC receives PCM digital audio data from either the CS8416 S/PDIF receiver or the AP
PSIA header and synchronizes this data with the CS42L56, regardless of the CS42L56’s master and audio clocks.
A complete description of the CS8421 (Figure 36 on page 29) and a discussion of the digital audio interface can be found in the CS8421 data sheet.
Configuration and routing selections for the CS8421 are made using controls in the “Board Configuration”
tab of the Cirrus FlexGUI software. Section 3. “Configuration Options” on page 9 and Section 4. “Software
Mode Control” on page 11 provide configuration examples and software details.
1.4 Digital Output
1.4.1 CS8406 S/PDIF Digital Audio Transmitter
The CS8406 converts the PCM data generated from the CS42L56 (through the “Receive” (Rx) SRC) to
the standard S/PDIF data stream.
CDB42L56
A complete description of the CS8406 (Figure 36 on page 29) and a discussion of the digital audio interface can be found in the CS8406 data sheet.
Configuration of the CS8406 is made using controls in the “Board Configuration” tab of the Cirrus FlexGUI
software. Section 3. “Configuration Options” on page 9 and Section 4. “Software Mode Control” on
page 11 provide configuration examples and software details.
1.4.2 CS8421 Sample Rate Converter (Rx SRC from CS42L56)
The CS8421 Rx SRC receives PCM digital audio data from the CS42L56 and synchronizes this data with
either the CS8406 S/PDIF transmitter or the AP PSIA headers, regardless of the CS42L56’s master and
audio clocks.
A complete description of the CS8421 (Figure 36 on page 29) and a discussion of the digital audio interface can be found in the CS8421 data sheet.
Configuration and routing selections for the CS8421 are made using controls in the “Board Configuration”
tab of the Cirrus FlexGUI software.Section 3. “Configuration Options” on page 9 and Section 4. “Software
Mode Control” on page 11 provide configuration examples and software details.
1.5 FPGA
The FPGA controls the digital signal routing between the CS42L56, CS8406, CS8416, CS8421 (Tx SRC
and Rx SRC), PLL and the I/O stake header. It also provides a divider for the system master clock from an
on-board oscillator to the required devices. Figures 2 and 3 in Section 3 show how the FPGA can route
clocks and data in order to allow the user to test the CS42L56 in various setups.
Configuration and routing selections for the FPGA are made using controls in the “Board Configuration” tab
of the Cirrus FlexGUI software. Section 4 on page 11 provides software configuration details.
DS851DB1 5
1.6 Oscillator
The socketed on-board oscillator (Y1) can be selected as the system master clock source by using the selections on the “Board Configuration” tab of the Cirrus FlexGUI. Section 4 on page 11 provides software
configuration details.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The device footprint on the
board will accommodate half-can or full-can sized oscillators.
1.7 PLL
An on-board PLL is used with the FPGA to generate the serial port sub-clocks for the CS42L56’s serial port
when the CS42L56 is set to slave mode. The sub-clocks’ frequencies are selected on the “Board Configuration” tab of the Cirrus FlexGUI. Section 4 on page 11 provides software configuration details.
1.8 I/O Stake Headers
Headers J104 and J109 (Figure 35 on page 28) provide unbuffered bidirectional access to the CS42L56
serial port and control port, respectively. For regular operation, the left two pins on all rows should be shunted to allow the CS42L56 to receive serial and control port data and clocks from the on-board FPGA.
Alternatively, the stake headers provide access to the CS42L56 from external systems simply by removing
all the shunt jumpers from the “USB” and “CDB I/O” positions. The user may then connect a ribbon cable
connector to the “Ext. Sys. Connect” pins for external control of board functions. A single row of “GND” pins
is provided to maintain signal ground integrity. Two unpopulated pull-up resistors are also available should
the user choose to use the CDB42L56 logic supply (VL) externally.
CDB42L56
If an external system is used to interface with the CS42L56 through headers J104 and J109, the digital I/O
logic voltage levels must be selected cautiously since the lines between the headers and the device are not
buffered. Please refer to the CS42L56 product data sheet for a detailed explanation on digital I/O interface
specifications. Selections are made using the “Board Configuration” tab of the Cirrus FlexGUI software.
Section 4 on page 11 provides software configuration details.
1.9 CS42L56 Audio Codec
A complete description of the CS42L56 (U3 - Figure 35 on page 28) can be found in the CS42L56 product
data sheet.
The CS42L56 is configured using the Cirrus Logic Windows compatible software FlexGUI. The device configuration registers are directly accessible via the “Register Maps” tab of the Cirrus FlexGUI software. This
tab provides low-level control of each bit. For easier configuration, additional tabs provide high-level control.
Section 4 on page 11 provides software configuration details.
1.10 Analog Inputs
The analog input circuitry on the CDB42L56 has been designed to allow for testing of the CS42L56 in all its
possible analog input configurations. Line or microphone level analog input signals can be provided to the
analog inputs on the CS42L56 through RCA or microphone input jacks (Figure 35 on page 28). Stake header J6 allows the user to select (with jumpers installed) the CS42L56 as the microphone bias source for each
microphone input (CAUTION: Only 2 jumpers may be installed at a time).
Headers J19 and J20 are used to select the desired input for pins AIN3A/AIN1REF and AIN3B/AIN2REF
on the CS42L56. These headers can be used to select between either a single-ended or a pseudo-differential analog input setup. Table 1 provides jumper and resistor settings for the various analog input configurations allowed on the CS42L56. The shaded rows in the table indicate the most commonly used
configurations and do not require any extra resistor modifications.
6 DS851DB1
CDB42L56
No. Analog Input 1 Analog Input 2 Analog Input 3 Jumper Settings Resistors
AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B J19 J20
1. S.E. S.E. S.E. S.E. S.E. S.E. 1-2 2-3 - -
2. S.E. P.Diff. S.E. S.E. - S.E. 2-3 2-3 R86 R12
3. P.Diff. S.E. S.E. S.E. - S.E. 2-3 2-3 R41 R58
4. S.E. S.E. S.E. P.Diff. S.E. - 1-2 1-2 R109 R78
5. S.E. S.E. P.Diff. S.E. S.E. - 1-2 1-2 R51 R43
6.
S.E. P.Diff. P.Diff. S.E. - - 2-3 1-2
7. S.E. P.Diff. S.E. P.Diff. - - 2-3 1-2
8. P.Diff. S.E. S.E. P.Diff. - - 2-3 1-2
9. P.Diff. S.E. P.Diff. S.E. - - 2-3 1-2
10. S.E. S.E. P.Diff. P.Diff. S.E. - 1-2 1-2 - -
11. P. D i ff . P.Diff. S.E. S.E. - S.E. 2-3 2-3 - -
12. S.E. P.Diff. P.Diff. P.Diff. - - 2-3 1-2 R86 R12
13. P.Diff. S.E. P.Diff. P.Diff. - - 2-3 1-2 R41 R58
14. P.Diff. P.Diff. S.E. P.Diff. - - 2-3 1-2 R109 R78
15. P.Diff. P.Diff. P.Diff. S.E. - - 2-3 1-2 R51 R43
16. P. D i ff . P.Diff. P.Diff. P.Diff. - - 2-3 1-2 - -
Table 1. Analog Input Configuration Jumper and Resistor Settings
to Populate
R86
R51
R86
R109
R41
R109
R41
R51
Resistors to
Unpopulate
R12
R43
R12
R78
R58
R78
R58
R43
Notes:
1. Use headers J7 and J11 to select input signal ground reference (in pseudo-differential mode) as either
the CDB42L56 board ground or the signal ground reference from the external system which the
CDB42L56 receives through the shield of the analog input cable.
2. Resistor modifications are only required if single-ended and pseudo-differential input configurations
need to be used simultaneously on the “A” and “B” inputs of the same analog input channel.
3. Resistor population settings for resistors not shown in the table should be the same as factory defaults.
Figure 35 on page 28 illustrates how the analog inputs are connected and routed. Table 3 on page 19 de-
tails the jumper selections.
1.11 Analog Outputs
The CS42L56 analog outputs can be monitored on RCA jacks J15 and J17 for line and J37 and J38 for
headphone outputs. Additionally, the CS42L56 headphone outputs can also be monitored on stereo headphone jack J1 which also allows the user to test the CS42L56’s headphone detect functionality. The
CDB42L56 on-board circuitry drives the headphone detect pin low when a headphone is inserted in J1.
Headers J12 and J4 can be used to select optional 16 or 32 resistive loads for headphone outputs.
Headers J2 and J3 give users the option of receiving filtered or unfiltered outputs on the RCA headphone
output jacks.
Figure 35 on page 28 illustrates how the analog outputs are connected and routed. Table 3 on page 19 pro-
vides details on jumper selections for filtered or unfiltered outputs.
DS851DB1 7
CDB42L56
1
2
3
4
5
6
7
Set ju mper se tting s for VL to 3 .3 V
and VCP, VLDO and VA to 1.8 V.
J48, J53, J52, J74, J7 and
J11 should be shunted.
Set Board Power setting to USB.
Left pins on J109 and
J104 should be
shunted.
Provide digital inputs to the
board either through the S/
PDIF optical or RCA phono
connectors or through the
PSIA I/O header J78.
Receive digital outputs from the board either
through the S/PDIF optical or RCA phono
connectors or through the PSIA I/O header
J40.
Monitor analog output either via HP or Line Channel
RCA phono connectors or HP stereo jack.
*Select which output channel will be used through
“CODEC configuration” tab in software
Provide Analog
Inputs to board.
*Select which input
channel will be used
through “CODEC
configuration” tab in
software
8
9
10
Connect USB to board.
Open Flex GUI software
on PC and load quick
setup script.
Set desired jumper
settings for J12, J4,
J2, J3.
2. QUICK-START GUIDE
The following figure is a simplified quick-start guide made for user convenience. The guide configures the board with
a 1.8 V power supply to VLDO, VA and VCP and a 3.3 V power supply to VL. The user may choose from steps 7
through 10 depending on the desired measurement. Refer to Section 3 on page 9 for details on how the various
components on the board interface with each other in different board configuration modes. Refer to Section 4 on
page 11 for descriptions on control settings in the Cirrus FlexGUI software.
.
8 DS851DB1
Figure 1. Quick-Start Board Layout
3. CONFIGURATION OPTIONS
Line Output
B
A
HP Output
J21
32
32
16
16
J4
J12
B
A
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
J19
J20
LRCK
CS42L56
SCLK
SDIN
(SLAVE)
MCLK
SDOUT
LINEOUTB
LINEOUTA
HPOUTB
HPOUTA
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
S/PDIF Rx
(CS8416)
RX.LRCK
RX.SCLK
RX.SDOUT
S/PDIF
IN
(MASTER)
RX.RMCK
TX.SCLK
TX.LRCK
TX.SDIN
S/PDIF
OUT
(MASTER)
S/PDIF Tx
(CS8406)
TX.OMCK
FPGA
PLL
Divider
DividerDivider
On-Board
Oscillator
Tx SRC
(CS8421)
(SLAVE)
ISCLK
ILRCK
SDIN
OSCLK
OLRCK
SDOUT
XTI
Rx SRC
(CS8421)
(SLAVE)
ISCLK
ILRCK
SDIN
OSCLK
OLRCK
SDOUT
XTI
Figure 2. S/PDIF In to Analog Out and Analog In to S/PDIF Out
This section shows two common configurations of the CDB42L56.
3.1 S/PDIF In to Analog Out and Analog In to S/PDIF Out
The CS42L56 ADC and DAC performance can be tested by loading the “SPDIF In to Analog Out -- Analog
In to S/PDIF Out” quick setup file provided with the software package. The script configures the digital clock
and data signal routing on the board as shown in Figure 2. The quick setup scripts provided in the software
assume that a 24.000 MHz on-board oscillator is populated in Y1.
A S/PDIF input must be provided as the S/PDIF Tx (CS8406) uses the RMCK signal from the S/PDIF Rx
(CS8416) for synchronization in this configuration, as shown in the Figure 2.
CDB42L56
DS851DB1 9
3.2 PSIA In to Analog Out and Analog In to PSIA Out
Line Output
B
A
HP Output
J21
32
32
16
16
J4
J12
B
A
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
J19
J20
LRCK
CS42L56
SCLK
SDIN
(SLAVE)
MCLK
SDOUT
LINEOUTB
LINEOUTA
HPOUTB
HPOUTA
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
FPGA
PLL
Divider
DividerDivider
On-Board
Oscillator
Tx SRC
(CS8421)
(SLAVE)
ISCLK
ILRCK
SDIN
OSCLK
OLRCK
SDOUT
XTI
PSIA Tx (J78)
TX.SCLK
TX.LRCK
TX.SDOUT
PSIA Rx (J40)
RX.SCLK
RX.LRCK
RX.SDIN
TX.MCLK
RX.MCLK
Rx SRC
(CS8421)
(SLAVE)
ISCLK
ILRCK
SDIN
OSCLK
OLRCK
SDOUT
XTI
(MASTER)
(MASTER)
Figure 3. PSIA In to Analog Out and Analog In to PSIA Out
The CS42L56 ADC and DAC performance can be tested by loading the “PSIA In to Analog Out -- Analog
In to PSIA Out” quick setup file provided with the software package. The script configures the digital clock
and data signal routing on the board as shown in Figure 2. The quick setup scripts provided in the software
assume that a 24.000 MHz on-board oscillator is populated in Y1.
CDB42L56
10 DS851DB1
CDB42L56
4. SOFTWARE MODE CONTROL
The CDB42L56 may be used with the Microsoft® Windows®-based FlexGUI graphical user interface, allowing software control of the CS42L56, FPGA, CS8421, CS8416 and CS8406 registers. The latest control software may be
downloaded from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI are provided
as follows:
1. Download and install the FlexGUI software as instructed on the web site.
2. Connect the CDB to the host PC using a USB cable.
3. Launch the Cirrus FlexGUI. Once the GUI is launched successfully, all registers are set to their default reset
state.
4. Refresh the GUI by clicking on the “Update” button. The default state of all registers are now visible.
For standard set-up:
5. Set up the signal routing in the “Board Configuration” tab as desired.
6. Set up the CS42L56 in the “Codec Configuration”, “Codec Analog Input Volume”, “Codec DSP Engine”, “Codec Analog Output Volume” and “Register Maps” tabs as desired.
7. Begin evaluating the CS42L56.
For quick set-up, the CDB42L56 may, alternatively, be configured by loading a predefined sample script file:
8. On the File menu, click "Restore Board Registers..."
9. Browse to Boards\CDB42L56\Scripts\.
10. Choose any one of the provided scripts to begin evaluation.
To create personal scripts files:
11. On the File menu, click “Save Board Registers...”
12. Enter any name that sufficiently describes the created setup.
13. Choose the desired location and save the script.
14. To load this script, follow the instructions from step 8 above.
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4.1 Board Configuration Tab
The “Board Configuration” tab provides high-level control of signal routing on the CDB42L56. The controls
in this tab are used to setup the CS8416, CS8406, Tx SRC, Rx SRC and the FPGA routing and are divided
into separate control groups for each of these individual devices. A description of each control group is outlined below. This tab also includes a drop down menu with a list of quick-setup configurations. Selecting a
quick-setup from the drop down box, the software loads a predefined configuration for the different devices
on the board. Section 3 on page 9 provides details on some quick-setup configurations.
FPGA Routing - Includes controls to setup the FPGA for using the S/PDIF or the PSIA test interface and for
setting up clock and signal routing for CS42L56 in master/slave mode. This group also has controls for selecting SCLK and LRCK frequencies, perform divide operations on the oscillator.
CS8416 S/PDIF Receiver Control - Controls for the CS8416.
CS8406 S/PDIF Transmitter Control - Controls for the CS8406.
CS8421 SRC Control - Controls for the receive and transmit SRCs. To configure, select the desired SRC
from the drop down menu and then click the update button.
Update - Reads all registers in the FPGA, CS42L56, CS8416, CS8406 and CS8421 and shows the current
values in the GUI.
Reset - Resets FPGA to default routing configuration.
CDB42L56
Figure 4. Board Configuration Tab
12 DS851DB1
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