Cirrus Logic CS42L50-KN, CDB42L50 Datasheet

CS42L50

Low Voltage, Stereo CODEC with Headphone Amp

Features

l 28-Pin CASON package l 1.8 to 3.3 Volt supply l 24-Bit conversion / 96 kHz sample rate l 96 dB ADC/DAC dynamic range at 3 V supply l -88/-85 dB ADC/DAC THD+N l 19 mW playback power consumption @ 1.8 V l Microphone or Line input amplifier with up to

32dB of gain

l 2:1 stereo mux l Digital volume control on inputs and outputs

– 96 dB attenuation, 1 dB step size

l Digital bass and treble boost on outputs

– Selectable corner frequencies

l Dynamic range compression and limiting l De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz l Headphone amplifier

– 26 mW power output into 16 W load @ 3.0V

supply – -80 dB THD+N – 34 dB analog attenuation and mute

l ATAPI mixing functions

I I

SCL SDA

Description

The CS42L50 is a highly integrated, 24-bit, 96 kHz audio codec.

This device is based on delta-sigma modulation allowing infinite adjustment of the sample rate between 8 kHz and 100 kHz simply by changing the master clock frequency.

The CS42L50 contains a 2:1 stereo mux, programmable analog gain control, and digital attenuation on the analog inputs. The output D/A converters include digital bass and treble boost, dynamic range compression, limiting, mixing, volume control and de-emphasis.

The CS42L50 operates from a +1.8 V to +3.3 V supply. These features are ideal for portable MP3 and MD recorders, CD and DVD recorders, digital camcorders, and other portable systems that require extremely low power consumption in a minimal amount of space.

ORDERING INFORMATION

CS42L50-KN 28-pin CASON, -10 to 70 °C CDB42L50 Evaluation Board

RST

LRCK

SCLK

SDIN

SDOUT

Control Port

Serial Port

Attenuator

Compression

De-emphasis

0-96 dB

Digital Volume Control

Bass/Treble

Boost

Limiting

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

Analog

Digital

Filters

MCLK

Volume Control

Analog

MUX

Volume Control

i a

Compensation

MUTEC

Gain

12 dB

Gain

12 dB

∆Σ

DAC

∆Σ

Digit al Filters

DAC

Analog

Filter

Analog

Filter

ADC

Headphone

Line

Amplifier

HP_A

HP_B

AOUT_A

AOUT_B

AIN_L1

AIN_L2

AIN_R1

AIN_R2

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

AUG ‘01

DS544PP1

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5

ANALOG INPUT CHARACTERISTICS .................................................................................... 5

ANALOG OUTPUT CHARACTERISTICS ................................................................................ 7

POWER AND THERMAL CHARACTERISTICS..................................................................... 10

DIGITAL CHARACTERISTICS ............................................................................................... 11

ABSOLUTE MAXIMUM RATINGS ......................................................................................... 11

RECOMMENDED OPERATING CONDITIONS ..................................................................... 11

SWITCHING CHARACTERISTICS ........................................................................................ 12

SWITCHING CHARACTERISTICS - CONTROL PORT......................................................... 14

2. TYPICAL CONNECTION DIAGRAM ....................................................................................... 15

3. REGISTER QUICK REFERENCE ........................................................................................... 16

4. REGISTER DESCRIPTION ..................................................................................................... 18

4.1 ADC (address 0010000) .................................................................................................. 18

4.1.1 I/O and Power Control (address 01h) .......................................................................... 18

4.1.2 20DB Gain Boost (BOOST) .......................................................................................... 18

4.1.3 Analog Input Multiplexer (AINMUX) ............................................................................... 18

4.1.4 Power Down (PDN)........................................................................................................ 18

4.1.5 Control Port Enable (CP_EN) ........................................................................................ 18

4.1.6 Interface Control (address 02h) .................................................................................... 19

4.1.7 Master Clock Divide (MCLKDIV)................................................................................... 19

4.1.8 Master Clock Ratio (RATIO) ......................................................................................... 19

4.1.9 Master Mode (MASTER)............................................................................................... 19

4.1.10 Digital Interface Format (DIF) ..................................................................................... 19

4.1.11 Analog I/O Control (address 03h) ............................................................................... 20

4.1.12 Left/Right Channel Mute (MUTE)............................................................................... 20

4.1.13 Soft Ramp and Zero Cross Enable (SOFT/ZC) ......................................................... 20

4.1.14 Independent Volume Control Enable (INDVC) .......................................................... 21

4.1.15 Left Channel Volume = Right Channel Volume (L=R) ............................................... 21

4.1.16 High-Pass Filter Freeze (HPFREEZE)....................................................................... 21

4.1.17 Volume Control: Left Channel (address 04h) & Right Channel (address 05h) ............ 22

4.1.18 Left/Right Analog Gain (address 06h) ........................................................................ 22

4.1.19 Clip Detection Status (address 07h) .......................................................................... 23

4.2 DAC (Address = 0010001) ............................................................................................... 23

4.2.1 Power and Muting Control (address 01h) .................................................................... 23

4.2.2 Auto-Mute (AMUTE) ..................................................................................................... 23

4.2.3 Soft Ramp and Zero Cross Control (SZC) ..................................................................... 23

4.2.4 Power Down Headphone Amplifier (PDNHP) ................................................................ 24

CS42L50

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found

2 DS544PP1

at http://www.cirrus.com

CS42L50

4.2.5 Power Down Line Amplifier (PDNLN)............................................................................ 24

4.2.6 Power Down (PDN) ....................................................................................................... 24

4.2.7 Control Port Enable (CP_EN) ........................................................................................ 24

4.2.8 Channel A Analog Headphone Attenuation Control (address 02h) (HVOLA) .............. 25

4.2.9 Channel B Analog Headphone Attenuation Control (address 03h) (HVOLB) .............. 25

4.2.10 Channel A Digital Volume Control (address 04h) (DVOLA) ....................................... 25

4.2.11 Channel B Digital Volume Control (address 05h) (DVOLB) ....................................... 25

4.2.12 Tone Control (address 06h)........................................................................................ 26

4.2.13 Bass Boost Level (BB)................................................................................................. 26

4.2.14 Treble Boost Level (TB)............................................................................................... 26

4.2.15 Mode Control (address 07h) ....................................................................................... 27

4.2.16 Bass Boost Corner Frequency (BBCF) ....................................................................... 27

4.2.17 Treble Boost Corner Frequency (TBCF) ..................................................................... 27

4.2.18 Channel A Volume = Channel B Volume (A=B) .......................................................... 27

4.2.19 De-Emphasis Control (DEM) ....................................................................................... 28

4.2.20 Digital Volume Control Bypass (VCBYP) .................................................................... 28

4.2.21 Volume and Mixing Control (address 0Ah) ................................................................. 28

4.2.22 Tone Control Mode (TC).............................................................................................. 28

4.2.23 Tone Control Enable (TC_EN) .................................................................................... 28

4.2.24 ATAPI Channel Mixing and Muting (ATAPI)................................................................ 29

4.2.25 Mode Control 2 (address 0Bh) ................................................................................... 29

4.2.26 Master Clock Divide Enable (MCLKDIV) ..................................................................... 29

4.2.27 Line Amplifier Gain Compensation (LINE)................................................................... 29

4.2.28 Digital Interface Format (DIF) ...................................................................................... 30

5. PIN DESCRIPTIONS ............................................................................................................... 31

6. APPLICATIONS ...................................................................................................................... 33

6.1 Grounding and Power Supply Decoupling ....................................................................... 33

6.2 Clock Modes .................................................................................................................... 33

6.3 EP73xx Serial Port Interface ........................................................................................... 33

6.4 De-Emphasis ................................................................................................................... 33

6.5 Recommended Power-up Sequence ............................................................................... 33

6.6 Optional External Headphone Mute ................................................................................ 33

7. CONTROL PORT INTERFACE ............................................................................................... 33

7.1 Memory Address Pointer (MAP) ...................................................................................... 35

7.2 INCR (Auto Map Increment Enable) ................................................................................. 35

7.3 MAP0-3 (Memory Address Pointer).................................................................................. 35

8. PARAMETER DEFINITIONS ................................................................................................... 44

9. REFERENCES ......................................................................................................................... 44

10. PACKAGE DIMENSIONS ..................................................................................................... 45

LIST OF FIGURES

Figure 1. SCLK to LRCK and SDIN, Slave Mode .................................................... 13

Figure 2. SCLK to LRCK and SDIN, Master Mode .................................................. 13

Figure 3. Control Port Timing - I

Figure 4. CS42L50 Typical Connection Diagram .................................................... 15

Figure 5. Control Port Timing .................................................................................. 35

Figure 6. Decimation Filter Single Speed Stopband Rejection ............................... 36

Figure 7. Decimation Filter Single Speed Transition Band ...................................... 36

Figure 8. Decimation Filter Single Speed Transition Band (Detail) ......................... 36

Figure 9. Decimation Filter Single Speed Passband Ripple ................................... 36

Figure 10.Decimation Filter Double Speed Stopband Rejection .............................. 36

Figure 11.Decimation Filter Double Speed Transition Band .................................... 36

Figure 12.Decimation Filter Double Speed Transition Band (Detail) ........................ 37

DS544PP1 3

C‚ ......................................................................... 14

Figure 13.Decimation Filter Double Speed Passband Ripple .................................. 37

Figure 14.Interpolation Filter Single Speed Stopband Rejection .............................. 38

Figure 15.Interpolation Filter Single Speed Transition Band .................................... 38

Figure 16.Interpolation Filter Single Speed Transition Band (Detail) ....................... 38

Figure 17.Interpolation Filter Single Speed Passband Ripple .................................. 38

Figure 18.Interpolation Filter Double Speed Stopband Rejection ............................ 38

Figure 19.Interpolation Filter Double Speed Transition Band ................................... 38

Figure 20.Interpolation Filter Double Speed Transition Band (Detail) ...................... 39

Figure 21.Interpolation Filter Double Speed Passband Ripple ................................. 39

Figure 22.Line Input Test Circuit .............................................................................. 39

Figure 23.Line Output Test Load .............................................................................. 40

Figure 24.Headphone Output Test Load .................................................................. 40

Figure 25.Left Justified, up to 24-bit data ................................................................. 41

Figure 26.Right Justified, 16-bit data ........................................................................ 41

Figure 27.Right Justified, 24-bit data ........................................................................ 41

Figure 28.Right Justified, 18-bit data ........................................................................ 42

Figure 29.Right Justified, 20-bit data ........................................................................ 42

Figure 30.I2S, up to 24-bit data ................................................................................ 42

Figure 31.De-Emphasis Curve ................................................................................. 43

Figure 32.ATAPI Block Diagram ............................................................................... 43

Figure 33.Package Dimensions ................................................................................ 45

Figure 34.Package Top and Side Views .................................................................. 46

Figure 35.Package Bottom View .............................................................................. 47

CS42L50

LIST OF TABLES

Table 1. Example Analog Volume Settings ...................................................................................25

Table 2. Example Digital Volume Settings ....................................................................................26

Table 3. Example Bass Boost Settings .........................................................................................26

Table 4. Example Treble Boost Settings .......................................................................................27

Table 5. ATAPI Decode.................................................................................................................29

Table 6. Digital Interface Format ...................................................................................................30

4 DS544PP1

1. CHARACTERISTICS/SPECIFICATIONS

CS42L50

ANALOG INPUT CHARACTERISTICS (T

GND = 0 V; MCLK = 12.288 MHz; Fs for Single Speed Mode = 48 kHz, SCLK = 3.072 MHz, Fs for Double Speed Mode = 96 kHz, SCLK = 6.144 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Input is 997Hz sine wave.)

Parameter Symbol

Analog Input Characteristics for VA = 1.8 V

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit -1 dB

-20 dB

-60 dB

16-Bit -1 dB

-20 dB

-60 dB

Dynamic Range (PGA on)*

0 dB Gain A-weighted

unweighted

12 dB Gain A-weighted

unweighted

Total Harmonic Distortion + Noise (PGA on)* (Note 1) 0 dB Gain, 18 to 24-Bit -1 dB

12 dB Gain, 18 to 24-Bit -1 dB

Analog Input Characteristics for VA = 3.0 V

Dynamic Range A-weighted

unweighted

Total Harmonic Distortion + Noise (Note 1)

18 to 24-Bit -1 dB

-20 dB

-60 dB

16-Bit -1 dB

-20 dB

-60 dB

Dynamic Range (PGA on)*

0 dB Gain A-weighted

unweighted

12 dB Gain A-weighted

unweighted

Total Harmonic Distortion + Noise (PGA on)* (Note 1) 0 dB Gain, 18 to 24-Bit -1 dB

12 dB Gain, 18 to 24-Bit -1 dB

*PGA : Programmable Gain Amplifier

THD+N

= 25° C; GND = 0 V Logic "1" = VL = 1.8 V; Logic "0" =

Single Speed Mode Double Speed Mode

UnitMin Typ Max Min Typ Max

TBD TBD9390

TBD TBD9693

-88

-70

-30

-86

-68

-28

90 87 85 82

85 83

-88

-73

-33

-86

-68

-28

93 90 88 85

78 73

TBD

TBD TBD9491

-88

-71

-31

-86

-68

-28

TBD TBD9895

89 86 86 83

84 82

-85

-75

-35

-83

-65

-28

92 89 89 86

77 76

TBD

dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB

DS544PP1 5

CS42L50

Single Speed Mode Double Speed Mode

Parameter Symbol

Analog Input Characteristics for VA = 1.8 - 3.3V

Interchannel Isolation 1 kHz - 90 - - 90 - dB

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Offset Error (with HPF Active) - - 0 - - 0 LSB

Full Scale Input Voltage TBD VA/3.6 TBD TBD VA/3.6 TBD Vrms

Gain Drift - 100 - - 100 - ppm/°C

Input Resistance 10 - - 10 - - kΩ

Input Capacitance - - 15 - - 15 pF

Programmable Gain Characteristics

Gain Step Size - 1.0 - - 1.0 - dB

Absolute Gain Step Error - - TBD - - TBD dB

A/D Decimation Filter Characteristics (Note 2)

Passband (Note 3) 0 - 23.5 0 - 47.5 kHz

Passband Ripple -0.08 - +0.17 -0.09 - 0 dB

Stopband (Note 3) 27.5 - - 64.1 - - kHz

Stopband Attenuation (Note 4) -60.3 - - -48.4 - - dB

Group Delay (Fs = Output Sample Rate)(Note 5) t

Group Delay Variation vs. Frequency ∆t

High Pass Filter Characteristics

Frequency Response -3 dB (Note 2)

-0.1 dB

Phase Deviation @ 20 Hz (Note 2) - 10 - - 10 - Degree

Passband Ripple (Note 2) - - 0.17 - - 0.09 dB

*PGA : Programmable Gain Amplifier

- 10/Fs - - 2.7/Fs - s

- - 0.03 - - 0.007 µs

3.7

24.2

3.7

24.2

UnitMin Typ Max Min Typ Max

6 DS544PP1

CS42L50

ANALOG OUTPUT CHARACTERISTICS (T

GND = 0 V; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Single Speed Mode = 48 kHz, SCLK = 3.072 MHz. Fs for Double Speed Mode = 96 kHz, SCLK = 6.144 MHz. Test load R C

= 10 pF (see Figure 24) for headphone out.

Parameter

Line Output Dynamic Performance for VA = 1.8 V

Dynamic Range (Note 6)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 6)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V

Dynamic Range (Note 6)

18 to 24-Bit unweighted

A-Weighted

16-Bit unweighted

A-Weighted

Total Harmonic Distortion + Noise (Note 6)

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz) - 66 - - 66 - dB

=10kΩ, CL= 10 pF (see Figure 23) for line out, RL=16Ω,

Symbol Min Typ Max Min Typ Max Unit

THD+N

= 25° C; Logic "1" = VL = 1.8 V; Logic "0" =

Single Speed Mode Double Speed Mode

TBD TBD

91 94 89 92

-80

-71

-31

-78

-69

-29

88 91 86 89

-82

-68

-28

-80

-66

-26

TBD

TBD TBD

89 92 87 90

-80

-69

-29

-78

-67

-27

88 91 86 89

-85

-68

-28

-83

-66

-26

TBD

dB dB

Notes: 1. Referenced to typical full-scale input voltage.

2. Filter response is not tested but is guaranteed by design.

3. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the

0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs.

4. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...).

5. Group delay for Fs = 48 kHz, t

6. One-half LSB of triangular PDF dither is added to data.

DS544PP1 7

= 10/48 kHz = 208 µs.

CS42L50

ANALOG OUTPUT CHARACTERISTICS (Continued)

Single Speed Mode Double Speed Mode

Parameter

Line Output Dynamic Performance for VA = 3.0 V

Dynamic Range (Note 6) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted

Total Harmonic Distortion + Noise (Note 6) 18 to 24 Bit 0dB

-20dB

-60dB 16-Bit 0dB

-20dB

-60dB

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V

Dynamic Range (Note 6) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted

Total Harmonic Distortion + Noise (Note 6) 18 to 24 Bit 0dB

-20dB

-60dB 16-Bit 0dB

-20dB

-60dB

Interchannel Isolation (1 kHz) - 66 - - 66 - dB

Symbol Min Typ Max Min Typ Max Unit

TBD

dB dB dB

dB dB dB dB dB dB

dB dB dB dB

dB dB dB dB dB dB

THD+N

TBD TBD

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-76

-70

-30

-74

-68

-28

TBD

TBD TBD

93 96 91 94

-85

-73

-33

-83

-71

-31

90 93 88 91

-73

-70

-30

-71

-68

-28

8 DS544PP1

CS42L50

ANALOG OUTPUT CHARACTERISTICS (Continued)

Parameters Symbol Min Typ Max Units

Analog Output

Full Scale Line Output Voltage (Note 7) V Line Output Quiescent Voltage V Full Scale Headphone Output Voltage V Headphone Output Quiescent Voltage V

FS_LINE

Q_LINE

FS_HP

Q_HP

Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C Maximum Line Output AC-Current VA=1.8 V

LINE

VA= 3 . 0 V

Maximum Headphone Output VA=VA_HP=1.8 V

AC-Current VA=VA_HP=3.0 V

Single Speed Mode Double Speed Mode

Parameter

Combined Digital and On-chip Analog Filter Response (Note 8)

Passband (Note 9)

to -0.05 dB corner

to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz

(Note 10)

StopBand .5465 - - .577 - - Fs

StopBand Attenuation (Note 11) 50 - - 55 - - dB

Group Delay tgd - 9/Fs - - 4/Fs - s

Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz

De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Symbol Min Typ Max Min Typ Max Unit

-.02 - +.08 0 - +0.11 dB

--±0.36/Fs

TBD G x VA TBD Vpp

- 0.5 x VA_LINE - VDC

TBD 0.55 x VA TBD Vpp

- 0.5 x VA_HP - VDC

.4535

.4998

+.2/-.1

+.05/-.14

+0/-.22

0.1

0.15 31

0 0

--±1.39/Fs

±0.23/Fs--

(Note 12)

.4426 .4984

mA mA

Fs Fs Fs

s s

dB dB dB

Notes: 7. See Section 4.2.7 for details.

8. Filter response is not tested but is guaranteed by design.

9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 14 through 21) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

10. Referenced to a 1 kHz, full-scale sine wave.

11. For Single Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

12. De-emphasis is not available in Double Speed Mode.

DS544PP1 9

CS42L50

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to

ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current- VA=1.8 V Normal Operation VA_HP=1.8 V

VL=1.8 V

Power Supply Current- VA=3.0 V Normal Operation VA_HP=3.0 V

VL=3.0 V

Power Supply Current- All Supplies=1.8 V Power Down Mode (Note 13) All Supplies =3.0V

Total Power Dissipation- All Supplies=1.8 V Normal Operation All Supplies=3.0 V

Maximum Headphone Power Dissipation (1 kHz full-scale sine wave VA=1.8 V into 16 ohm load) VA=3.0 V

Package Thermal Resistance θ Power Supply Rejection Ratio (Note 14) (1 kHz)

(60 Hz)

A_HP

D_L

A_HP

D_L

PSRR -

13.3

1.5

154

1.5

270 150

350

27 65

15 26

TBD TBD

mA mA

µA

mA mA

µA µA

µA

mW mW

-55-°C/Watt 60

dB dB

Notes: 13. Power Down Mode is defined as RST

14. Valid with the recommended capacitor values on FILT+_ADC, FILT+_DAC, VQ_DAC, and VQ_ADC as shown in Figure 4. Increasing the capacitance will also increase the PSRR. Note that care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 µA will cause degradation in analog performance. A small ceramic capacitor in parallel with a larger electrolytic is recommended.

= LO with all clocks and data lines held static.

10 DS544PP1

CS42L50

DIGITAL CHARACTERISTICS (T

= 25° C; VL = 1.7 V - 3.3 V; GND = 0 V)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage

Low-Level Input Voltage Input Leakage Current I High-Level Output Voltage V Low-Level Output Voltage V

0.7 x VL - - V

- - 0.3 x VL V

--±10µA

0.7 x VL - - V

- - 0.3 x VL V Input Capacitance - 8 - pF Maximum MUTEC Drive Capability VA=1.8 V

VA= 3 . 0 V

TBD

mA MUTEC High-Level Output Voltage - VA - V MUTEC Low-Level Output Voltage - 0 - V

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supplies: Analog&Headphone

Digital I/O Input Current, Any Pin Except Supplies I Digital Input Voltage V Ambient Operating Temperature (power applied) T Storage Temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

VA&VA_HP

IND

stg

-0.3

4.0

V V

-±10mA

-0.3 VL+0.4 V

-55 125 °C

-65 150 °C

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

Ambient Temperature T DC Power Supplies: Analog&Headphone (Note 15)

VA&VA_HPVL1.7

Digital I/O

Notes: 15. VA and VA_HP should be tied to the same supply as shown in Figure 4.

-10 - 70 °C

1.7

3.6

V V

DS544PP1 11

CS42L50

SWITCHING CHARACTERISTICS (T

Logic 1 = VL, C

= 20 pF)

= -10 to 70° C; VA = 1.7 V - 3.3 V; Inputs: Logic 0 = GND,

Parameters Symbol Min Typ Max Units

Input Sample Rate Single Speed Mode

Double Speed Mode

Fs Fs

100

kHz kHz

MCLK Pulse Width High MCLK/LRCK = 1024 8 - - ns

MCLK Pulse Width Low MCLK/LRCK = 1024 8 - - ns

MCLK Pulse Width High MCLK/LRCK = 768 10 - - ns

MCLK Pulse Width Low MCLK/LRCK = 768 10 - - ns

MCLK Pulse Width High MCLK/LRCK = 512 15 - - ns

MCLK Pulse Width Low MCLK/LRCK = 512 15 - - ns

MCLK Pulse Width High MCLK / LRCK = 384 or 192 25 - - ns

MCLK Pulse Width Low MCLK / LRCK = 384 or 192 25 - - ns

MCLK Pulse Width High MCLK / LRCK = 256 or 128 35 - - ns

MCLK Pulse Width Low MCLK / LRCK = 256 or 128 35 - - ns

Master Mode

SCLK Falling to LRCK Edge t

SCLK Falling to SDOUT Valid t

slrd

sdo

-20 - 20 ns

0 - 20 ns

SCLK Duty Cycle 40 50 60 %

Slave Mode

LRCK Duty Cycle 40 50 60 %

Rise Time of Both LRCK and SCLK t

Fall Time of Both LRCK and SCLK t

SCLK Period (Note 16) Single Speed Mode

Double Speed Mode

sclkw

SCLK Falling to LRCK Edge t

SCLK Falling to SDOUT Valid Single Speed Mode

Double Speed Mode

slrd

dss

- - 10 ns

------------ ---------128()Fs

------------ ------

64()Fs

-20 - 20 ns

(512)Fs

(256)Fs

16. There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.

12 DS544PP1

CS42L50

SCLK

LRCK

SDIN

sclkh

sclkl

slrd

dss

MSB

Figure 1. SCLK to LRCK and SDIN, Slave Mode

sclkw

SCLK

slrd

LRCK

sdo

SDIN

MSB MSB-1

Figure 2. SCLK to LRCK and SDIN, Master Mode

DS544PP1 13

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25° C; VL = 1.7 V - 3.3 V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)

Parameter Symbol Min Max Unit

SCL Clock Frequency f

Rising Edge to Start t

RST

Bus Free Time Between Transmissions t

Start Condition Hold Time (prior to first clock pulse) t

Clock Low time t

Clock High Time t

Setup Time for Repeated Start Condition t

SDA Hold Time from SCL Falling (Note 17) t

SDA Setup time to SCL Rising t

Rise Time of SCL t

Fall Time of SCL t

Rise Time of SDA t

Fall Time of SDA t

Setup Time for Stop Condition t

scl

irs

buf

hdst

low

high

sust

hdd

sud

susp

CS42L50

-100KHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

0-µs

250 - ns

-25ns

-1µs

-300ns

4.7 - µs

Note: 17. Data must be held for sufficient time to bridge the transition time, t

RST

SDA

SCL

irs

Stop S ta rt

buf

hdd

high

sud

hdst

low

Figure 3. Control Port Timing - I2C

Repeated

Start

sust

hdst

, of SCL.

Stop

susp

14 DS544PP1

2. TYPICAL CONNECTION DIAGRAM

CS42L50

1.8 to 3.3 V Supply

1.0 µF 0.1 µF

150 Ω

0.47 µF

150 Ω

0.47 µF

150 Ω

0.47 µF

150 Ω

0.47 µF

Digital

Audio

Source

µc

Configuration

1.0 nF

0. 1 µ F

0. 1 µF

0. 1 µ F

0. 1 µF

1.0 nF

AIN_L1

AIN_R1

AIN_L2

AIN_R2

MCLK

SCLK

LRCK

SDOUT

SDIN

RST

SDA

SCL

AFLTL

AFLTR

0.1 µF 0.1 µF

13 21

VA_HPVA VL

CS42L50

VQ_DAC

FILT+_DAC

REF_GND

FILT+_ADC

VQ_ADC

GND

HP_A

HP_B

AOUTL

AOUTR

MUTEC

220 µF

3.3 µ F +

0.1 µF

C =

1.0 µF

RL + 560

4 π F

1 kΩ

10 kΩ

1.0 µF

(RL560)

4.7 µH

560 Ω

1.0 µF

0.1 µF

1.8 to 3.3 V Supply

Headphones

Mute

Circuit

1.0 µF

Ω

Figure 4. CS42L50 Typical Connection Diagram

DS544PP1 15

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