Cirrus Logic CDB4272 User Manual
Evaluation Board For CS4272
CDB4272
Features
Differential Analog Inputs
CS8406 S/PDIF digital audio transmitter
CS8416 S/PDIF digital audio receiver
Header for optional external configuration of
CS4272
Header for external DSP serial audio I/O
3.3V to 5.0V Logic Interface
Demonstrates recommended layout and
grounding arrangements
Microsoft Windows® compatible software
interface to configure CS4272 and interboard connections
ORDERING INFORMATION
CDB4272 Evaluation Board
I
Description
The CDB4272 demonstration board is an excellent
means for evaluating the CS4272 stereo CO DEC . Evaluation requires an analog/digital signal source and
analyzer, and power suppl ies. Optionally, a Windows
PC compatible com puter may be used to evaluate the
CS4272 in control port mode.
System timing can be provided by the CS4272, by the
CS8416 phase-locked to its S/PDIF input, by an I/O
stake header or by an on-board oscillator. RCA phono
jacks are provided for the CS4272 analog outputs . Balanced XLR jacks are provided for the CS4272 analog
inputs. Digital data I/O is available via RCA phono or optical connectors to the CS8416 and CS8406.
Microsoft Windows
configuration of the board easy. The software communicates through the PC’s parallel port to configure the
hardware so that all features of the CS4272 can be evaluated. The evaluation boa rd may also be configured to
accept external timing and data signals for operation in a
user application during system development.
®
software provides a GUI to make
®
Differential
Analog
Inputs
Differential to
Single-Ended
Analog
Outputs
Cirrus Logic, Inc.
www.cirrus.com
CS4272
Control Port
SDOUT
MCLK
LRCK
SCLK
SDIN
I/O
Header f or
Clocks &
Data
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
CS8406
S/PDIF
Transmitter
Oscillator
CS8416
S/PDIF
Receiver
S/PDIF
Output
S/PDIF
Input
SEPT ‘03
DS593DB2
1
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4
1.1 CS4272 Stereo Au dio CODEC .................... ................ .......... ................ .......... ................ ..4
1.2 CS8406 Digital Audio Transmitter ......................................................................................4
1.3 CS8416 Digital Audio Receiver ..........................................................................................4
1.4 Canned Oscillator ..............................................................................................................5
1.5 Analog Input .......................................................................................................................5
1.6 Analog Outpu ts ......................... ................ .......... ................ ................. ................ ..............5
1.7 Stand-Alone Control ...........................................................................................................7
1.8 PC Parallel Por t Control ................... ......... ................. ................ .......... ................ ..............7
1.9 External Control Headers ......................................................... .. .......... .. ....... ....... ..... ....... ..8
1.10 Power ................ .......... ................ ................. .......... ................ ................. ......... ................8
1.11 Grounding and Power Supply Decoupling .......................................................................8
2. INITIAL BOARD SETUP .........................................................................................................11
2.1 Power Supplies: ................................................................ ....... .. .......... ....... .. ....... ............11
2.2 Installing the Software: ..................................................................................................... 11
2.2.1 Verifying Board Operation: ..................................................................................12
3. CDB427X.EXE USER'S GUIDE .............................................................................................13
3.1 Main Window ................................................... .......... ....... .. ....... .......... ....... .. ....... ............13
3.2 Advanced Window .............................................................. ....... ............ ....... ....... .......... ..14
3.3 I²C Mode No Acknowledge Error ................... ....... ..... ....... .. ....... ..... ..... ....... .. ....... ..... .......14
4. BLOCK DIAGRAM .................................................................................................................15
5. SCHEMATICS AND LAYOUT ...............................................................................................16
6. APPENDIX ..............................................................................................................................29
CDB4272
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is sub-
ject t o change without notice and is pr ovided "AS I S" without warranty of any kind (express or implied). Customers are advised to obtain the latest versio n of
relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement
of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied
under any patents, mask work rights, copyrights, trademar ks, trade secrets or other i ntellect ual property rights. Cirrus owns the copyr ights assoc iated with the
information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated
circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes,
or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICAT IONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMI TS THE USE OF CI RRUS PRODUCTS I N CRI TI CAL APPLI CA TI ONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUT ORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
I2C is a regi stered t rademark of Philips Semiconductor. Purc hase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associ ate d Companie s
conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
Microsoft Windows is a registered trademark of Microsoft Corporation.
2
LIST OF FIGURES
Figure 1. Instr u men tation Amplifier Configuration............................ .......... ................ ................. .... 6
Figure 2. Main Win d ow....................... ................. ......... ................. ................. ................ .............. 13
Figure 3. Advanced Window......................................................................................................... 14
Figure 4. I²C Error Message..........................................................................................................14
Figure 5. Clock and Data Routi n g.............. ................. .......... ................ .......... ................ .......... ....15
Figure 6. Hierarchy, Schematic Sheet 1 . ...................................................................................... 16
Figure 7. CS4272, Schematic Sheet 2.................................... ....... ....... ....... ....... ....... ....... .......... ..17
Figure 8. Analog Input, Schematic Sheet 3...................................................................................18
Figure 9. Analog Output, Schematic Sheet 4................................................................................ 19
Figure 10. CS8416 S/PDIF Receiver, Schematic Sheet 5....................................... .. ....... .......... ..20
Figure 11. CS8406 S/PDIF Transmitter, Schematic Sheet 6........................................................ 21
Figure 12. Board Se tu p , Sch e matic Sheet 7.......... .......... ................ ................. ......... ................. ..22
Figure 13. PCM Header, Schematic Sheet 8.... ............................................................................23
Figure 14. Control Port, Schematic Sheet 9................................................. ....... ....... ....... ............24
Figure 15. Power, Schematic Sheet 10......................................................................................... 25
Figure 16 . Component Placement and Reference Designators.................................... ....... .......26
Figure 17 . Top Layer....................... ......... ................. ................. ................ .......... .......................27
Figure 18 . Bottom Layer................ ......... ................. ................ ................. ......... ................. .........28
Figure 19 . Complete Analog Input Buffer Schematic........................................................... .......29
CDB4272
LIST OF TABLES
Table 1. System Connec tions............. .......... ................ ................. ......... ................. ................. ...... 9
Table 2. Jumper/ Switch Settings......... ................. ......... ................. ................. ......... ................. .... 10
3
CDB4272
1. SYSTEM OVERVIEW
The CDB4272 demonstration board is an excellent means for evaluating the CS4272 stereo
CODEC. Analog and digital audio signal interfaces are provided, as well as a DB-25 computer
parallel port interface for use with the supplied Window® configuration software.
The CDB4272 schematic set has been partitioned into 10 pages and is shown in Figures 6
through 15.
1.1 CS4272 Stereo Audio CODEC
A complete description of the CS4272 is included in the CS4272 product data sheet.
1.2 CS8406 Digital Audio Transmitter
The operation o f the CS840 6 transmitter (see Figur e 11) and a d iscussion of t he digital a udio
interface are included in the CS8406 data sheet.
The CS8406 converts the PCM data generated by the CS4272 to the standard S/PDIF data
stream. The CDB4272 is able to operate the CS8406 in either master or slave mode. The
serial audio i nput da ta for th e CS840 6 is received fro m the se rial audio output of the CS4272.
Using the GUI, the user may elect to supply the CS8406 with an external serial audio data
source through a sta k e he ader (J17). Digital Inter face fo rma t sel ection of e ither Left Ju sti fied
or I2S can be made via the control port GUI or via the I2S/LJ position on switch, S1
(see Table 2 for switch control options).
1.3 CS8416 Digital Audio Receiver
The operation of the CS8416 receiver (see Figure 10) and a discussion of the digital audio
interface are included in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream into PCM data for the CS4272. The
CDB4272 is able to oper ate the CS8 416 in master or slave mo de. Digital I nterface for mat selection of either Left Justified or I2S can be made via the I2S/LJ position on S1. Left Justi fied,
I2S or Right Justified interface formats can be selected via the control port GUI.
The CS8416 always sour ces an MCLK signal. As a result, it should be noted that the CS8416
will provide invalid data in modes where the MCLK signal is generated by the CS4272 or received through the stake header (J26). Care should be taken to ensure that the crystal (Y2)
is removed when the board is configured to receive MCLK from the CS8416.
The CS8416 cont ains an internal input multi plexer whic h must be se t to receive the ap propriate stream from the Optical or Coaxial input connector. This may be done via the
Coaxial/Optical position on S1, or through the control port GUI.
4
CDB4272
-- -
1.4 Canned Oscillator
Oscillator Y1 provides a System Clock (OMCK) to the CS8416. This clock can be routed
through the CS8416 and out the RMCK pin by simply disconnecti ng the S/PDIF input. To use
the canned oscillat or as the sou rce of the MCLK si gnal, configur e the boar d to recei ve MCLK
from the CS8416 using either the MCLK[1:0] positions on S1 or the GUI, and remove the
input S/PDIF stream. Care should be taken to ensure that the crystal (Y2) is removed when
the board is configured to receive MCLK from the canned oscillator.
The oscillator is mou nted in pin sockets, allowing easy rem oval or replaceme nt. The board is
shipped with a 12.000 MHz crystal oscillator stuffed at Y1. Please refer to the CS8416 data
sheet for details on OMCK operation.
1.5 Analog Input
XLR connectors sup ply the CS4272 ana log inputs t hrough u nity ga in, AC-co upled differ ential
circuits. A 2 Vrms differential signal will drive the CS4272 inputs to full scale.
The CDB4272 was designed for use with not only the CS4272, but also the CS421 with a
simple change of assembly options. For this reason, the input buffer schematic shown in
Figure 8 reflects only the configuration assembled on the CDB4272. For a complete schematic of the analog input buffer printed on the PCB, refer to Figure 19
1.6 Analog Outputs
The CS4272 analog output is routed through a differential to single-ended, unity-gain low
pass filter, which is AC-couple d to an RCA phono jack (see Figure 9). The analog output filter
on the CDB4272 has been de signed to add fl exib ility whe n evalua ti ng the CS427 2 DAC ou tputs. The output filter was designed in a two stage format, with the first stage being an optional instrumentation amplifier, and the second stage a 2-pole butterworth low pass filter.
The 2-pole low pass filter provides an example of an inexpensive circuit with good distortion
and dynamic rang e per form ance. It is desi gned to have the in- band i mpedance matched between the positiv e and neg ative le gs. I t also pro v ides a ba lanced to si n gle-e nded conver sion
for standard un -balan ced outpu ts. Evalua te this circu it by placing the FILT jumpers (thre e per
output channel) to position 1 (selectable by J13, J14 & J15 for AOUTR, etc.).
The instrumentation amplifier is optionally inserted before the LPF by changing the FILT
jumpers to position 2. The instrumentation amplifier incorporates a 5x gain (+14 dB) which
effectively lowers the noise contributio n of the following 2-p ole LPF. This impr oves the overall
dynamic range of the system. The gain of this stage is determined from the
following equation:
Gain 1
2R()
+=
--------R
2
5
CDB4272
The resistor designated by R2 (see Figure 1) can be adjusted to change the gain of the instrumentation amp. The feedback resistors ‘R’ on the two sides of the instrumentation amp
must be equal.
In+
In-
Figure 1. Instrumentation Amplifier Configuration
+
-
R
R
2
R
+
Out+
Out-
A resistor divider pad (parall el combination of R5 // R8 // R10 and R22 for AOUTR) has been
placed after the low pass filter to bring the circuit back to unity gain (selectable with jumper
J15 for AOUTR).
In the resistor divider pad, three 3.92 kΩ, 1/4 W, 1210 size resistors are used in parallel to
provide a combined resistan ce of 1.30 kΩ and a combined power handling of 3/4W. This is
done to provide sufficient power handling capability to accommodate the high signal levels
output from the instru menta tion am pl ifier stage. When not usi ng the instru menta ti on am plifi er, these resi stors may be reduced to a single 1.30 kΩ, 1/10 W, 0805 size resistor (for muting
attenuation purposes).
In certain places throughout the output circuit, 1/8 W, 1206 size and 1/4 W, 1210 size resistors are used. Similar to the parallel resistors in the resistor divider pad, these are used to
provide sufficient power handling capability in order to accommodate the high signal levels
output from the instru menta tion am pl ifier stage. When not usi ng the instru menta ti on am plifi er, these resistors may all be replaced with 1/10 W, 0805 size resistors.
The attenuat ion pr ovi ded by t he ou tput mute tra nsistor (Q2 for AOUTR ) is determined by the
resistor-div ider formed between the collector-emi tter on-resistance and the output resistance
of the LPF (R5 // R8 // R10 for AOUTR). The greater the output resistance, the greater the
attenuation will be for a given transistor. The trade off is that a high output impedance is not
usually desirable, and may affect the voltage transfer to the next stage based upon its input
impedance.
The same resistance that affects the transistor mute level also affects the HPF formed with
the output DC-block capacitor (C26 for AOUTR). For LPF configuration 2, the values for the
DC-block capacitor and output resistor pad (R5 // R8 // R10 and R22 for AOUTR) were chosen to minimize the rise in distortion performance at low frequency due to the electrolytic's
6
CDB4272
dielectric absorpti on prop erties. The H PF form ed by th i s R-C pai r must b e such th at the voltage across the alum inum ele ctrol ytic DC -b lock capacito r is mi nim al at 20 Hz. This keeps the
distortion due t o the electr ol ytic's di electric absorption prop erti es to a minim um. For a design
utilizing only LPF configuration 1, there is no post-LPF resistor-divider pad, and a much
smaller value capacitor can be used (22 µF).
Similar to the output DC-block capacitor described above, the value of the AC coupling
capacitor from the non-inverti ng input of the 2 -pole l ow pass to ground ( C23 for A OUTR) was
also chosen to minimize the rise in distortion performance at low frequency due to the electrolytic's dielectric absorption properties. These properties become apparent only as the
signal level on that leg increases to the levels output from the differential amp used in LPF
configuration 2. For a design utilizing only LPF configuration 1, the levels on that leg are sufficiently low, and a much smaller value capacitor can be used (22 µF).
1.7 Stand-Alone Control
Switch S1 allows stand-alone hardware signal routing and configuration of the CDB4272.
See Table 2 for a list of the various options available. After changing settings using S1, the
user must assert a reset by pressing the RESET button (S2).
Operation in stand-alone mode requires the parallel port cable to remain disconnected from
the DB-25 connector (J31). Connecting a cable to the connector will enable the PC control
port, automatically disabling switch S1 and its associated logic.
1.8 PC Parallel Port Control
A graphical user interf ace is included w ith the CD B4272 to all ow easy ma nipulation of all registers of the CS4 272 a nd ha rdw are configuration of t he CDB 4272. Conne cti ng a ca ble to the
DB-25 connecto r ( J31) will e nabl e the PC con trol p ort, autom ati cally disab lin g switch S 1 and
its associated logic.
7
CDB4272
1.9 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the
headers J26, J32, J17, and J24.
The 10-pin header, J26, all ows the user bidirectional a ccess to MCLK, S CLK, and LRCK . The
direction of these signal s is set using S1 (see T able 2 for switch control options) or the control
port GUI. Also accessible from this header is a buffered version of the SDOUT signal from
the CS4272, and a buffered input which, using S1 or the GUI, can be conf ig ured to drive the
CS4272 SDIN pin. Care should be taken to ensure that the crystal (Y2) is rem oved when the
board is configured to receive MCLK from this header.
The 2-pin header, J17, allows the user to supply the CS8406 with an external data source.
This option is available through the control port GUI and may be asserted by setting the
CS8406 data source to “Header”.
The 2-pin header, J24, supplies the user w ith a buffered version of the SDOUT signal generated by the CS8416. Th is may be used, for instan ce, to route r eceived S/PDIF data off -board
for processing before introducing it at the SDIN position on J26.
The 6-pin h eader, J32, allows the user b idirectional acce ss to the SPI/I2C control signal s. The
signals on J32 default t o outputs. W hen a jumpe r is place d across J34, th e header (J 32) may
be used as an input. When set as an input, the control signals on J32 are routed to the corresponding control pins on the CS4272 and external control signals may be applied.
1.10 Power
Power must be supplied to the evaluation board through at least three binding posts, +5.0 V
(J1), +18.0 V (J6), and -18.0 V (J7). Jumper J10 allows the user to connect th e VA supply of
the CS4272 to a fixed +5.0 V supply or to another separate binding post (J5). Jumpers J8
and J9 connect the VL and VD supply, respectively, to a fixed +5.0 V or +3.3 V supply or to
two separate binding posts (J2 and J3) for variable voltage settings. All voltage inputs must
be referenced to the single black banana-type ground connector (see Figure 15).
It should be noted that devices other than the CS4272 are powered from the VL supply and
therefore VL must be limited to a minimum of 3.3 V.
WARNING:Please refer to the CS4272 data sheet for allowable voltage levels.
1.11 Grounding and Power Supply Decoupling
The CS4272 requi res car eful att enti on to power sup ply and groundi n g arr angem ents to optimize performance. Figure 5 provides an overview of the connections to the CS4272,
Figure 16 shows the component placement, Figure 17 shows the top layout, and Figure 18
shows the bottom layout. The decoupling capacitors are located as close to the CS4272 as
possible. Extensive use of ground plane fill in the evaluation board yields large reductions in
radiated noise.
8
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
+5V - J1 Input +5.0 V Power Supp ly
-18V - J7 Input -18.0 V to -5.0 V Power Supply for the op-amps
+18V - J6 Input +5.0 V to +1 8.0 V Powe r Supply for the op-amps
VA - J5 Input +5.0 V Power Supp ly for VA
VD - J3 Input +3.3 V to +5.0 V Variable Power Supply for VD
VL - J2 Input +3.3 V to +5.0 V Variable Power Supply for VL
GND - J4 I nput Ground Reference
RX-COAX - J25 Input Digital audio input via coaxial cable
RX-OPT - OPT1 Input Digital audio input via optical cable
TX-COAX - J12 Output CS8406 digital audio output via coaxial cable
TX-OPT - J18 Output CS8406 digital audio output via optical cable
PC Port - J31 Input/Output
PCM HEADER - J26 Input/Output I/O for Clocks & Data
8416 SDOUT - J24 Output CS8416 serial data output (SDOUT)
8406 SDIN - J17 Input External data source for CS8406 SDIN
EXT CTRL I/O Input/Output
AINL - J33
AINR - J30
AOUTL - J23
AOUTR - J16
Input XL R jacks for differential analog input signal to CS4272
Output RCA phono jacks for analog outputs
Parallel connection to PC for SPI / I
tem configuration
2
I/O for extern al SPI / I
header in/out selection (J34)
C control port signals (J32) and control signal
2
C control port signals and sys-
CDB4272
T able 1. System Connections
9
Loading...