Cirrus Logic CDB4270 User Manual

Evaluation Board for CS4270

CDB4270

Features

 Single-Ended Analog Audio Inputs and Outputs

 CS8416 S/PDIF Digital Audio Receiver

 Header for External Configuration of CS4270

 Header for External DSP Serial Audio I/O

 3.3V Logic Interfaces

 Pre-Defined Software Scripts

 Demonstrates Recommended Layout

 Windows

Configuration and Control

®

-Compatible GUI Interface for Board

Description

Using the CDB4270 is an excellent way to evaluate the
CS4270 CODEC. Other equipment required includes
analog/digital audio sources/analyzer, a 5V power sup­ply and a Windows-compatible

PC for the GUI.
System timing for the I²S, Left-Justified or Right-Justi-

fied audio data formats can be provided by the CS4270,
by the CS8416, or by a device connected to the on­board DSP I/O header. The evaluation board may also
be configured to accept external timing and data signals
for operation in a user application during system
development.

RCA jacks are provided for the analog audio inputs and
outputs. Digital S/PDIF transmit or receive data I/O is
available via either RCA jacks or optical connectors.

The Windows GUI software provided allows for easy
configuration of the CDB4270. The GUI software com­municates with the board via USB or serial port
connections to configure the CS4270 registers.

ORDERING INFORMATION

CDB4270 Evaluation Board

CS8406

S/PDIF
Output

CS8416

S/PDIF

Input

Osc.

http://www.cirrus.com

Hardware

Setup

Clocks/Data

MCLK BUS

Hardware

Setup

Clocks

/Data

DSP HEADER

FPGA

ADC/DAC Clocks & Data

Serial/USB Control Port

I2C/SPI Header

ADC/DAC

Clocks/

Data

Hardware

Setup

Copyright © Cirrus Logic, Inc. 2006

CS4270

HW Setup

Switches

(All Rights Reserved)

ANALOG INPUT

Single-Ended Input

ANALOG OUTPUT

Single-Ended
Output

SEPTEMBER '06

DS686DB3

TABLE OF CONTENTS

1. SYSTEM OVERVIEW ............................................................................................................................. 5

1.1 Power ............................................................................................................................................... 5

1.2 Grounding and Power Supply Decoupling ...................... ... .... ... ... ... ... .... ........................................... 5

1.3 FPGA ................................................................................................................................................ 5

1.4 CS4270 Audio CODEC .................................................................................................................... 5

1.5 CS8406 Digital Audio Transmitter ............... ... ... ... .... .......................................... ... ... ........................ 5

1.6 CS8416 Digital Audio Receiver ...................... ... ... .... ... ... ... .... ......................................... .... .............. 5

1.7 Canned Oscillator ............................................................................................................................. 6

1.8 External Control Headers ................................................................................................................. 6

1.9 Analog Input ..................................................................................................................................... 6

1.10 Analog Outputs ............................................................................................................................... 8

1.11 Control Port .................................................................................................................................... 8

1.12 Hardware Mode Switches ............................................................................................................... 8

2. FPGA OVERVIEW .................................................................................................................................. 9

2.1 FPGA Architecture ............................................................................................................................ 9

2.2 Internal Sub-Clock Routing ............................................................................................................... 9

2.3 Internal Data Routing ...................................................................................................................... 10

2.4 Internal Drivers ............................................................................................................................... 11

2.5 External MCLK Control ................................................................................................................... 12

3. SOFTWARE MODE .............................................................................................................................. 13

3.1 CDB4270 Control Scripts ............................................................................................................... 13

3.1.1 S/PDIF In, Analog Out ........................................................................................................... 13

3.1.2 Analog In, S/PDIF Out .............................. ... .... ... ... ....................................... ... ... ... .... ... ......... 13

3.1.3 Analog In, Analog Out (Digital Loop-Back) ............................ ... .... ... ... ... .... ............................ 13

3.1.4 DSP In, Analog Out ............................................................................................................... 13

3.2 CDB4270 GUI ................................................................................................................................. 14

3.3 Register Maps Control Tabs ........................................................................................................... 15

4. HARDWARE MODE ............................................................................................................................. 18

5. FPGA GUI REGISTER DESCRIPTION ................................................................................................ 18

5.1 FPGA REGISTER QUICK REFERENCE ....................................................................................... 18

5.2.1 Revision Number Bits (Bits 7:0) ............................................... .... ......................................... 19

5.3.1 SDOUT Routing to Header (Bits 7:6) .................................................................................... 20

5.3.2 MCLK Source (Bit 4) .......................................... ... ... ....................................... ... ... .... ... ......... 20

5.3.3 SDOUT Routing to DUT (Bits 3:2) ......................................................................................... 20

5.3.4 Subclock Routing (Bits 1:0) ... ... ... ... .... ... ... ... .... ... ... ... .... ......................................... .... ... ......... 21

5.4.1 CS8406 OMCLK Divider Control (Bits 7:6) ........................................................................... 21

5.4.2 CS8406 Master/Slave Select (Bit 4) ...................................................................................... 22

5.4.3 CS8406 SDIN Format Select (Bit 3) ...................................................................................... 22

5.4.4 CS8406 SDIN Source (Bits 1:0) ......................... ................................................................ ...22

5.5.1 CS8416 RMCLK Divider Control (Bit 6) ................................................................................ 23

5.5.2 CS8416 Master/Slave Select (Bit 4) ...................................................................................... 23

5.5.3 CS8416 SDOUT Format Select (Bit 3) .................................................................................. 23

6. CDB4270 HARDWARE MODE SETTINGS ......................................................................................... 24

7. CDB CONNECTORS, SWITCHES, INDICATORS AND JUMPERS ................................................... 26

8. ADC PERFORMANCE PLOTS ............... ... ... .... ... ... ... .......................................... .... ... ......................... 27

9. DAC PERFORMANCE PLOTS ............... ... ... .... ... ... ... .......................................... .... ... ......................... 31

10. CDB BLOCK DIAGRAM ................................................................................................................ 36

11. CDB SCHEMATICS ............................................................................................................................ 37

12. CDB LAYOUT ..................................................................................................................................... 46

13. CHANGES MADE TO REV. B BOARD ............................................................................................. 49

13.1 Modifications (Done by Cirrus Logic) .......................................................................................... 49

14. REVISION HISTORY .......................................................................................................................... 50

CDB4270

2 DS686DB3

LIST OF FIGURES

Figure 1.ADC THD+N ................................................................................................................................. 7

Figure 2.ADC Dynamic Range .................................................................................................................... 7

Figure 3.Internal Sub-Clock Routing ........................................................................................................... 9

Figure 4.Internal Data Routing .................................................................................................................. 10

Figure 5.Internal Drivers ............................................................................................................................ 11

Figure 6.External MCLK Control ............................................................................................................... 12

Figure 7.CDB4270 Controls Tab ............................................................................................................... 14

Figure 8.Register Maps Tab - CS4270 ..................................................................................................... 15

Figure 9.Register Maps Tab - Board Configuration .................................................................................. 16

Figure 10.Register Maps Tab - GPIO ....................................................................................................... 17

Figure 11.FFT (-1 dB 48 kHz) ................................................................................................................... 27

Figure 12.FFT (-60 dB, 48 kHz) ................................................................................................................ 27

Figure 13.FFT (48 kHz, No Input) ............................................................................................................. 27

Figure 14.48 kHz, THD+N vs. Input Freq .................................................................................................. 27

Figure 15.48 kHz, THD+N vs. Level ......................................................................................................... 27

Figure 16.48 kHz, Fade-to-Noise Linearity ............................................................................................... 27

Figure 17.48 kHz, Frequency Response ................................................................................................... 28

Figure 18.48 kHz, Crosstalk ...................................................................................................................... 28

Figure 19.FFT (-1 dB 96 kHz) ................................................................................................................... 28

Figure 20.FFT (-60 dB, 96 kHz) ................................................................................................................ 28

Figure 21.FFT (96 kHz, No Input) ............................................................................................................. 28

Figure 22.96 kHz, THD+N vs. Input Freq .................................................................................................. 28

Figure 23.96 kHz, THD+N vs. Level ......................................................................................................... 29

Figure 24.96 kHz, Fade-to-Noise Linearity ............................................................................................... 29

Figure 25.96 kHz, Frequency Response ................................................................................................... 29

Figure 26.96 kHz, Crosstalk ...................................................................................................................... 29

Figure 27.FFT (-1 dB 192 kHz) ................................................................................................................. 29

Figure 28.FFT (192 kHz, -60 dB) .............................................................................................................. 29

Figure 29.FFT (192 kHz, No Input) ........................................................................................................... 30

Figure 30.192 kHz, THD+N vs. Input Freq ................................................................................................ 30

Figure 31.192 kHz, THD+N vs. Level ....................................................................................................... 30

Figure 32.192 kHz, Fade-to-Noise Linearity ............................................................................................. 30

Figure 33.192 kHz, Frequency Response ................................................................................................. 30

Figure 34.192 kHz, Crosstalk .................................................................................................................... 30

Figure 35.FFT (48 kHz, 0 dB) ................................................................................................................... 31

Figure 36.FFT (48 kHz, -60 dB) ................................................................................................................ 31

Figure 37.FFT (48 kHz, No Input) ............................................................................................................. 31

Figure 38.FFT (48 kHz Out-of-Band, No Input) ......................... ... .... ... ... ... ... .... ... ... ... .... ... ......................... 31

Figure 39.48 kHz, THD+N vs. Input Freq .................................................................................................. 31

Figure 40.48 kHz, THD+N vs. Level ......................................................................................................... 31

Figure 41.48 kHz, Fade-to-Noise Linearity ............................................................................................... 32

Figure 42.48 kHz, Frequency Response ................................................................................................... 32

Figure 43.48 kHz, Crosstalk ...................................................................................................................... 32

Figure 44.48 kHz, Impulse Response ....................................................................................................... 32

Figure 45.FFT (96 kHz, 0 dB) ................................................................................................................... 32

Figure 46.FFT (96 kHz, -60 dB) ................................................................................................................ 32

Figure 47.FFT (96 kHz, No Input) ..............................................................................................

Figure 48.FFT (96 kHz Out-of-Band, No Input) ......................... ... .... ... ... ... ... .... ... ... ... .... ... ......................... 33

Figure 49.96 kHz, THD+N vs. Input Freq .................................................................................................. 33

Figure 50.96 kHz, THD+N vs. Level ......................................................................................................... 33

Figure 51.96 kHz, Fade-to-Noise Linearity ............................................................................................... 33

Figure 52.96 kHz, Frequency Response ................................................................................................... 33

CDB4270

............... 33

DS686DB3 3

CDB4270

Figure 53.96 kHz, Crosstalk .. .... ... ... ... .... ... ................................................................................................ 34

Figure 54.96 kHz, Impulse Response ................................. ...................................................................... 34

Figure 55.FFT (192 kHz, 0 dB) ................................................................................................................. 34

Figure 56.FFT (192 kHz, -60 dB) .............................................................................................................. 34

Figure 57.FFT (192 kHz, No Input) ........................................................................................................... 34

Figure 58.FFT (192 kHz Out-of-Band, No Input) ....................................................................................... 34

Figure 59.192 kHz, THD+N vs. Input Freq ................................................................................................ 35

Figure 60.192 kHz, THD+N vs. Level ....................................................................................................... 35

Figure 61.192 kHz, Fade-to-Noise Linearity ............................................................................................. 35

Figure 62.192 kHz, Frequency Response ................. .......... ......... .......... .......... ......... .......... .......... ............ 35

Figure 63.192 kHz, Crosstalk .................................................................................................................... 35

Figure 64.192 kHz, Impulse Response ..................................................................................................... 35

Figure 65.Block Diagram ........................................................................................................................... 36

Figure 66.CS4270 .... .... ... ... ... .... ... ... ... .......................................... .... ... ...................................................... 37

Figure 67.Analog Input .... ... ... .......................................... .... ... .......................................... ... ...................... 38

Figure 68.Analog Output ....... .... ... ... ... .......................................... .... ... ...................................................... 39

Figure 69.CS8406 S/PDIF Transmitter ..................................................................................................... 40

Figure 70.CS8416 S/PDIF Receiver ............... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ................................... 41

Figure 71.Buffers - Clock/Data Routing .................................................................................................... 42

Figure 72.FPGA ........................ ... ... ... .... ... ... ... .......................................................................................... 43

Figure 73.USB/RS232 Microprocessor .................................................................................. ... .... ............ 44

Figure 74.Power . ....................................................................................................................................... 45

Figure 75.Silk Screen ... .......................................... ... ... ... .... ... ... ... ............................................................. 46

Figure 76.Top-Side Layer ...................................................... ... ... .... ... ... ... ................................................ 47

Figure 77.Bottom-Side Layer .......................... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 48

LIST OF TABLES

Table 1. Revision Number ......................................................................................................................... 19

Table 2. SDOUT Routing to Header ......................................................................................................... 20

Table 3. MCLK Source .............................................................................................................................. 20

Table 4. SDOUT Routing to DUT .............................................................................................................. 20

Table 5. Sub-Clock Routing ...................................................................................................................... 21

Table 6. CS8406 OMCLK Frequency ....................................................................................................... 21

Table 7. CS8406 Master/Slave ................................................................................................................. 22

Table 8. CS8406 SDIN Format ................................................................................................................. 22

Table 9. CS8406 SDIN Source ................................................................................................................. 22

Table 10. CS8416 RMCLK Frequency ...................................................................................................... 23

Table 11. CS8416 Master/Slave ............................................................................................................... 23

Table 12. CS8416 SDOUT Format ........................................................................................................... 23

Table 13. CDB4270 Hardware Mode - Functional Description ................................................................. 24

Table 14. Connectors and Switches ......................................................................................................... 26

Table 15. Jumpers and Indicators ............................................................................................................. 26

4 DS686DB3

CDB4270

1. SYSTEM OVERVIEW

The CDB4270 evaluation board is an excellent tool for evaluating the CS4270 CODEC. The board features both
analog and digital audio interfaces along with an FPGA for data/clk routing and an on-board microprocessor for con­figuration control. The board is easily configured in Software Mode using the supplied PC-to-DUT USB cable along
with the Windows-based GUI configuration software or in Hardware Mode using the on-board dip switches.

The CDB4270 schematic set has been partitioned into nine pages and is shown in Figures 66 through 74.

1.1 Power

Power must be supplied to the evaluation board through the +5.0 V binding posts. The +5 V inputs must be
referenced to the single black binding post ground connector (Figure 74 on page 45).

WARNING: Please refer to the CS4270 data sheet for allowable voltage levels.

1.2 Grounding and Power Supply Decoupling

To optimize performance, PC board designs for the CS4270 require careful attention to power supply,
grounding and signal routing arrangements. Figure 65 on page 36 shows the basic compon ent/signal inter­connect for the CDB4270. Figure 75 on page 46 shows the component placement. Figure 76 on page 47
shows the top layout. Figure 77 on page 48 shows the botto m layout. The decoupling capacitors are loca ted
as close to the CS4270 as possible. Extensive use of ground plane fill in the evaluation board yields large
reductions in radiated noise.

1.3 FPGA

See “F PGA Overview” on page 9 for a complete description of the FPGA (Figure 72 on page 43) that is used
on the CDB4270.

1.4 CS4270 Audio CODEC

A complete description of the CS4270 (Figure 66 on page 37) is included in the CS4270 product data sheet.
The CS4270 codec performs stereo 24-bit A/D and D/A conversion at sample rates of up to 216 KHz. The

part accommodates I²S, Left-Justifie d an d Rig ht -Ju st if ied ser ial au dio for m ats .

1.5 CS8406 Digital Audio Transmitter

A complete description of the CS8406 transmitter ( Figure 69 on page 40 ) and a discussion of the d igital au­dio interface are included in the CS8406 data sheet.

The CS8406 converts the PCM data from either the CS4 270, the DSP Header, or the CS8416 to a standard
S/PDIF data stream. The CS8406 operates in either master or slave sub-clock mode and will accept either
a 128 Fs, 256 Fs, or 512 Fs master clock on the OMCK input pin. The device will operate in either the Left­Justified or I²S interface data modes.

1.6 CS8416 Digital Audio Receiver

A complete description of the CS8416 receiver (Figure 70 on page 41) and a discussion of the digital audio
interface are included in the CS8416 data sheet.

The CS8416 converts the input S/PDIF data stream into PCM data that can be used by the CS4270 and
CS8406. The device operates in either Master or Slave su b-clo ck modes and gen er ates eith er a 128 Fs or
256 Fs master clock for output on the RMCK pin. Either Left-Justified or I²S interface output data formats
can be selected

DS686DB3 5

1.7 Canned Oscillator

Oscillator Y1 provides a system master clock. This clock is routed through the CS8416 and out of the RMCK
pin when the S/PDIF input is disconnected (refer to the CS8416 data sheet for details on OMCK opera tion).
To use the canned oscillator as the source of the MCLK signal, remove the S/PDIF input to the CS8416 and
configure the CS8416 appropriately.

The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with
a 12.288 MHz crystal oscillator populated at Y1.

1.8 External Control Headers

The evaluation board has been designed to allow interfacing with external systems via the J10 and J9 head­ers.

The 10-pin, 2-row header, J9, allows access to the serial audio signa ls required to interface with a DSP (see

Figure 71 on page 42).

The 18-pin, 3-row header, J10, allows the user bidirectional acce ss to the SPI
ply removing all of the shunt jumpers from the “NORMAL” position. The user may then choose to connect
a ribbon cable to the “EXTERNAL” position. A single “GND” row for the ribbon cable’s ground connection is
provided to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user
choose to use the CDB for the I²C power rail.

CDB4270

TM

/I²C® control signals by sim-

1.9 Analog Input

RCA connectors supply the CS4270 analog inputs through passive, AC-coupled, single-ended circuits. A
2 Vrms single-ended signal into the RCA connectors will drive the CS4270 inputs to full scale (1 Vrms). The
input network on the CDB4270 was designed to demonstrate that the CS4270 will provide superior perfor­mance with up to 2.5 kΩ driving impedances (looking back from the CS4270 inputs) while allowing for
2 Vrms inputs. ADC performance varies depending upon the input impedance of the input network.

Figures 1 and 2 show typical THD+N and Dynamic Range performance for the ADC as a function of input

impedance.

6 DS686DB3

CDB4270

Figure 1. ADC THD+N

Figure 2. ADC Dynamic Range

DS686DB3 7

1.10 Analog Outputs

The CS4270 analog outputs are AC-coupled and routed through a single-pole RC Low-Pass filter.

1.11 Control Port

A graphical user interface is included with the CDB 4270 to allow easy manipu lation of the registers in th e
CS4270 (see the CS4270 data sheet for register descriptions and the “FPGA GUI Regi ster Descr iption” on

page 18). The GUI will run on a standard Windows-based PC. Connecting a USB cable from a PC to J15

or an RS-232 cable to J16 and launching the Cirrus Logic FlexGUI software enab les control and configur a­tion of the board.

Refer to “Software Mode” on page 13 for a description of the Graphical User Interface (GUI).

1.12 Hardware Mode Switches

The “HW Mode Config” and ”Clk/Data Config” switches control all Hardware Mode options. “Hardware

Mode” on page 18 provides a description of each topology.

CDB4270

8 DS686DB3

CDB4270

2. FPGA OVERVIEW

The FPGA (U11) controls all digital signal routing between the CS4270, CS8406, CS8416 and the DSP I/O Header.
The device also generates all of the clock/data driver output enables and S/PDIF device mode controls. The FPGA
internal registers can be configured either via the I² C (Software Mode) or via external dip switches (Hardware Mode).
When using the CS4270 in Hardware Mode, the FPGA decodes some of these dip-switch settings and generates
the CS4270 control signals. In addition, the FPGA distributes resets from the micro for all of the devices on the
board.

2.1 FPGA Architecture

Figures 3 through 5 show the internal architect ure of the FPG A. Figure 6 shows the MCLK routing to/from

the FPGA and the other devices on the board. The FPGA has an I²C interface and interna l registers for soft­ware control and can also read external dip-switch settings for hardware control. Refer to the FPGA GUI

Register Description section of this document for a description of the FPGA registers.

2.2 Internal Sub-Clock Routing

Figure 3 shows the internal sub-clock (SCLK, LRCK) routing topology between the CS4270, CS8416,

CS8406 and DSP Header. Refer to the FPGA GUI R egister Description section of this document for a
description of the sub-clock routing register settings.

.

FPGA

CS4270

LRCK
SCLK

CS8416-FPGA-LRCK

HDR-LRCK

FPGA-CS8406-LRCK

SUB_CK[1:0]

FPGA- DUT-LRCK

SUB_CK[1:0]

CS8416-FPGA-SCLK

HDR-SCLK

FPGA-CS8406-SCLK

FPGA-DUT-SCLK

CS8416

LRCK
SCLK

DSP Header

LRCK
SCLK

SUBCLK.FROM.HDR

SUBCLK.FROM.HDR

SUB_CK[1:0]

CS8416-FPGA-SCLK

HDR-SCLK

FPGA-DUT-SCLK

FPGA-CS8406-SCLK

SUB_CK[1:0]

FPGA-DUT-SCLK

HDR-SCLK

FPGA-CS8406-SCLK

SUB_CK[1:0]

CS8416-FPGA-SCLK

FPGA-DUT-SCLK

FPGA-CS8406-SCLK

SUBCLK.TO.HDR

SUBCLK.TO.HDR

CS8416-FPGA-LRCK

HDR-LRCK

FPGA-DUT-LRCK

FPGA-CS8406- LRCK

SUB_CK[1:0]

CS8416-FPGA-SCLK

SUB_CK[1:0]

HDR-SCLK

Figure 3. Internal Sub-Clock Routing

SUB_CK[1:0]

FPGA-DUT-LRCK

HDR-LRCK

FPGA-CS8406-LRCK

CS8416-FPGA- LRCK

CS8416-FPGA-LRCK

FPGA-DUT-LRCK

FPGA-CS8406-LRCK

HDR-LRCK

CS8406

LRCK
SCLK

DS686DB3 9

2.3 Internal Data Routing

Figure 4 shows the internal data routing topology between the CS4270, CS8416, CS8406 and the DSP

Header. Refer to the FPGA GUI Register Description section of this document for a description of the audio
data routing register settings.

.

CDB4270

CS8416

SDOUT

DSP Head er

SDIN

SDOUT

CS4270

SDOUT

SDIN

CS8416-FPGA-SDOUT

FPGA-SDIN

FPGA-HDR-SDOUT

CS4270-FPGA-SDOUT

CS4270-SDIN

FPGA

SDIO[1 :0]

DUT_SDIO[1:0]

TXSDIO [1:0]

CS8406-SDIN

CS8406

SDIN

Figure 4. Internal Data Routing

10 DS686DB3

2.4 Internal Drivers

Figure 5 shows the internal drivers and logic for board level selects/enables and so forth. Refe r to the FPGA
GUI Register Description section of this document for a description of the board level control register set-

tings.

.

MICRO-SDA/CCLK

CDB4270

FPGA

FPGA-SPI

HDR-SDA/CDOUT

MICRO-SCL/MISO

HDR-SCL/CCLK

FPGA-CS

HDR-AD1/CDIN

FPGA-AD0

FPGA-I2C

HDR-AD2

FPGA-MOSI

HDR-AD0/CS

FPGA-AD1

FPGA-SPI

FPGA-SPI

FPGA-SPI

FPGA-I2C

M1

M0

MDIV1

MDIV2

DIF

FPGA-SW/HW

FPGA-AD2

FPGA-I2C

FPGA-I2C

I2C

Figure 5. Internal Drivers

DS686DB3 11

2.5 External MCLK Control

Several sources for MCLK exist on the CDB4270. The crystal oscillator, Y1, will master the MCLK bus when
no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for details on OMCK operation).

When S/PDIF data is present at the CS8416 input, the CS8416 generates a master clock whenever its in­ternal PLL is locked to the incoming S/PDIF stream.

The DSP Header can master the MCLK bus or be an observation point for MCLK depe nding upon th e state
of the driver control signals from the FPGA.

Refer to the Register Description section of this document for a description of the MCLK routing co ntrol reg­isters.

.

CDB4270

OSC

CS8416

OMCK

CS8406

DSP Header

RMCK

OMCK

MCLK

CS4270

MCLK

FPGA

MCLK.FROM.8416

MCLK

MCLK.FROM.HDR

MCLK.TO.HDR

Figure 6. External MCLK Control

12 DS686DB3

CDB4270

3. SOFTWARE MODE

The CDB4270 uses a Microsoft Windows-based GUI (download from Cirrus web site), which allows control of the
CS4270 and FPGA registers. Interface to the GUI is provided via USB or RS-232 serial connection. Once the ap­propriate cable is connected between the CDB4270 and the host PC, run “FlexLoader.exe”. The software should
automatically detect the board. If a board selection dialog is displayed, select “CDB4270” from the list. Once loaded,
all registers are set to their default state. Note: The board is automatically set to Software Control Mode once the
serial or USB cable is installed and the GUI is up and running. The GUI’s “File” menu provides the ability to save
and load script files containing all of the register settings. Sample script file s for basic mode operation can be down­loaded from the archive at www.cirrus.com.

3.1 CDB4270 Control Scripts

Brief descriptions of the supplied scripts are given below.

3.1.1 S/PDIF In, Analog Out

When the SPDIF_IN_AOUT.FGS script is run, the CS8416 is the sub-clock (SCLK an d LRCK) master and
all other devices including the DSP Header are slaves. The CS8416 provides MCLK recovered from the
S/PDIF data and SDOUT to the CS4270 DAC, DSP Header and CS8406.

3.1.2 Analog In, S/PDIF Out

When the AIN_SPDIF_OUT.FGS script is run, the crystal oscillator is the MCLK master. The CS8416
passes the clock from the crystal oscillator, Y1, through to the RMCK output (Note: the S/PDIF input must
be disconnected) to the CS4270, the CS84 06 and the DSP Heade r. The CS4270 provides SDOUT to the
CS8406 and the DSP Header. The CS8406 generates sub-clocks derived from the CS4270 data and is
the sub-clock master. All other devices including the DSP Header are sub-clock slave devices.

3.1.3 Analog In, Analog Out (Digital Loop-Back)

When the AIN_AOUT.FGS script is run, the crystal oscillator is the MCLK master. The CS8416 passes
the clock from the crystal oscillator, Y1, through to the RMCK output (Note: the S/PDIF input must be dis­connected) to the CS4270, the CS8406 and the DSP Header. Th e CS8416 generates sub- clocks derived
from the crystal oscillator and is the sub-clock master. All other devices and the DSP Header are sub­clock slave devices. SDOUT from the CS4270 ADC is routed through the FPGA to the CS4270 DAC, to
the DSP Header and to the CS8406.

3.1.4 DSP In, Analog Out

When the DSP_IN_AOUT.FGS script is run, the DSP Header is the MCLK, sub-clock and data master
and all other devices are slaves. SDOUT at the header is the CS4270 SDOUT.

DS686DB3 13

3.2 CDB4270 GUI

Brief descriptions of the GUI tab views are provided below.
The CDB4270 Controls tab provides high-level control of the CS4270, FPGA (Board Controls) and S/PDIF

Tx and Rx devices. The “CS4270 Controls” group affects that device’s register settings. The “Board Con­trols” group allows the user to select MCLK and sub-clock source/routing as well as CS4270 and CS8406
SDIN sources. The “S/PDIF Receiver” and “S/PDIF Transmitter” control gr oups allow the user to select data
formats, MCLK frequency and master or slave for each device. Reset push-buttons are also availa ble along
with a “Comm Mode” select drop box for CS4270 communication mode format selection.

CDB4270

Figure 7. CDB4270 Controls Tab

14 DS686DB3

3.3 Register Maps Control Tabs

Under this tab are the CS4270, Board Configuration (FPGA) and GPIO tabs. On each tab, register values
can be modified bit-wise or byte-wise. For bit-wise modification, click the appropriate push-button fo r the
desired bit. For byte-wise modification, the desired hex value can be typed directly into th e register address
box in the register map. Refer to the CS4270 device data sheet registe r settings section and the FPGA reg­ister information in this document for register definitions.

CDB4270

Figure 8. Register Maps Tab - CS4270

DS686DB3 15