Evaluation Board for CS4265
CDB4265
Features
z Single-ended Analog Inputs
z Single-ended Analog Outputs
z Coaxial and Optical Connections for CS4265
S/PDIF Transmitter Output
z CS8416 S/PDIF Digital Audio Receiver
z Header for Optional External Software
Configuration of CS4265
z Header for External PCM Serial Audio I/O
z 3.3 V Logic Interface
z Pre-defined Software Scripts
z Demonstrates Recommended Layout and
Grounding Arrangements
z Windows
to Configure CS4265 and Inter-board
Connections
ORDERING INFORMATION
CDB4265 Evaluation Board
®
Compatible Software Interface
Description
The CDB4265 evaluation board is an excellent means
for evaluating the CS4265 CODEC. Evaluation requires
an analog/digital signal source and analyzer, and power
supplies. A Windows
used to evaluate the CS4265.
System timing for the I²S, Left-Justified and Right-Justified interface formats can be provided by the CS4265,
the CS8416, or by a PCM I/O stake header with an external source connected.
RCA phono jacks are provided for the CS4265 analog inputs and outputs. Digital data I/O is available via RCA
phono or optical connectors to the CS8416 and CS4265.
The Windows
®
uration of the CDB4265 easy. The software
communicates through the PC’s serial port to configure
the control port registers so that all features of the
CS4265 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
®
PC compatible computer must be
software provides a GUI to make config-
I
Cirrus Logic, Inc.
www.cirrus.com
Passive Input Filter
Active Input Filter
Microphone Input
Control Port Interface
M
U
X
CS4265
FPGA
Sub-clocks and Data
CS8416
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
Header
Passive Output Filter
Active Output Filter
S/PDIF Output Circuits
Test Points
Master Clock
Canned
Oscillator
FEB ‘05
DS657DB1
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4
1.1 Power ..... .............................................................................. ... ... ... ... .... ... ... ... .....................4
1.2 Grounding and Power Supply Decoupling ......................................................................... 4
1.3 CS4265 Audio CODEC ...................................................................................................... 4
1.4 CS8416 Digital Audio Receiver .......................................................................................... 4
1.5 FPGA ........................ .... ... ... ... .... ... ....................................... ... ... ... ... .... ... ...........................4
1.6 Canned Oscillator ......................................... ... ... .... ... ... ... .......................................... ........ 4
1.7 External Control Headers ...................................................................................................5
1.8 Analog Inputs ............ .... ... ... ... .... ... ... ... ....................................... ... ... .... ... ... ... .... ... ..............5
1.9 Analog Outputs ............................. ... ... ... ............................................................................ 5
1.10 Serial Control Port ............................................................................................................ 5
1.11 USB Control Port ............................................................................................................. 5
2. SYSTEM CLOCKS AND DATA ................................................................................................ 6
2.1 Clock Routing ................................... ... ... ............................................................................ 6
2.2 Data Routing ....................................................... .... .......................................... ... ..............6
2.2.1 CS4265 SDIN1 and SDIN2 Source ............... .......................................... ... ... ... .... . 6
2.2.2 CS4265 TXSDIN Source ....................................................................................... 6
3. PC SOFTWARE CONTROL .....................................................................................................7
3.1 CDB4265 Controls Tab ....... ... .... ... ... ... .......................................... ... .... ... ... ... .... ... ... ... ... .....7
3.2 S/PDIF Rx Controls Tab ......................................... .......................................... ... ..............8
3.3 Register Maps Tab ..................................... ... ... ... .... ... ... .......................................... ... ........9
3.4 Pre-Configured Script Files . ... .... ... ... ... ... .... ... ... .......................................... ... .... ... ... ... ........9
3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out ............................................. ... .... . 9
3.4.2 SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF Out ......................10
4. FPGA REGISTER QUICK REFERENCE ...............................................................................11
5. FPGA REGISTER DESCRIPTION .........................................................................................12
6. CDB CONNECTORS, JUMPERS, AND SWITCHES ............................................................. 16
7. CDB BLOCK DIAGRAM ..................................................................................................... 18
8. CDB SCHEMATICS ............................................................................................................... 19
9. CDB LAYOUT ........................................................................................................................ 27
10. REVISION HISTORY ............................................................................................................ 30
CDB4265
2 DS657DB1
LIST OF FIGURES
Figure 1. CDB4265 Controls Tab.................................................................................................... 7
Figure 2. S/PDIF Rx Controls Tab .................................................................................................. 8
Figure 3. Register Maps Tab........................................................................................................... 9
Figure 4. Block Diagram................................................................................................................ 18
Figure 5. CS4265.......................................................................................................................... 19
Figure 6. Analog Inputs................................................................................................................. 20
Figure 7. Analog Outputs.............................................................................................................. 21
Figure 8. S/PDIF I/O...................................................................................................................... 22
Figure 9. Control Port.................................................................................................................... 23
Figure 10. FPGA........................................................................................................................... 24
Figure 11. Discrete Clock Routing and Level Shifting................................................................... 25
Figure 12. Power........................................................................................................................... 26
Figure 13. Silk Screen................................................................................................................... 27
Figure 14. Topside Layer.............................................................................................................. 28
Figure 15. Bottom side Layer........................................................................................................ 29
LIST OF TABLES
Table 1. MCLK Source.................................................................................................................. 12
Table 2. CS4265 Subclock Source............................................................................................... 13
Table 3. SDIN2 Source................................................................................................................. 14
Table 4. SDIN1 Source................................................................................................................. 14
Table 5. TXSDIN Source............................................................................................................... 15
Table 6. System Connections.................... ... ... .......................................... ... ................................ 16
Table 7. System Jumper Settings....................... .... ... ... ... .... ... ... ... .... ......................................... ...17
Table 8. Revision History.............................................................................................................. 30
CDB4265
DS657DB1 3
CDB4265
1. SYSTEM OVERVIEW
The CDB4265 evaluation board is an excellent means for evaluating the CS4265 CODEC. Analog and dig ital audio
signal interfaces are provided, an on-board FPGA is used for easily configuring the evaluatio n platform, a nd a 9-pi n
serial cable is included for use with the supplied Windows
The CDB4265 schematic set is shown in Figures 5 through 12.
1.1 Power
Power must be supplied to the evaluation board through the red +5.0V binding post. On-board regulators
provide 3.3 V, 2.5 V, and 1.8 V supplies. Appropriate supply levels for powering VA, VD, VLS, and VLC are
set by a series of jumpers (see Table 7 on page 17). All voltage inputs must be referenced to the single black
binding post ground connector (see Table 6 on page 16).
WARNING: Please refer to the CS4265 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS4265 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 on page 18 provides an overview of the connections to the CS4265. Figure 13 on page 27
shows the component placement. Figure 14 on page 28 shows the top layout. Figure 15 on page 29 shows
the bottom layout. The decoupling capacitors are located as close to the CS4265 as possible. Extensive use
of ground plane fill in the evaluation board yields large reductions in radiated noise.
1.3 CS4265 Audio CODEC
A complete description of the CS4265 is included in the CS4265 product data sheet.
The required configuration settings of the CS4265 are made in its control port registers, accessible through
the CS4265 tab of the Cirrus Logic FlexGUI softwar e.
Clock and data source selections are made through the control port of the FPGA. Basic routing selections
can be made using the CS4265 Controls tab in the GUI software application. Advanced options are accessible through the Board Configuration sub-tab on the Register Maps tab of the Cirrus Logic FlexGUI software. Refer to the FPGA register descriptions sections beginning on page 12.
®
configuration software.
1.4 CS8416 Digital Audio Receiver
A complete description of the CS8416 receiver (Figure 8 on page 22) and a discussion of the digital audio
interface are included in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream into PCM da ta for the CS4265 and operates in master
or slave mode, generating eith er a 128 Fs or 256 Fs master clock on the RMCK output pin, and can operate
in the Left-Justified, I²S, Right-Justified 16-bit, and Right-Justified 24-bit interface formats.
The most common operations of the CS8416 may be controlled via the S/PDIF Rx Controls tab in the GUI
software application. Advanced option s are accessibl e through the CS8416 sub-tab on the Register Maps
tab of the Cirrus Logic FlexGUI software.
1.5 FPGA
The FPGA handles both clock and data routing on the CDB4265. Clock and data routing selections made
via the CDB4265 Controls tab in the GUI will be handled by the FPGA with no user interv ention required.
For advanced information regarding the internal registe rs and oper ation of the F PGA, see sections 4 and 5
beginning on page 11.
1.6 Canned Oscillator
A canned oscillator, Y1, is available to provide a master clock source to the CDB4265.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with
a 12.2880 MHz crystal oscillator populated.
4 DS657DB1
1.7 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the headers J15, and
J17.
The 14-pin, 2 row header, J15, provides access to the serial audio signals required to interface to the serial
audio port of the CS4265 with a DSP (see Figure 11).
The direction of the signals on header J15 can be configured using the controls located within the Board
Controls group box on the CDB4265 Controls tab in the provided GUI software.
The 12-pin, 3 row header, J17, allows the user bidirectional access to the SPI/I
removing all the shunt jumpers from the “PC” position. The user ma y then choose to connect a ribbon cable
to the “EXT CONTROL” position. A single “GND” row for the ribbon cable’s ground connection is provided
to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user choose to
use the CDB for the I
2
C power rail.
1.8 Analog Inputs
RCA connectors supply the CS4265 analog inputs through single-ended, unity gain, active or passive circuits. Refer to the CS4265 data sheet for the ADC full-scale level.
A 4-pin CD-ROM type header is provided for easily connecti ng the analog outputs from a CD-ROM drive to
the analog inputs of the CS4265.
1.9 Analog Outputs
The CS4265 analog outputs are routed through a two-pole active filter. The outpu t of th e filter is co nne cted
to RCA jacks for easy evaluation.
CDB4265
2
C control signals by simply
1.10 Serial Control Port
A graphical user interface is included with the CDB4265 to allow easy manipulation of the registers in the
CS4265, CS8416, and FPGA. See the device-specific data sheets for the CS4265, CS8416, and CD8406
internal register descriptions. The internal register map for the FPGA is located in section 4 on page 11.
Connecting a cable to the RS-232 connector (J19) and launching the Cirrus Logic FlexGUI software (FlexLoader.exe) will enable the CDB4265.
Refer to “PC Software Control” on page 7 for a description of the Graphical User Interface (GUI).
1.11 USB Control Port
The USB control port connector (J29) is currently unavailable.
DS657DB1 5
CDB4265
2. SYSTEM CLOCKS AND DATA
The CDB4265 implements comprehensive clock and data routing capabilities. Configuration of the clock and data
routing can be easily achieved using the controls within the Board Controls gr oup box on the CDB42 65 Controls tab
in the GUI software application.
2.1 Clock Routing
The master clock signal (MCLK) may be sourced from the canned oscillator (Y1), the CS8416 S/PDIF receiver, or the PCM I/O header (J15)
The sub-clock signals (SCLK and LRCK) may be sourced from the CS4265 in m aster mode, th e CS8416 in
master mode, or the PCM I/O header.
Clock routing configuration is a chieved using the MCLK Source and Subclock Source controls within the
Board Controls group box on the CDB4265 Controls tab in the GUI software application.
2.2 Data Routing
The CDB4265 implements comprehensive data routing capabilities. The SDIN source of the CS4265 may
be easily selected using the provided GUI software application.
2.2.1 CS4265 SDIN1 and SDIN2 Source
The CS8416 S/PDIF receiver, the PCM I/O header (J15), or the CS4265 serial data output (SDOUT) may
source the serial data input of the CS4265. Configuration of the CS4265 SDIN1 and SDIN2 source is
achieved using the respective CS4265 SDIN Source control within the Board Controls group box on the
CDB4265 Controls tab in the GUI software application.
2.2.2 CS4265 TXSDIN Source
The CS8416 S/PDIF receiver, the PCM I/O header (J15), or the CS4265 serial data output (SDOUT) may
source the serial data input of the CS4265. Configuratio n of the CS4265 TXSDIN sour ce is achieved usin g
the CS4265 TxSDIN Source control within the S/PDIF Transmitter group box on the CDB4 265 Controls tab
in the GUI software application.
6 DS657DB1
CDB4265
3. PC SOFTWARE CONTROL
The CDB4265 is shipped with a Microsoft Windows® based graphical user interface which allows control over the
CS4265, CS8416, and FPGA. The board control software communicates with the CDB4265 over the RS-232 interface using the PC’s COM1 port.
To use the board control software, the contents of the included CD-ROM should fir st be copied to a directory on the
PC’s local disk. If applied, the Read Only attribute should be removed from all files. Once the appropriate cable has
been connected between the CDB4265 and the host PC, load FlexLoader.exe from the Software directory. When
the software loads, all devices will be reset to their default reset state.
The GUI’s File menu provides the ability to save a nd load script file s contain ing all o f t he registe r setting s. Pr e-configured script files are provided for basic functionality. Refer to “Pre-Configured Script Files” on page 9 for details.
3.1 CDB4265 Controls Tab
The CDB4265 Controls tab provides a high-level intuitive interface to many of the configuration options of
the CS4265 and CDB4265. The controls within the CS4265 Controls group box (with the exception of the
AD0 control) control the internal registers of the CS4265. The controls within the Bo ard Co ntro ls group box
control the board level clock and data routing on the CDB4265.
Figure 1. CDB4265 Controls Tab
DS657DB1 7
3.2 S/PDIF Rx Controls Tab
When the CDB4265 is configured to make u se of the CS8416 S/PDIF re ceiver, these devices must be configured for proper operation. The S/PDIF Rx Controls tab pr ovides a high-level intuitive interface to the most
common configuration options of the CS8416.
CDB4265
Figure 2. S/PDIF Rx Controls Tab
8 DS657DB1
3.3 Register Maps Tab
The Register Maps tab provides low level control over the register level settings of the CS4265, CS8416,
and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise or bytewise. For bit-wise, click the appropriate push button for the desired bit. Fo r byte-wise, the desired h ex value
can be typed directly in the register address box in the register map.
CDB4265
Figure 3. Register Maps Tab
3.4 Pre-Configured Script Files
Pre-configured script files are provided with the CDB4265 to allow easy initial board bring-up. The board
configurations stored within these files are described in sections 3.4.1 - 3.4.2.
3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out
Using the pre-configured script file named “Oscillator Clock - Line In to DAC & SPDIF Out.txt”, an analog
input signal applied to the line level inputs of the CS4265 input multiplexer will be digitized by the ADC, transmitted in S/PDIF format by the CS 4265 internal S/PDIF transmitter, and converted to analog by the DAC
and output through the passive output filter.
The canned oscillator is the source of MCLK. The CS4265 is the sub-clock master to the PCM I/O header.
DS657DB1 9
CDB4265
3.4.2 SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF Out
Using the pre-configured script file named “SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF
Out.txt”, an analog input signal applied to the line level inputs of the CS4265 input multiplexer will be digitized by the ADC and transmitted in S/PDIF format by the CS4265 internal S/PDIF transmitter. The S/PDIF
signal received by the CS8416 will be recovered, decoded into PCM, and routed to the CS4265 DAC where
it will be converted to analog by the DAC and output through the passive output filter. For proper operation
of this script, a valid S/PDIF signal must be applied.
The CS8416 recovered clock is the source of MCLK. The CS8416 is also the sub-clock master to the
CS4265 and the PCM I/O header.
10 DS657DB1
CDB4265
4. FPGA REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function 7 6 5432 1 0
Code Rev. ID
01h
MCLK Source
02h
Subclock
03h
Source
CS4265 SDIN
03h
Source
Transmitter
04h
SDIN Source
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0
xxxxxx x x
Reserved Reserved MCLK1 MCLK0 Reserved Reserved Reserved Reserved
001000 0 0
Reserved Reserved Reserved Reserved Reserved Reserved SUBCLK1 SUBCLK0
000100 0 1
Reserved SDIN2.2 SDIN2.1 SDIN2.0 Reserved SDIN1.2 SDIN1.1 SDIN1.0
000000 0 0
Reserved Reserved Reserved Reserved Reserved TXSDIN2 TXSDIN1 TXSDIN0
000100 0 1
DS657DB1 11
CDB4265
5. FPGA REGISTER DESCRIPTION
5.1 CODE REVISION ID - REGISTER 01H
76543210
Rev7 Rev6 Rev5 Rev4 Rev3 Rev2 Rev1 Rev0
Function:
Identifies the revision of the FPGA code. This register is Read-Only.
5.2 MCLK SOURCE CONTROL - ADDRESS 02H
76543210
Reserved Reserved MCLK1 MCLK0 Reserved Reserved Reserved Reserved
5.2.1 MCLK SOURCE (BITS 5:4)
Default = 10
Function:
These bits select the source of the CS4265 MCLK signal. Table 1 shows the available settings.
Table 1. MCLK Source
MCLK1 MCLK0 MCLK Source
0 0 Oscillator
0 1 MCLK position on PCM Header (J15)
1 0 CS8416 RMCK
11 Reserved
12 DS657DB1
CDB4265
5.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H
76543210
Reserved Reserved Reserved Reserved Reserved Reserved SUBCLK1 SUBCLK0
5.3.1 SUBCLOCK SOURCE (BITS 1:0)
Default = 01
Function:
This bit selects the source of the CS4265 SCLK and LRCK signals. Table 2 shows the available settings.
Table 2. CS4265 Subclock Source
SUBCLK1 SUBCLK0 CS4265 Subclock Source
0 0 - CS4265 is Master
- PCM Header Subclocks are Output from CS4265
01 Reserved
1 0 - CS4265 is Slave to PCM Header
- PCM Header Subclocks are an Input
1 1 - CS4265 is Slave to CS8416 subclocks
- PCM Header Subclocks are Output from CS8416 Subclocks
DS657DB1 13
CDB4265
5.4 CS4265 SDIN SOURCE CONTROL - ADDRESS 04H
76543210
Reserved SDIN2.2 SDIN2.1 SDIN2.0 Reserved SDIN1.2 SDIN1.1 SDIN1.0
5.4.1 SDIN2 SOURCE (BITS 6:4)
Default = 00
Function:
These bits select the source of the CS4265 SDIN2 signal. Table 3 shows the available settings.
Table 3. SDIN2 Source
SDIN2.2 SDIN2.1 SDIN2.0 SDIN2 Source
0 0 0 CS8416 SDOUT
0 0 1 CS4265 SDOUT
0 1 0 SDIN1 from Header
0 1 1 SDIN2 from Header
1 0 0 TXSDIN from Header
101
... ... ... Reserved
111
5.4.2 SDIN1 SOURCE (BITS 2:0)
Default = 00
Function:
These bits select the source of the CS4265 SDIN1 signal. Table 4 shows the available settings.
Table 4. SDIN1 Source
SDIN1.2 SDIN1.1 SDIN1.0 SDIN1 Source
0 0 0 CS8416 SDOUT
0 0 1 CS4265 SDOUT
0 1 0 SDIN1 from Header
0 1 1 SDIN2 from Header
1 0 0 TXSDIN from Header
101
... ... ... Reserved
111
14 DS657DB1
CDB4265
5.5 TRANSMITTER SDIN SOURCE CONTROL - ADDRESS 05H
76543210
Reserved Reserved Reserved Reserved Reserved TXSDIN2 TXSDIN1 TXSDIN0
5.5.1 TXSDIN SOURCE (BITS 2:0)
Default = 01
Function:
These bits select the source of the CS4265 TXSDIN signal. Table 5 shows the available settings.
Table 5. TXSDIN Source
TXSDIN2 TXSDIN1 TXSDIN0 TXSDIN Source
0 0 0 CS8416 SDOUT
0 0 1 CS4265 SDOUT
0 1 0 SDIN1 from Header
0 1 1 SDIN2 from Header
1 0 0 TXSDIN from Header
101
... ... ... Reserved
111
DS657DB1 15
CDB4265
6. CDB CONNECTORS, JUMPERS, AND SWITCHES
Reference
CONNECTOR
+5V J4 Input
GND J3 Input
S/PDIF RX OPT1 Input
S/PDIF RX J1 Input
CS4265 TXOUT J13 Output CS4265 S/PDIF transmitter digital audio output via coaxial
CS4265 TXOUT OPT3 Output CS4265 S/PDIF transmitter digital audio output via optical
RS232 I/O J19 Input/Output
USB I/O J29 Input/Output
PCM I/O J15 Input/Output
CONTROL J17 Input/Output
MICRO JTAG J22 Input/Output
FPGA-JTAG J23 Input/Output
RESET S2 Input
PROGRAM FPGA S1 Input
AINA
AINB
CD IN J30 Input CD-ROM type header for analog input signal to CS4265.
MICIN1
MICIN2
AOUTA
AOUTB
Designator INPUT/OUTPUT SIGNAL PRESENT
+5.0 V Power Supply
Ground Reference
CS8416 digital audio input via optical cable
CS8416 digital audio input via coaxial cable
cable
cable
Serial connection to PC for SPI / I2C control port signals
USB connection to PC for SPI / I2C control port signals.
Not Available.
I/O for Serial Audio Clocks & Data
I/O for external SPI / I2C control port signals.
I/O for programming the micro controller (U32).
I/O for programming the FPGA (U27).
Reset for the micro controller (U32).
Reset for the FPGA (U27).
J18
J24
J14
J16
J14
J16
Input RCA phono jacks for analog input signal to CS4265.
Input
Output
1/8“ TRS jacks for microphone input.
RCA phono jacks for DAC analog outputs.
Table 6. System Connections
16 DS657DB1
JUMPER PURPOSE POSITION FUNCTION SELECTED
J6 Selects the source of voltage for the VLS
supply.
J7 Selects the source of voltage for the VLC
supply.
J11 Selects the source of voltage for the VD
supply.
J12 Selects the source of voltage for the VA
supply.
J20
J21
J26
J27
J28 Selects the source of the CS4265 SGND
Selects the input connector for the mic
inputs of the CS4265 ADC input multiplexer.
Selects the input connector for the line
inputs of the CS4265 ADC input multiplexer.
signal.
*Default factory settings
Table 7. System Jumper Settings
+1.8 V
+2.5 V
+3.3 V
+5 V*
+1.8 V
+2.5 V
+3.3 V
+5 V*
+3.3 V
+5 V*
+3.3 V
+5 V*
Line Input*
Mic Input
RCA*
CD
GND*
SGND
Voltage source is +1.8 V regulator.
Voltage source is +2.5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Voltage source is +1.8 V regulator.
Voltage source is +2.5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +5 V regulator.
Select RCA inputs as source.
Select TRS inputs as source.
Select RCA inputs as source.
Select CD input as source.
Local connection to board ground plane.
SGND signal from CD IN connector.
CDB4265
DS657DB1 17
7. CDB BLOCK DIAGRAM
CDB4265
Canned
Oscillator
Test Points
Passive Output Filter
M
Activ e Outpu t Filter
U
S/PDIF O utput Circuits
Master Clock
Header
FPGA
CS4265
Sub-clocks and Data
Figure 4. Block Diagram
CS8416
X
Pas siv e In p ut F ilte r
18 DS657DB1
Activ e In p u t F ilte r
Microphone Input
Con tro l Port In te rfa c e
8. CDB SCHEMATICS
CDB4265
Figure 5. CS4265
DS657DB1 19
CDB4265
Figure 6. Analog Inputs
20 DS657DB1
CDB4265
Figure 7. Analog Outputs
DS657DB1 21
CDB4265
Figure 8. S/PDIF I/O
22 DS657DB1
CDB4265
Figure 9. Control Port
DS657DB1 23
CDB4265
Figure 10. FPGA
24 DS657DB1
CDB4265
Figure 11. Discrete Clock Routing and Level Shifting
DS657DB1 25
CDB4265
Figure 12. Power
26 DS657DB1
9. CDB LAYOUT
CDB4265
Figure 13. Silk Screen
DS657DB1 27
CDB4265
Figure 14. Topside Layer
28 DS657DB1
CDB4265
Figure 15. Bottom side Layer
DS657DB1 29
10.REVISION HISTORY
Revision Date Changes
DB1 February 2005 Initial Release
Table 8. Revision History
CDB4265
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the infor-
mation is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain
the latest version of relevant information t o verify, before placing orders, that inf ormation being relied on is curre nt and complete. All products are
sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification,
and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any item s, or f or i nf ring eme nt of patents or o t her r ig hts of t hird partie s. Th is do cum ent i s th e p roper t y o f Cirrus and by furnishing
this information, Cirrus g rants no license, express or implied under an y patents, mask work rights, cop yrights, trademarks, tr ade secrets or other
intellectual property rights. Cirr us own s th e copy ri gh ts associ at ed w ith t he inf o rmati o n con tained he re in an d gi ves co nse nt for copies to be made of
the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend
to other copying such as copyin g for general distribution, advertising or promotional purposes, or for creating any work for resale.
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OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRIT ICAL APPL ICATIONS, CUSTOMER AGREES,
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ANY AND ALL LIABILITY , INCLUDING A TT ORNEYS' FEES AND COSTS, THA T MAY RESUL T FROM OR ARISE IN CONNECTION WITH THESE
USES.
Cirrus Logic, Cirrus, the Cirr us Logic log o designs, an d Popguard are tradema rks of Cirru s Logic, Inc. All other br and and prod uct names in this doc ument may be trademarks or service mar ks of their respective owners.
Windows is a registered trademark of Microsoft Corporation.
30 DS657DB1
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