Cirrus Logic CDB4265 User Manual

Evaluation Board for CS4265

CDB4265

Features

z Single-ended Analog Inputs
z Single-ended Analog Outputs
z Coaxial and Optical Connections for CS4265

S/PDIF Transmitter Output

z CS8416 S/PDIF Digital Audio Receiver
z Header for Optional External Software

Configuration of CS4265

z Header for External PCM Serial Audio I/O
z 3.3 V Logic Interface
z Pre-defined Software Scripts
z Demonstrates Recommended Layout and

Grounding Arrangements

z Windows

to Configure CS4265 and Inter-board
Connections

ORDERING INFORMATION

CDB4265 Evaluation Board

®

Compatible Software Interface

Description

The CDB4265 evaluation board is an excellent means
for evaluating the CS4265 CODEC. Evaluation requires
an analog/digital signal source and analyzer, and power
supplies. A Windows
used to evaluate the CS4265.

System timing for the I²S, Left-Justified and Right-Justi­fied interface formats can be provided by the CS4265,
the CS8416, or by a PCM I/O stake header with an ex­ternal source connected.

RCA phono jacks are provided for the CS4265 analog in­puts and outputs. Digital data I/O is available via RCA
phono or optical connectors to the CS8416 and CS4265.

The Windows

®

uration of the CDB4265 easy. The software
communicates through the PC’s serial port to configure
the control port registers so that all features of the
CS4265 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.

®

PC compatible computer must be

software provides a GUI to make config-

I

Cirrus Logic, Inc.

www.cirrus.com

Passive Input Filter

Active Input Filter

Microphone Input

Control Port Interface

M
U
X

CS4265

FPGA

Sub-clocks and Data

CS8416

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

Header

Passive Output Filter

Active Output Filter

S/PDIF Output Circuits

Test Points

Master Clock

Canned

Oscillator

FEB ‘05

DS657DB1

TABLE OF CONTENTS

1. SYSTEM OVERVIEW ............................................................................................................... 4

1.1 Power ..... .............................................................................. ... ... ... ... .... ... ... ... .....................4

1.2 Grounding and Power Supply Decoupling ......................................................................... 4

1.3 CS4265 Audio CODEC ...................................................................................................... 4

1.4 CS8416 Digital Audio Receiver .......................................................................................... 4

1.5 FPGA ........................ .... ... ... ... .... ... ....................................... ... ... ... ... .... ... ...........................4

1.6 Canned Oscillator ......................................... ... ... .... ... ... ... .......................................... ........ 4

1.7 External Control Headers ...................................................................................................5

1.8 Analog Inputs ............ .... ... ... ... .... ... ... ... ....................................... ... ... .... ... ... ... .... ... ..............5

1.9 Analog Outputs ............................. ... ... ... ............................................................................ 5

1.10 Serial Control Port ............................................................................................................ 5

1.11 USB Control Port ............................................................................................................. 5

2. SYSTEM CLOCKS AND DATA ................................................................................................ 6

2.1 Clock Routing ................................... ... ... ............................................................................ 6

2.2 Data Routing ....................................................... .... .......................................... ... ..............6

2.2.1 CS4265 SDIN1 and SDIN2 Source ............... .......................................... ... ... ... .... . 6

2.2.2 CS4265 TXSDIN Source ....................................................................................... 6

3. PC SOFTWARE CONTROL .....................................................................................................7

3.1 CDB4265 Controls Tab ....... ... .... ... ... ... .......................................... ... .... ... ... ... .... ... ... ... ... .....7

3.2 S/PDIF Rx Controls Tab ......................................... .......................................... ... ..............8

3.3 Register Maps Tab ..................................... ... ... ... .... ... ... .......................................... ... ........9

3.4 Pre-Configured Script Files . ... .... ... ... ... ... .... ... ... .......................................... ... .... ... ... ... ........9

3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out ............................................. ... .... . 9

3.4.2 SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF Out ......................10

4. FPGA REGISTER QUICK REFERENCE ...............................................................................11

5. FPGA REGISTER DESCRIPTION .........................................................................................12

6. CDB CONNECTORS, JUMPERS, AND SWITCHES ............................................................. 16

7. CDB BLOCK DIAGRAM ..................................................................................................... 18

8. CDB SCHEMATICS ............................................................................................................... 19

9. CDB LAYOUT ........................................................................................................................ 27

10. REVISION HISTORY ............................................................................................................ 30

CDB4265

2 DS657DB1

LIST OF FIGURES

Figure 1. CDB4265 Controls Tab.................................................................................................... 7

Figure 2. S/PDIF Rx Controls Tab .................................................................................................. 8

Figure 3. Register Maps Tab........................................................................................................... 9

Figure 4. Block Diagram................................................................................................................ 18

Figure 5. CS4265.......................................................................................................................... 19

Figure 6. Analog Inputs................................................................................................................. 20

Figure 7. Analog Outputs.............................................................................................................. 21

Figure 8. S/PDIF I/O...................................................................................................................... 22

Figure 9. Control Port.................................................................................................................... 23

Figure 10. FPGA........................................................................................................................... 24

Figure 11. Discrete Clock Routing and Level Shifting................................................................... 25

Figure 12. Power........................................................................................................................... 26

Figure 13. Silk Screen................................................................................................................... 27

Figure 14. Topside Layer.............................................................................................................. 28

Figure 15. Bottom side Layer........................................................................................................ 29

LIST OF TABLES

Table 1. MCLK Source.................................................................................................................. 12

Table 2. CS4265 Subclock Source............................................................................................... 13

Table 3. SDIN2 Source................................................................................................................. 14

Table 4. SDIN1 Source................................................................................................................. 14

Table 5. TXSDIN Source............................................................................................................... 15

Table 6. System Connections.................... ... ... .......................................... ... ................................ 16

Table 7. System Jumper Settings....................... .... ... ... ... .... ... ... ... .... ......................................... ...17

Table 8. Revision History.............................................................................................................. 30

CDB4265

DS657DB1 3

CDB4265

1. SYSTEM OVERVIEW

The CDB4265 evaluation board is an excellent means for evaluating the CS4265 CODEC. Analog and dig ital audio
signal interfaces are provided, an on-board FPGA is used for easily configuring the evaluatio n platform, a nd a 9-pi n
serial cable is included for use with the supplied Windows

The CDB4265 schematic set is shown in Figures 5 through 12.

1.1 Power

Power must be supplied to the evaluation board through the red +5.0V binding post. On-board regulators
provide 3.3 V, 2.5 V, and 1.8 V supplies. Appropriate supply levels for powering VA, VD, VLS, and VLC are
set by a series of jumpers (see Table 7 on page 17). All voltage inputs must be referenced to the single black
binding post ground connector (see Table 6 on page 16).

WARNING: Please refer to the CS4265 data sheet for allowable voltage levels.

1.2 Grounding and Power Supply Decoupling

The CS4265 requires careful attention to power supply and grounding arrangements to optimize perfor­mance. Figure 4 on page 18 provides an overview of the connections to the CS4265. Figure 13 on page 27
shows the component placement. Figure 14 on page 28 shows the top layout. Figure 15 on page 29 shows
the bottom layout. The decoupling capacitors are located as close to the CS4265 as possible. Extensive use
of ground plane fill in the evaluation board yields large reductions in radiated noise.

1.3 CS4265 Audio CODEC

A complete description of the CS4265 is included in the CS4265 product data sheet.
The required configuration settings of the CS4265 are made in its control port registers, accessible through

the CS4265 tab of the Cirrus Logic FlexGUI softwar e.
Clock and data source selections are made through the control port of the FPGA. Basic routing selections

can be made using the CS4265 Controls tab in the GUI software application. Advanced options are acces­sible through the Board Configuration sub-tab on the Register Maps tab of the Cirrus Logic FlexGUI soft­ware. Refer to the FPGA register descriptions sections beginning on page 12.

®

configuration software.

1.4 CS8416 Digital Audio Receiver

A complete description of the CS8416 receiver (Figure 8 on page 22) and a discussion of the digital audio
interface are included in the CS8416 data sheet.

The CS8416 converts the input S/PDIF data stream into PCM da ta for the CS4265 and operates in master
or slave mode, generating eith er a 128 Fs or 256 Fs master clock on the RMCK output pin, and can operate
in the Left-Justified, I²S, Right-Justified 16-bit, and Right-Justified 24-bit interface formats.

The most common operations of the CS8416 may be controlled via the S/PDIF Rx Controls tab in the GUI
software application. Advanced option s are accessibl e through the CS8416 sub-tab on the Register Maps
tab of the Cirrus Logic FlexGUI software.

1.5 FPGA

The FPGA handles both clock and data routing on the CDB4265. Clock and data routing selections made
via the CDB4265 Controls tab in the GUI will be handled by the FPGA with no user interv ention required.
For advanced information regarding the internal registe rs and oper ation of the F PGA, see sections 4 and 5
beginning on page 11.

1.6 Canned Oscillator

A canned oscillator, Y1, is available to provide a master clock source to the CDB4265.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with

a 12.2880 MHz crystal oscillator populated.

4 DS657DB1

1.7 External Control Headers

The evaluation board has been designed to allow interfacing with external systems via the headers J15, and
J17.

The 14-pin, 2 row header, J15, provides access to the serial audio signals required to interface to the serial
audio port of the CS4265 with a DSP (see Figure 11).

The direction of the signals on header J15 can be configured using the controls located within the Board
Controls group box on the CDB4265 Controls tab in the provided GUI software.

The 12-pin, 3 row header, J17, allows the user bidirectional access to the SPI/I
removing all the shunt jumpers from the “PC” position. The user ma y then choose to connect a ribbon cable
to the “EXT CONTROL” position. A single “GND” row for the ribbon cable’s ground connection is provided
to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user choose to
use the CDB for the I

2

C power rail.

1.8 Analog Inputs

RCA connectors supply the CS4265 analog inputs through single-ended, unity gain, active or passive cir­cuits. Refer to the CS4265 data sheet for the ADC full-scale level.

A 4-pin CD-ROM type header is provided for easily connecti ng the analog outputs from a CD-ROM drive to
the analog inputs of the CS4265.

1.9 Analog Outputs

The CS4265 analog outputs are routed through a two-pole active filter. The outpu t of th e filter is co nne cted
to RCA jacks for easy evaluation.

CDB4265

2

C control signals by simply

1.10 Serial Control Port

A graphical user interface is included with the CDB4265 to allow easy manipulation of the registers in the
CS4265, CS8416, and FPGA. See the device-specific data sheets for the CS4265, CS8416, and CD8406
internal register descriptions. The internal register map for the FPGA is located in section 4 on page 11.

Connecting a cable to the RS-232 connector (J19) and launching the Cirrus Logic FlexGUI software (Flex­Loader.exe) will enable the CDB4265.

Refer to “PC Software Control” on page 7 for a description of the Graphical User Interface (GUI).

1.11 USB Control Port

The USB control port connector (J29) is currently unavailable.

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CDB4265

2. SYSTEM CLOCKS AND DATA

The CDB4265 implements comprehensive clock and data routing capabilities. Configuration of the clock and data
routing can be easily achieved using the controls within the Board Controls gr oup box on the CDB42 65 Controls tab
in the GUI software application.

2.1 Clock Routing

The master clock signal (MCLK) may be sourced from the canned oscillator (Y1), the CS8416 S/PDIF re­ceiver, or the PCM I/O header (J15)

The sub-clock signals (SCLK and LRCK) may be sourced from the CS4265 in m aster mode, th e CS8416 in
master mode, or the PCM I/O header.

Clock routing configuration is a chieved using the MCLK Source and Subclock Source controls within the
Board Controls group box on the CDB4265 Controls tab in the GUI software application.

2.2 Data Routing

The CDB4265 implements comprehensive data routing capabilities. The SDIN source of the CS4265 may
be easily selected using the provided GUI software application.

2.2.1 CS4265 SDIN1 and SDIN2 Source

The CS8416 S/PDIF receiver, the PCM I/O header (J15), or the CS4265 serial data output (SDOUT) may
source the serial data input of the CS4265. Configuration of the CS4265 SDIN1 and SDIN2 source is
achieved using the respective CS4265 SDIN Source control within the Board Controls group box on the
CDB4265 Controls tab in the GUI software application.

2.2.2 CS4265 TXSDIN Source

The CS8416 S/PDIF receiver, the PCM I/O header (J15), or the CS4265 serial data output (SDOUT) may
source the serial data input of the CS4265. Configuratio n of the CS4265 TXSDIN sour ce is achieved usin g
the CS4265 TxSDIN Source control within the S/PDIF Transmitter group box on the CDB4 265 Controls tab
in the GUI software application.

6 DS657DB1

CDB4265

3. PC SOFTWARE CONTROL

The CDB4265 is shipped with a Microsoft Windows® based graphical user interface which allows control over the
CS4265, CS8416, and FPGA. The board control software communicates with the CDB4265 over the RS-232 inter­face using the PC’s COM1 port.

To use the board control software, the contents of the included CD-ROM should fir st be copied to a directory on the
PC’s local disk. If applied, the Read Only attribute should be removed from all files. Once the appropriate cable has
been connected between the CDB4265 and the host PC, load FlexLoader.exe from the Software directory. When
the software loads, all devices will be reset to their default reset state.

The GUI’s File menu provides the ability to save a nd load script file s contain ing all o f t he registe r setting s. Pr e-con­figured script files are provided for basic functionality. Refer to “Pre-Configured Script Files” on page 9 for details.

3.1 CDB4265 Controls Tab

The CDB4265 Controls tab provides a high-level intuitive interface to many of the configuration options of
the CS4265 and CDB4265. The controls within the CS4265 Controls group box (with the exception of the
AD0 control) control the internal registers of the CS4265. The controls within the Bo ard Co ntro ls group box
control the board level clock and data routing on the CDB4265.

Figure 1. CDB4265 Controls Tab

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3.2 S/PDIF Rx Controls Tab

When the CDB4265 is configured to make u se of the CS8416 S/PDIF re ceiver, these devices must be con­figured for proper operation. The S/PDIF Rx Controls tab pr ovides a high-level intuitive interface to the most
common configuration options of the CS8416.

CDB4265

Figure 2. S/PDIF Rx Controls Tab

8 DS657DB1

3.3 Register Maps Tab

The Register Maps tab provides low level control over the register level settings of the CS4265, CS8416,
and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise or byte­wise. For bit-wise, click the appropriate push button for the desired bit. Fo r byte-wise, the desired h ex value
can be typed directly in the register address box in the register map.

CDB4265

Figure 3. Register Maps Tab

3.4 Pre-Configured Script Files

Pre-configured script files are provided with the CDB4265 to allow easy initial board bring-up. The board
configurations stored within these files are described in sections 3.4.1 - 3.4.2.

3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out

Using the pre-configured script file named “Oscillator Clock - Line In to DAC & SPDIF Out.txt”, an analog
input signal applied to the line level inputs of the CS4265 input multiplexer will be digitized by the ADC, trans­mitted in S/PDIF format by the CS 4265 internal S/PDIF transmitter, and converted to analog by the DAC
and output through the passive output filter.

The canned oscillator is the source of MCLK. The CS4265 is the sub-clock master to the PCM I/O header.

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