Cirrus Logic CDB42448 User Manual
CDB42448
Evaluation Board For CS42448
Features
z Single-ended/Single-ended to Differential
Analog Inputs
z Single-ended/Differential to Single-ended
Analog Outputs
z CS8406 S/PDIF Digital Audio Transmitter
z CS8416 S/PDIF Digital Audio Receiver
z Header for Optional External Software
Configuration of CS42448
z Header for External DSP Serial Audio I/O
z 3.3 V Logic Interface
z Pre-defined Software Scripts
z S/PDIF-to-TDM Conversion for Easy
Evaluation of the TDM Digital Interface
z Demonstrates Recommended Layout and
Grounding Arrangements
z Windows
Configure CS42448 and Inter-board
Connections
ORDERING INFORMATION
CDB42448 Evaluation Board
®
Compatible Software Interface to
Description
The CDB42448 evaluation bo ard is an exc ellent mean s
for evaluating the CS42448 CODEC. Evaluation requires an analog/digital signal source and analyzer, and
power supplies. A Windows
must be used to evaluate the CS42448.
System timing for the I²S, Left-Justified and Right-Justified interface formats can be provided by the CS42448,
by the CS8416, or by a DSP I/O stake header with a DSP
connected. System timing for TDM mode is provided by
an FPGA using clocks derived from the CS8416 or DSP
I/O header.
RCA phono jacks are provided for the CS42448 analog
inputs and outputs. Digital data I/O is available via RCA
phono or optical connectors to the CS8416 and CS8406.
The Windows
®
software provides a GUI to make configuration of the CDB42448 easy. The software
communicates through the PC’s serial port to configure
the control port registers so that all features of the
CS42448 can be evaluated. The evaluation board may
also be configured to accept external timing and data
signals for operation in a user application during system
development.
®
PC compatible computer
I
Cirrus Logic, Inc.
www.cirrus.com
CS8406
S/PDIF
Output
CS8416
S/PDIF
Input
Osc.
Clocks/Data
MCLK BUS
Hardware
Setup
Clocks
/Data
DSP HEADER
Serial Control Port
CS42448
ADC/DAC
Clocks/
Data
FPGA
ADC/DAC Clocks & Data
MCLK Divided
CS5341
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
I2C/SPI Header
ANALOG INPUT
y Single-Ended to
Differential Input
y Single-Ended
Input
ANALOG OUTPUT
y Differential to
Single-Ended
Output
y Single-Ended
Output
AUXILIARY
ANALOG INPUT
y Single-Ended
Input
OCT ‘04
DS648DB2
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4
1.1 Power ..... ....................................... ... ... ... .... ... ... ....................................... ... ... .... ... .............. 4
1.2 Grounding and Power Supply Decoupling ......................................................................... 4
1.3 FPGA ........................ .... ... ... ... .... ... ....................................... ... ... ... ..................................... 4
1.4 CS42448 Audio CODEC ..................................... .... ... ... ... .... ... ... ... ... .................................. 4
1.5 CS8406 Digital Audio Transmitter ......................................................................................4
1.6 CS8416 Digital Audio Receiver .......................................................................................... 5
1.7 CS5341 ............... ... ... .... ... ....................................... ... ... ... .... ... ...........................................5
1.8 Canned Oscillator ......................................... ... ... .... ... ... ... ....................................... ... ........ 5
1.9 External Control Headers ...................................................................................................5
1.10 Analog Input ..................................................................................................................... 6
1.11 Analog Outputs ................................................................................................................6
1.12 Serial Control Port ............................................................................................................ 6
1.13 USB Control Port ............................................................................................................. 6
2. SOFTWARE MODE .................................................................................................................. 7
2.1 Advanced Register Debug Tab .. ... ... ... ... .... .......................................... .............................. 7
3. FPGA SYSTEM OVERVIEW .................................................................................................... 9
3.1 FPGA Setup . .... ... ... ... .... ...................................... .... ... ... ....................................... ... ... ........ 9
3.1.1 S/PDIF In, S/PDIF Out (SPDIF1-4) ............... ........................................................9
3.1.2 Analog In, Analog Out (Digital Loopback) ............................................... ... ... ... .... . 9
3.1.3 DSP Routing .......................... ... .... ... ....................................... ... ... ... .... ... ... ...........9
3.2. Internal Sub-Clock Routing .............................................................................................10
3.3. Internal Data Routing ......................................................................................................11
3.4. Internal TDM Conversion, MUXing and Control (TDMer) ...............................................12
3.5 External MCLK Control .................................................................................................... 13
3.5.1 CS5341 MCLK ....... ... .... ... ... ... ... ....................................... ... .... ... .........................13
3.5.2 TDMer MCLK ................ ...................................... .... ... ... ... ... .... ............................ 13
3.6 Bypass Control - Advanced ............................................................................................. 14
4. FPGA REGISTER QUICK REFERENCE ...............................................................................15
5. FPGA REGISTER DESCRIPTION .........................................................................................16
6. CDB CONNECTORS AND JUMPERS ................................................................................... 28
7. CDB BLOCK DIAGRAM ................................................................................................... 30
8. CDB SCHEMATICS ............................................................................................................. 31
9. CDB LAYOUT ..................................................................................................................... 41
10. REVISION HISTORY ............................................................................................................ 44
CDB42448
2 DS648DB2
LIST OF FIGURES
Figure 1. Advanced Register Tab - CS42448................................................................................. 7
Figure 2. Advanced Register Tab - FPGA ...................................................................................... 8
Figure 3. Internal Sub-Clock Routing............................................................................................10
Figure 4. Internal Data Routing..................................................................................................... 11
Figure 5. TDMer............................................................................................................................ 12
Figure 6. External MCLK Control .................................................................................................. 13
Figure 7. Bypass FPGA Control.................................................................................................... 14
Figure 8. Block Diagram................................................................................................................ 30
Figure 9. CS42448........................................................................................................................ 31
Figure 10. FPGA........................................................................................................................... 32
Figure 11. S/PDIF Input & Output................................................................................................. 33
Figure 12. Control Port.................................................................................................................. 34
Figure 13. Buffers - FPGA Bypass................................................................................................35
Figure 14. Buffers - DSP Routing.................................................................................................. 36
Figure 15. Analog Inputs............................................................................................................... 37
Figure 16. Auxiliary Input .............................................................................................................. 38
Figure 17. Analog Outputs............................................................................................................ 39
Figure 18. Power........................................................................................................................... 40
Figure 19. Silk Screen................................................................................................................... 41
Figure 20. Topside Layer.............................................................................................................. 42
Figure 21. Bottom side Layer........................................................................................................ 43
CDB42448
LIST OF TABLES
Table 1. Data to SDIN4................................................................................................................. 17
Table 2. Data to SDIN3................................................................................................................. 17
Table 3. Data to SDIN2................................................................................................................. 17
Table 4. Data to SDIN1................................................................................................................. 18
Table 5. Clocks to DAC................................................................................................................. 18
Table 6. Clocks to ADC................................................................................................................. 19
Table 7. Data to CS8406............................................................................................................... 19
Table 8. Data to DSP.................................................................................................................... 24
Table 9. System Connections.................... ... ... ....................................... ... ... .... ... ... ... .... ... ... ......... 28
Table 10. Jumper Settings............................ ... ... .... ... ... ... .... ... ... .......................................... ......... 29
Table 11. Revision History......................... ... ... ... .... .......................................... ............................ 44
DS648DB2 3
CDB42448
1. SYSTEM OVERVIEW
The CDB42448 evaluation board is an excellent means for evaluating the CS42448 CODEC. Analog and digital audio signal interfaces are provided, an FPGA used for easily configuring the
board and a 9-pin serial cable for use with the supplied Windows® configuration software.
The CDB42448 schematic set has been partitioned into 10 pages and is shown in Figures 9
through 18.
1.1 Power
Power must be supplied to the evaluation board through the +5.0 V, +12.0 V and -12.0 V
binding posts. Jumper J1 connects the VA supply to a fixed +5.0 V or +3.3 V supply. VD, VLS
and VLC are all hard-tied to +3.3 V. All voltage inputs must be referenced to the single black
binding post ground connector (Figure 18 on page 40).
WARNING: Please refer to the CS42448 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS42448 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 9 on page 31 provides an overview of the connections to the
CS42448. Figure 19 on page 41 shows the component placement. Figure 20 on page 42
shows the top layout. Figure 21 on page 43 shows the bottom layout. The decoupling capacitors are located as close to the CS42448 as possible. Extensive use of ground plane fill in
the evaluation board yields large reductions in radiated noise.
1.3 FPGA
See “FPGA System Overview” on page 9 for a complete description of how the FPGA (Figure
10 on page 32) is used on the CDB42448.
1.4 CS42448 Audio CODEC
A complete description of the CS42448 (Figure 9 on page 31) is included in the CS42448
product data sheet.
The required configuration settings of the CS42448 are made in its control port registers, accessible through the “CS42448” tab of the Cirrus Logic FlexGUI software.
Clock and data source selections are made in the control port of the FPGA, accessible
through the “FPGA” tab of the Cirrus Logic FlexGUI software. Refer to registers “CODEC
SDINx Control (address 02h)” on page 17 and “CODEC Clock Control (address 03h)” on
page 18 for configuration settings.
1.5 CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter (Figure 11 on page 33) and a discussion
of the digital audio interface are included in the CS8406 data sheet.
The CS8406 converts the PCM data generated by the CS42448 to the standard S/PDIF data
stream. The CS8406 operates in slave mode, accepting either a 128Fs or 256Fs master
4 DS648DB2
CDB42448
clock on the OMCK input pin, and can operate in either the Left-Justified or I²S interface format.
Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of
the Cirrus Logic FlexGUI software. Refer to register “CS8406 Control (address 04h)” on
page 19 for configuration settings.
1.6 CS8416 Digital Audio Receiver
A complete description of the CS8416 receiver (Figure 11 on page 33) and a discussion of
the digital audio interface are included in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream into PCM data for the CS42448 and operates in master or slave mode, generating either a 128Fs or 256Fs master clock on the
RMCK output pin, and can operate in either the Left-Justified or I²S interface format.
Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of
the Cirrus Logic FlexGUI software. Refer to register “CS8416 Control (address 05h)” on
page 21 for configuration settings.
1.7 CS5341
A complete description of the CS5341 Audio ADC (Figure 16 on page 38) is included in the
CS5341 data sheet.
The CS5341 is connected to the AUX port of the CS42448 and is used only in the TDM interface format of the CODEC. The AUX port of the CS42448 masters the CS5341 and accepts either Left-Justified or I²S data on AUX_SDIN.
Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of
the Cirrus Logic FlexGUI software. Refer to register “CS5341 and Miscellaneous Control (Address 08h)” on page 26 for configuration settings.
1.8 Canned Oscillator
Oscillator Y1 provides a system master clock. This clock is routed through the CS8416 and
out the RMCK pin when the S/PDIF input is disconnected (refer to the CS8416 data sheet for
details on OMCK operation). To use the canned oscillator as the source of the MCLK signal,
remove the S/PDIF input to the CS8416 and configure the CS8416 appropriately.
The oscillator is mounted in pin sockets, allowing easy removal or replacement.The board is
shipped with a 12.2880 MHz crystal oscillator populated at Y1.
1.9 External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the
headers J11 and J25.
The 24-pin, 2 row header, J25, provides access to the serial audio signals required to interface with a DSP (see Figure 13 on page 35).
DS648DB2 5
CDB42448
Selections are made in the control port of the FPGA, accessible through the “FPGA” tab of
the Cirrus Logic FlexGUI software. Refer to register “DSP Header Control (address 07h)” on
page 24 for configuration settings
The 12-pin, 3 row header, J11, allows the user bidirectional access to the SPI/I2C control signals by simply removing all the shunt jumpers from the “PC” position. The user may then
choose to connect a ribbon cable to the “EXTERNAL” position. A single “GND” row for the
ribbon cable’s ground connection is provided to maintain signal integrity. Two unpopulated
pull-up resistors are also available should the user choose to use the CDB for the I2C power
rail.
1.10 Analog Input
RCA connectors supply the CS42448 analog inputs through unity gain, AC-coupled singleended to differential circuits. The inputs may also be driven single-ended by shunting the appropriate stake headers labeled “Single In”. A 1 Vrms single-ended signal into the RCA connectors will drive the CS42448 inputs to full scale.
1.11 Analog Outputs
The CS42448 analog outputs may be routed either through a single-pole RC passive filter,
or a differential to single-ended 2-pole active filter.
1.12 Serial Control Port
A graphical user interface is included with the CDB42448 to allow easy manipulation of the
registers in the CS42448 (see the CS42448 data sheet for register descriptions) and FPGA
(see section 5 on page 16 for register descriptions). Connecting a cable to the RS-232 connector (J7) and launching the Cirrus Logic FlexGUI software will enable the CDB42448.
Refer to “Software Mode” on page 7 for a description of the Graphical User Interface (GUI).
1.13 USB Control Port
The USB control port connector (J12) is currently unavailable.
6 DS648DB2
CDB42448
2. SOFTWARE MODE
The CDB42448 is shipped with a Microsoft Windows® based GUI, which allows control over the
CS42448 and FPGA registers. Interface to the GUI is provided using an RS-232 serial cable.
Once the appropriate cable is connected between the CDB42448 and the host PC, load “FlexLoader.exe” from the CDB42448 directory. Once loaded, all registers are set to their default reset state. The GUI’s “File” menu provides the ability to save and load script files containing all of
the register settings. Sample script files are provided for basic functionality. Refer to section 3.1
on page 9 for details.
2.1 Advanced Register Debug Tab
The Advanced Register Debug tab provides low level control over the CS42448 and FPGA
individual register settings. Each device is displayed on a separate tab. Register values can
be modified bit-wise or byte-wise. For bit-wise, click the appropriate push button for the desired bit. For byte-wise, the desired hex value can be typed directly in the register address
box in the register map.
Figure 1. Advanced Register Tab - CS42448
DS648DB2 7
CDB42448
Figure 2. Advanced Register Tab - FPGA
8 DS648DB2
CDB42448
3. FPGA SYSTEM OVERVIEW
The FPGA (U14) controls all digital signal routing between the CS42448, CS8406 CS8416,
CS5341 and the DSP I/O Header. For easy evaluation of the TDM interface format of the
CS42448, the FPGA will copy stereo PCM data from either the CS8416 or DSP I/O Header onto
one data line at a 256Fs data rate. It will in turn de-multiplex the TDM data from the CS42448
and output stereo channel pairs to the CS8406.
3.1 FPGA Setup
Sections 3.2 to 3.4 show graphical descriptions of the routing topology internal to the FPGA.
Section 3.5 shows the graphical description of the FPGA’s control of the MCLK bus. And section 3.6 provides details for routing clocks and data, bypassing the FPGA (recommended for
more advanced users only). Refer to “FPGA Register Description” on page 16 for all configuration settings.
The board may also be configured simply by choosing from 6 pre-defined scripts provided in
the supplied CD ROM. The pre-defined scripts, along with a brief description, are shown below.
3.1.1 S/PDIF In, S/PDIF Out (SPDIF1-4)
This script sets up the CDB42448 to operate the CS8416 as the master and all other devices as slave. The CS8416 masters the MCLK bus.
Various permutations of this option exist as S/PDIF1, S/PDIF2, S/PDIF3 and S/PDIF4.
Each permutation signifies which ADC data is transmitted to the CS8406.
The CS42448 operates in the TDM digital interface format. The FPGA copies PCM data
from the CS8416 onto one data line and transmits this data to the DAC_SDIN1 input.
3.1.2 Analog In, Analog Out (Digital Loopback)
This script sets up the CDB42448 to operate the crystal oscillator as the master. The
CS8416 passes the signal from the crystal oscillator, Y1, through its OMCK input and out
its RMCK output (NOTE: the S/PDIF input must be disconnected). The CS8416 then generates sub clocks derived from the crystal oscillator and input to the FPGA for TDM clock
generation. The FPGA then masters the sub clocks to the CS42448.
The CS42448 operates in the TDM digital interface format, looping ADC_SDOUT1 back
into the DAC_SDIN1 input. ADC1-3 appear on DAC1-3 and the CS5341 ADC appears on
DAC4.
3.1.3 DSP Routing
This script sets up the CDB42448 to operate the device attached to the DSP Header as
the master and all other devices as slave. The DSP Header masters the MCLK bus.
DS648DB2 9
CDB42448
3.2. Internal Sub-Clock Routing
The graphical description below shows the internal clock routing topology between the CS42448,
CS8416, CS8406 and DSP Header. Refer to registers “CODEC Clock Control (address 03h)” on
page 18, “CS8406 Control (address 04h)” on page 19 and “CS8416 Control (address 05h)” on
page 21 for configuration settings.
CS8416
LRCK
SCLK
DSP Header
DSP.ADC_LRCK
DSP.ADC_SCLK
DSP.DAC_LRCK
DSP.DAC_SCLK
CS8406
LRCK
SCLK
CS8416 LRCK
CS8416 SCLK
DSP.ADC_LRCK
DSP.ADC_SCLK
DSP.DAC_LRCK
DSP.DAC_SCLK
M/S
FPGA->DSPADC
FPGA->DSPDAC
T2P/ADC
AUX/DAC
ADC LRCK
T2P LRCK
T2P SCLK
ADC SCLK
DAC LRCK
AUX LRCK
DAC SCLK
AUX SCLK
CS8416 LRCK
DAC LRCK
DSP.ADC_LRCK
CS8416 LRCK
ADC LRCK
DSP.DAC_LRCK
TDMer
CS42448
ADC.CLK_MUX[1:0]
FPGA->ADC
FS
DAC.CLK_MUX[1:0]
FPGA->DAC
FS
FS
256Fs
CS8416 SCLK
DAC SCLK
DSP.ADC_SCLK
256Fs SCLK
CS8416 SCLK
ADC SCLK
DSP.DAC_SCLK
256Fs SCLK
ADC_MUX[1: 0]
DAC_MUX[1:0]
FPGA->ADC
FPGA->DAC
ADC LRCK
ADC SCLK
DAC LRCK
DAC SCLK
AUX LRCK
AUX SCLK
ADC_LRCK
ADC_SCLK
DAC_LRCK
DAC_SCLK
AUX_LRCK
AUX_SCLK
Figure 3. Internal Sub-Clock Routing
10 DS648DB2
CDB42448
3.3. Internal Data Routing
The graphical description below shows the internal data routing topology between the CS42448,
CS8416, CS8406 and DSP Header. Refer to registers “CODEC SDINx Control (address 02h)”
on page 17, “CS8406 Control (address 04h)” on page 19 and “DSP Header Control (address
07h)” on page 24 for configuration settings.
CS8416
SDOUT
DSP Header
DSP.DATA_OUT1
DSP.DATA_OUT2
DSP.DATA_OUT3
DSP.DATA_OUT4
DSP_SDIN1
DSP_SDIN2
DSP_SDIN3
CS8406
SDIN
SDOUT1
SDOUT2
SDOUT3
DATA_MUX[2:0]
ADC1
ADC2
ADC3
AUX
ADC1,2,3, AUX
TDMer
TDM Stream
CS8416 SDOUT
DSP OUT1
SDOUT1
TDM Stream
CS8416 SDOUT
DSP OUT1
DSP OUT2
SDOUT2
CS8416 SDOUT
DSP OUT1
DSP OUT3
SDOUT3
CS8416 SDOUT
DSP OUT1
DSP OUT4
SDOUT1
SDIN1_MUX[1:0]
DSPDATA->DAC
SDIN2_MUX[1:0]
SDIN3_MUX[1:0]
SDIN4_MUX[1:0]
SDIN1
SDIN2
SDIN3
SDIN4
CS8416 SDOUT
CS42448
SDIN1
SDIN2
SDIN3
SDIN4
SDOUT1
SDOUT2
SDOUT3
AUX_SDIN
MUX[2:0]
Figure 4. Internal Data Routing
DS648DB2 11
CDB42448
3.4. Internal TDM Conversion, MUXing and Control (TDMer)
The graphical description below shows the routing topology of the TDM converter between the
CS42448, CS8416, CS8406 and DSP Header. Refer to register “TDM Conversion (address
01h)” on page 16 for configuration settings.
The TDMer allows the user to easily evaluate the CS42448 in the TDM digital interface format.
A 256Fs clock and an FS pulse is derived from either the CS8416 or DSP Header. Data is multiplexed onto one data line and transmitted to the DAC. Likewise, data from the ADC of the
CS42448 is de-multiplexed and transmitted to the CS8406. The CS8406 sub clocks, in this case,
must be taken from the TDM2PCM engine of the TDMer (refer to register “ADC or TDM2PCM
Clock Selection (T2P/ADC)” on page 20 for implementation).
The TDMer is also capable of transmitting the de-multiplexed data to the DSP Header; however,
the user must re-time this data using a DSP. The CDB42448 does not provide an option for routing the TDM2PCM clocks to the DSP Header.
TDMer
CS42448
CS8416
LRCK
SCLK
DSP.ADC_LRCK
CS8416_LRCK
CS8416_SCLK
DSP.ADC_SCLK
DSP/CS8416
PCM2TDM
Clocks
256Fs SCLK
FS
ADC/DAC_SCLK
ADC/DAC_LRCK
SDOUT
CS8416_SDOUT
DSP Header
DSP.ADC_LRCK
DSP.ADC_SCLK
DSP.SDOUT1
DSP.SDOUT2
DSP.SDOUT3
DSP.SDOUT4
DSP OUT1
DSP OUT2
DSP OUT3
DSP OUT4
OUT1/OUT2
OUT1/OUT3
OUT1/OUT4
CS8406
LRCK
SCLK
SDIN
T2P_LRCK
T2P_SCLK
ADC.SDOUT_MUX
D_MUX[2:0]
ADC1
ADC2
ADC3
AUX
SDOUT1
SDOUT2
SDOUT3
= Other logic prior to input/output pin of FPGA not shown.
Data
SLOT1
SLOT2
SLOT3
SLOT4
MCLK
TDM2PCM
Clocks
Data
Figure 5. TDMer
TDM Stream
SDIN1
SDOUT1
12 DS648DB2
CDB42448
3.5 External MCLK Control
Several sources for MCLK exist on the CDB42448. The crystal oscillator, Y1, will master the
MCLK bus when no S/PDIF signal is input to the CS8416 (refer to the CS8416 data sheet for
details on OMCK operation). This signal will be driven directly out the CS8416.
The CS8416 will generate a master clock whenever its internal PLL is locked to the incoming
S/PDIF stream. This MCLK signal from the CS8416 can be taken off the MCLK bus by setting
the “RMCK_Master” bit in the register “CS8416 Control (address 05h)” on page 21.
The DSP Header can master or slave the MCLK bus by setting the “MCLK_M/S” bit in the
register “DSP Header Control (address 07h)” on page 24 accordingly.
3.5.1 CS5341 MCLK
To accommodate an MCLK signal greater than 25 MHz on the MCLK bus, a 2.0 divider
internal to the FPGA has been implemented. The divided MCLK signal is routed only to
the CS5341. Refer to register “CS5341 and Miscellaneous Control (Address 08h)” on
page 26 for the required setting.
3.5.2 TDMer MCLK
MCLK signals greater than 256Fs must be divided accordingly to maintain a 256Fs MCLK
signal into the TDMer. A 1.5 and a 2.0 divider has been implemented inside the FPGA.
Refer to register “CS5341 and Miscellaneous Control (Address 08h)” on page 26 for the
required setting.
OSC
CS8416
OMCK
CS8406
DSP Header
RMCK
OMCK
MCLK
RMCK_Master
Reg 05h[0]
Divider
Divider
MCLK_M/S
Reg 07h[0]
FPGA
Reg 08h[6:5]
TDMer
Reg 08h[3:2]
CS42448
MCLK
CS5341
MCLK
Figure 6. External MCLK Control
DS648DB2 13
CDB42448
3.6 Bypass Control - Advanced
The DSP clocks and data may be routed through buffers directly to the CS42448, bypassing
the FPGA. This configuration may be desired for more stringent timing requirements at higher
clock speeds. See register “Bypass Control (address 06h)” on page 22. These bits are only
accessible through the Advanced tab of the Cirrus Logic FlexGui software.
NOTE: To avoid contention with the FPGA, set the clock direction for the FPGA appropriately: The FPGA->DAC
and FPGA->ADC bits in register 03h and 07h must be set to ‘1’b.
FPGA – Bypass Control
Register 06h
DSPDATA->DAC
SDOUT->DSP
NOTE: FPGA->ADC/
DACb bits in Reg 03h
must be disabled to avoid
bus contention.
NOTE: FPGA->DSPb bits in
Reg 07h must be disabled
to avoid bus contention.
DAC->DSP
DSP->DAC
ADC->DSP
DSP->ADC
DSP Header
DSP_ADC.LRCK/
DSP_DAC.LRCK/
SCLK
SCLK
DSP.SDOUT1-4
DSP.SDIN1-3
Figure 7. Bypass FPGA Control
CS42448
ADC.LRCK
/SCLK
DAC.LRCK
/SCLK
SDIN1-4
SDOUT1-3
14 DS648DB2
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