Cirrus Logic CDB4244 User Manual
CS4244 Evaluation Board
CS4244
S/PDIF Input
(CS8416)
S/PDIF Output
(CS8406)
Clock Synthesis
(CS2000)
Osc. Crystal
DSP Header
Control
Header
USB Control
Port
Analog Inputs
- Active Single Ended to
Differential
- Passive Differential
Analog Outputs
- Passive Single Ended
& Differential
- Active Single Ended &
Differential
- Active Differential to
Single Ended
CDB4244
Features
Multiple Analog Input Filter Options
– Active Single Ended to Differential
– Passive Differential
Multiple Analog Output Filter Options
– Passive Single Ended & Differential
– Active Single Ended & Differential
– Active Differential to Single Ended
Versatile S/PDIF Interface
– CS8416 Digital Audio Receiver
– CS8406 Digital Audio Transmitter
– CS2000 Clock Synthesizer
External Connection Headers
– Control Port Accessibility
– DSP Serial Audio I/O Accessibility
Windows
– Allows Easy Configuration of the CDB4244
– Predefined & User-Configurable Scripts
®
Compatible FlexGUI S/W Control
Description
The CDB4244 evaluation board is an excellent platform
designed to facilitate evaluation of the CS4244 multichannel CODEC. Use of the board requires an analog/digital signal source, an audio analyzer, and power
supplies. A Windows
needed in order to configure the board.
System timing for the I²S and Left-Justified serial interface formats can be accomplished using S/PDIF I/O or
crystal-based timing hardware on the CDB42 44. An e xternal DSP interface header supports I²S, Left-Justified,
and TDM serial interface formats.
1/8” audio jacks, three-pin headers, and RCA phono
jacks are provided for the CS4244 analog I/O connections. Digital I/O connections are accomplished through
RCA phono jacks or optical connectors leading to the
S/PDIF receiver and transmitter.
The Windows-based software available online makes
configuring the CDB4244 easy. The software communicates through the PC’s USB port to control the
CS4244, the S/PDIF receiver and transmitter, and the
clock synthesizer. These devices can also be controlled through an external control header for easy insystem evaluation.
ORDERING INFORMATION
CDB4244 Evaluation Board
PC-compatible computer is also
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
MAR '11
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TABLE OF CONTENTS
1 SYSTEM OVERVIEW ..............................................................................................................................4
1.1 Power ...............................................................................................................................................4
1.2 Grounding and Power Supply Decoupling ....................................................................................... 4
1.3 CS4244 Multi-Channel CODEC ....................................................................................................... 4
1.4 CS8406 Digital Audio Transmitter ....................................................................................................4
1.5 CS8416 Digital Audio Receiver ........................................................................................................5
1.6 CS2000 Fractional-N Clock Synthesizer & Clock Multiplier ............................................................. 5
1.7 Oscillator .......................................................................................................................................... 5
1.8 External Connection Headers ..........................................................................................................5
1.9 Analog Inputs ................................................................................................................................... 6
1.10 Analog Outputs ......................................... ... ..................................................................................6
2 SOFTWARE MODE CONTROL ............... ... ... .... ... ... ... .... ........................................................................ 7
2.1 Board Control Tab ............................................................................................................................8
2.2 CODEC Control Tab ........................................................................................................................9
2.3 Volume Control Tab .......................................................................................................................10
2.4 Register Maps Tab ......................................................................................................................... 11
2.5 Predefined Sample Scripts ............................................................................................................ 12
3 MASTER CLOCK CONFIGURATION ...................................................................................................13
3.1 CS8416 Recovered Master Clock ..................................................................................................13
3.2 CS2000-Generated Master Clock .................................................................................................. 14
3.3 CS2000 Timing Reference .............................................................................................................14
3.4 Miscellaneous Options ................................................................................................................... 14
4 ANALOG INPUT FILTERS .................................................................................................................... 15
4.1 Active Single-Ended-to-Differential Input Filter .............................................................................. 15
4.2 Passive Differential Input Filter ...................................................................................................... 15
4.3 Analog Input Filter Configuration ................................................................................................... 16
5 ANALOG OUTPUT FILTERS ................................................................................................................ 17
5.1 Analog Output Filter Considerations ..............................................................................................17
5.2 Analog Output Filter Configuration .................................................................................................19
6 SYSTEM CONNECTIONS AND JUMPER PIN BLOCKS ..................................................................... 20
6.1 System Connections ...................................................................................................................... 20
6.2 Jumper Pin Blocks .........................................................................................................................21
6.3 Test Points ..................................................................................................................................... 21
7 CDB4244 BLOCK DIAGRAM ...............................................................................................................22
8 CDB4244 SCHEMATIC ......................................................................................................................... 23
9 CDB4244 LAYOUT ................................................................................................................................ 31
10 REVISION HISTORY ........................ ... ... ... ... .................................................................... ...................36
CDB4244
LIST OF FIGURES
Figure 1.Board Control Tab ............................. ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ........................................ 8
Figure 2.CODEC Control Tab ................................... ... ... .... ... ... ... .... ... ... ... ... ............................................... 9
Figure 3.Volume Control Tab ................................. ... ... ... .......................................................................... 10
Figure 4.Register Maps Tab ............................ ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ......................................... 11
Figure 5.Master Clock Path ....................... ... ... ... .... ... ... ... ..........................................................................13
Figure 6.Active Single-Ended-to-Differential Input Filter Block Diagram ................ ... .... ... ... ... ...................15
Figure 7.Passive Differential Input Filter Block Diagram ........ .......................................... ......................... 15
Figure 8.Analog Output Filter Block Diagram ............................................................................................17
Figure 9.CDB4244 Block Diagram .................................. .... ... ... ... .... ... ... ... ... .... ... ... ... ................................ 22
Figure 10.CS4244 (Schematic Sheet 1) ................ ... ... ... .... ... ................................................................... 23
Figure 11.S/PDIF I/O (Schematic Sheet 2) ...............................................................................................24
Figure 12.USB I/O (Schematic Sheet 3) ...................................................................................................25
Figure 13.Analog Input Channels 1 & 2 (Schematic Sheet 4) ................................................................... 26
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Figure 14.Analog Input Channels 3 & 4 (Schematic Sheet 5) ................................................................... 27
Figure 15.Analog Output Channels 1 & 2 (Schematic Sheet 6) ................................................................28
Figure 16.Analog Output Channels 3 & 4 (Schematic Sheet 7) ................................................................29
Figure 17.Power (Schematic Sheet 8) ......................................................................................................30
Figure 18.Silk Screen ................................................................................................................................31
Figure 19.Top Side (Layer 1) ....................................................................................................................32
Figure 20.Ground Plane (Layer 2) ............... ... ... .... ... ... .............................................................................33
Figure 21.Power Plane (Layer 3) ..............................................................................................................34
Figure 22.Bottom Side (Layer 4) ............................................................................................................... 35
LIST OF TABLES
Table 1. Analog Input Filter Components ..................................................................................................16
Table 2. Analog Output Filter Components .. ... ... ....................................................................... .... ... .........19
Table 3. System Connections ...................................................................................................................20
Table 4. Jumper Pin Blocks ...... ... ... ... .... ... ... ... .................................................................... ......................21
CDB4244
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1 SYSTEM OVERVIEW
CDB4244
The CDB4244 platform provides analog and digital interfac es to the CS4244 and allows for external DSP and I²C
control. Board configuration can be done using the Windows PC-compatible graphical user interface (GUI) to read
and write device registers. Multiple analog input and output filter configurations are supported, as well are several
different options for generating a system master clock.
The CDB4244 schematic set has been partitioned into eight pages and is shown in Section 8 starting on page 23.
Additionally, Section 6 on page 20 provides a description of all external connectors, including the default factory settings for all jumpers.
TM
1.1 Power
Power is supplied to the board through an external regulated +5-V supply or a PC USB port. The CS4244
analog supply (referred to as VA) may be taken from the selected +5-V supply or an onboard +3.3-V regulator. Table 4 on page 21 explains how to configure each option. A dual-rail ±12-V regulated supply is required to power the active filter network used for each analog input channel. A special resistor option allows
the optional active analog output filter configurations to use either a single-rail or dual-rail power supply.
Shunt jumpers and 1%, 1-Ω parallel resistors provide a convenient way to measure both the VA and VL
supply currents to the CS4244. The current is easily calculated by measuring the vol tage drop across each
resistor with its associated shunt removed. The shunts connected in parallel with these resistors must be in
place during normal operation.
WARNING: Please refer to the CS4244 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS4244 requires careful attention to power supply and grounding arrangements to optimize performance. The CDB4244 demonstrates these optimal arrangements. Figur e 18 on page 31 shows the component placement; Figure 19 on page 32 shows the top-side layout and Figure 22 on page 35 shows the
bottom-side layout. Power supply decoupling capacitors are located as close as possible to the CS4244.
Extensive use of ground plane fill helps reduce radiated noise.
1.3 CS4244 Multi-Channel CODEC
A complete description of the CS4244 (Figure 10 on page 23) can b e found in the CS42 44 da ta shee t. The
CS4244 is configured using the Cirrus Logic FlexGUI software. The device configuration registers are accessible via the “Register Maps” tab of the software. This tab provides low-level control of each bit in the
device’s control port. The “CODEC Control” and “Volume Control” tabs p rovide high- level co ntrol of the d evice for faster configuration. See Section 2 on page 7 for details.
1.4 CS8406 Digital Audio Transmitter
The CS8406 S/PDIF transmitter (Figure 11 on page 2 4) converts the digital audio generated by th e CS4244
(I²S or Left-Justified serial interface formats) to the standard S/PDIF data stream and routes these signals
to the optical and RCA connectors on the CDB4244. With a supplied master clock, the CS8406 can master
the serial audio interface timing for the CDB4244.
The CS8406 can be controlled using the Cirrus Logic FlexGUI software under the “Board Control” tab. See
Section 2.1 on page 8 for details. A complete description of the CS8406 and a discussion of the digi tal audio
interface can be found in the CS8406 data sheet.
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1.5 CS8416 Digital Audio Receiver
The CS8416 S/PDIF receiver (Figure 11 on page 24) converts the incoming S/PDIF data stream from the
optical or RCA connectors into digital audio (I²S or Left-Justified serial interface formats) and passes it to
the CS4244. Using the master clock recovered from the incoming S/PDIF stream or the clock provided by
the socketed onboard oscillator, the CS8416 can master the serial audio interface timing for the CDB4244.
The CS8416 can be controlled using the Cirrus Logic Fl exGUI software under the “Board Control” tab. See
Section 2.1 on page 8 for details. A complete description of the CS8416 and a discussion of the digital audio
interface can be found in the CS8416 data sheet.
1.6 CS2000 Fractional-N Clock Synthesizer & Clock Multiplier
The CS2000 clock synthesize r (Figure 11 on page 24) provides a low-jitter master clock source for the
CS4244 and CS8406, and is capable of generating th e necessary master clock frequen cies to provide multiple sample rates without having to make hardware changes to the board. The Cirrus Logic FlexGUI software can be used to easily realize many of the clocking options available for the CDB4244.
Refer to Section 3 on page 13 for a detailed expla nation of how the CS2000 can be used wi th the CDB4244.
A complete description of the CS2000 can be found in the CS2000 data sheet.
1.7 Oscillator
The socketed onboard oscillator (Figure 11 on page 24) can serve as the master clock for the CDB4244
when the CS8416 can no longer recover a master clock from the incoming S/PDIF stream. Refer to Section
3.1 on page 13 for more information. The oscillator is mounted in pin sockets, allowing easy removal or re-
placement. The CDB4244 can accommodate +5-V half-can oscillators.
CDB4244
1.8 External Connection Headers
The CDB4244 has been de signed to allow connections to and from an external system through a DSP
header (J2 in Figure 10 on page 23) and a control port header (J1 in Figure 10 on p age 23). The DSP header
provides access to the serial audio signals required to interface with an external system. The control port
header provides bidirectional access to the I²C control port signals. Two unp opulated pull-up resistors (R165
and R166) are also available in the event that the external host does not have pull-up resistors on its I²C
lines.
These headers are accessed by removing the jumpers from the “Jumper for Bd Control” positio n labeled on
the board. The user may then connect a ribbon cable connector to the “Ext Control Connection” pins for
external control of the CDB4244. A single row of “GND” pins are provided to maintain signal ground integrity.
If the headers are not in use, the jumpers must be in place for each row of J1 and J2 in the “Jumper for Bd
Control” position. In this configuration, the CDB4244 assumes full control of the CS4244, with access
through the PC USB connection.
Note that the CS4244 INT
have a pull-up resistor to pull the interrupt signal high once it is deasserted by the CS4244. Instead, the interrupt signal is pulled high by a pull-up resisto r internal to the onboard microcontroller. If the CDB4244 is
controlled externally (through the use of J1), the external system must be able to pull the interrupt signal
high if the CS4244 INT
configured as active high or active low, avoiding the need for a pull-up resistor in this case. Refer to the
CS4244 data sheet for more information.
To pass digital audio data from the ADCs of the CS4244 directly to the DACs in order to evaluate analogin-to-analog-out performance, remove the jumpers from the SDOUT1, SDIN1, SDOUT2, and SDIN2 rows
of the DSP header (J2). Then jumper SDOUT1 to SDIN1, an d SDOUT 2 to SDIN2 using the mid dle colum n
of the DSP header.
pin defaults to an active-low, open-drain interrupt output. Th e CDB4244 does not
pin remains in its default open-drain configuration. Alternatively, the INT pin may be
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1.9 Analog Inputs
The CDB4244 can accept single-ended analog input signals through the RCA phono jacks on each channel.
An active single-ended-to-different ial input filter network converts the single-ended input into a differential
signal before the signal is passed to the respective differential analog inputs of the CS4244.
Space for a passive differential filter option allows differential analog input signals to be connected directly
to the CDB4244. Stereo 1/8” audio jacks are provided to support this option; however, the components used
to populate this filter option must be obt ained separa tely. With either filter option, analog input signals are
AC-coupled to the CS4244.
Refer to Section 4 starting on page 15 for details on the implementation of either input filter.
1.10 Analog Outputs
The CDB4244 provides differential analog outputs through the stereo 1/8 ” audio jacks on each output channel. While a passive filter network is populated on each output channel by default, each channel has space
for an optional active differential filter network.
Both the active and passive differential filter options can be converted to provide single-ended outputs by
removing certain components from the board. A fifth filter option provides space for an active differential-tosingle-ended filter, which can convert the differentia l analog outputs of the CS4 244 into a single- ended signal. RCA phono jacks are provided to support these options. The components used to populate any of the
three active output filter options available for each channel must be obtained separately.
CDB4244
Refer to Section 5 starting on page 17 for details on the implementation of each output filter.
6 DS900DB2
CDB4244
2 SOFTWARE MODE CONTROL
The CDB4244 can be used with the Microsoft Windows®–based FlexGUI graphical user interface, allowing software
control of the CS4244, CS8416, CS8406, and CS2000 registers. The latest control software can be downloaded
from www.cirrus.com/msasoftware. Step-by-step instructions for setting up the FlexGUI with the CDB4244 configured under the factory default settings are provided as follows:
1. Download and install the FlexGUI software as instructed on the Cirrus Logic website.
2. Connect a triple-output power supply to the binding posts marked “+5 V EXT, GND, -12 V, and +12 V.”
3. Connect the CDB4244 to the host PC using a USB cable.
4. Launch the Cirrus Logic FlexGUI. Once the GUI is launched successfully, all CS4244 registers are set to
their default reset state, with the remaining devices preconfigured as necessary.
5. Refresh the GUI by clicking on the “Update” button. The state of all registers is now visible.
For standard setup:
1. Set up the board’s clocking and data options in the “Board Control” tab as desired.
2. Set up the CS4244 in the “CODEC Control” and “Volume Control” tabs as desired.
3. Begin evaluating the CS4244.
For quick setup, the CDB4244 may, alternatively, be configured by loading a predefined sample script file:
1. On the File menu, click "Restore Board Registers..."
2. Br ows e to the “Bo ard s\CDB4244\Scripts” directory.
3. Choose any one of the provided scripts to begin evaluation.
To create custom script files:
1. O n the File menu , click "Sa ve Boar d Reg ist er s.. ."
2. Enter any name that sufficiently describes the current setup.
3. Choose the desired location, and save the script.
4. To load this script at a later time, follow the instructions above for loading a predefined sample s crip t.
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2.1 Board Control Tab
The “Board Control” tab provides high-level contr ol of the clocking and data options within the CDB4244. A
description of each control group is outlined below.
CS8416 S/PDIF Receiver—Configures the serial interface format of the S/PDIF receiver and indicate s how
the receiver is connected to the external transmitter (coaxial or optical).
CS8406 S/PDIF Transmitter—Configures the serial interface format of the S/PDIF transmitter and selects
which data channel is passed to the outgoing S/PDIF stream: SDOUT1 (ADC1 and ADC2 ) or SDOUT2
(ADC3 and ADC4).
CS2000 Clock Synthesizer—Selects the master clock that is presented to the CS4244 and CS8406. Refer
to Section 3 on page 13 for more information.
Update—Reads the registers of each device within the CDB4244 an d reflects the current values in the GUI.
CDB4244
Figure 1. Board Control Tab
Note: Refer to the CS4244 data sheet for information on how to configure the device’s clocking options
in order to satisfy the device’s recommended power up and power down sequence.
8 DS900DB2
2.2 CODEC Control Tab
The “CODEC Control” tab provides high-level control of many CS4244 register settings. Status text detailing
the CODEC’s specific configuration is shown as part of certain controls. The text shown depends on the
setting of the associated control. Note that the Update button (described below) must be pressed to show
the current status of the CS4244 registers represented in this tab. A description of each control group is
outlined below. See the CS4244 data sheet for complete register descriptions.
Serial Port Configuration—Configures the CS4244’s serial port and provides controls for r ela ted inter rupts.
Note that changes to these settings durin g nor mal oper ation may violate the de vice’s recommende d power
up or power down sequence; refer to the CS4244 data sheet for more information.
Power—Provides a means to power up or power down each ADC and DAC of the CS4244. Note that it is
the user’s responsibility to ensure that the “VA Selection” control correctly reflects the VA supply level.
Miscellaneous Controls—Configures interrupt behavior and various ADC options, as well as selects the
CS4244’s I²C address.
TDM Options—Configures the CS4244’s serial port when operating in the TDM interface format. Note that
the CS4244 cannot operate in TDM mode using the CDB4244 alone; instead the CS4244 must be controlled externally to exercise the device’s TDM capabilities. Refer to Section 1.8 on page 5 for more information on how to release the CS4244 from the board’s command and control it with an external device.
Update—Reads all registers in the CS4244 and reflects the current values in the GUI.
CDB4244
Reset—Resets the CS4244.
Figure 2. CODEC Control Tab
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2.3 Volume Control Tab
The “Volume Control” tab provides high-le vel cont rol of all volu me-re late d settings for each ADC and DAC
of the CS4244. Status text detailing the CODEC’s specific configuration is shown as part of certain controls.
The text shown depends on the setting of the associated control. Note that the Update button (described
below) must be pressed to show the current status of the CS4244 registers represented in this tab. A description of each control group is outlined below. See the CS4244 data sheet for complete registe r descriptions.
ADC—Provides controls to mute or invert the output of each ADC and to control ADC overflow interrupts.
DAC—Provides volume, muting, and inversion controls for each DAC, as well as a master volume control.
Fine volume control can be performed by clicking on the associated volume slider and using the arrow keys.
This group also controls DAC volume changes, as well as DAC clipping interrupts.
Update—Reads all registers in the CS4244 and reflects the current values in the GUI.
Reset—Resets the CS4244.
CDB4244
Figure 3. Volume Control Tab
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2.4 Register Maps Tab
The “Register Maps” tab provides low-level control over the register-level se ttings of the CS4244, CS84 16,
CS8406, CS2000, and microcontroller GPIO. Each device is displayed on a separate tab. Register values
can be modified bitwise or bytewise. For bitwise control, click the appropriate push button for the desired
bit. For bytewise control, the desired hexadecimal value can be type d dir ectly into the reg iste r addr ess box
within the register map.
CDB4244
Figure 4. Register Maps Tab
Certain device tabs provide a means to reset the selected device throug h the use of the “Reset Device” button. The “Released Reset/Hold In Reset” butto n provid es manu al control of the selected device’s r eset pin,
if applicable. The “Reset All” button resets the CDB4244.
The “Update Device” button reads all registers of the selected device and updates the register map accordingly. Highlighting a specific register and clicking the “Update Register” button reads only the selected register and refreshes its display in the register map.
DS900DB2 11
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