Cirrus Logic AN89 User Manual

Application Note

Interfacing the CS5525/6/9 to the 68HC05

By Keith Coffey

AN89

INTRODUCTION

This applica tion note details the interfac e of Crys-

tal Semiconductor’s CS5525/6/9 Analog-to-Digital Converter (ADC) to a Motorola 68HC05 microcontroller. This note takes the reader through a simple e xamp le de scribi ng how to co mmun icate with the ADC. Al l algor ithms di scussed are included in the Appendix at the end of this note.

ADC DIGITAL INTERFACE

The CS5525/6/9 interface s to the 68HC05 t hrough either a thre e-wir e or a four-wir e inte rface. Figure 1 depicts the interface between the two devices. Though this software was written to interface to the

SPI

modified to w ork in the four-wire format.

on the 68HC05, the algorithms can be easily

The ADC’s serial port consists of four control lines: CS

, SCLK, SDI, and SDO.

, Chip S elect, is the contro l line w hich e nables

access to the serial port. SCLK, Serial Clock, is the bit-clock which controls

the shifting of data to or from the ADC’s serial port.

SDI, Serial Data In, is the data signal used to transfer data from the 68HC05 to the ADC.

SDO, Serial Data Out, is the data signal used to transfer outpu t da ta from the ADC to the 68HC 05.

SOFTWARE DESCRIPTION

This note presents algorithms to initialize the 68HC05 and the CS5525/6/9, perform a self-offset calibration, modify the CS5525/6/9’s gain register, and acquir e a c onversi on. Fi gure 2 depi cts a block

CS5525/6/9 68HC05

SDI

SDO

SCLK

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

No Connect MOSI (PD3) MISO (PD2)

SCK(PD4)

Figure 1. 3-Wire and 4-Wire Interfaces

CS5525/6/9 68HC05

SDI

SDO

SCLK

(All Rights Reserv ed)

PA0 MOSI (PD3) MISO (PD2)

SCK (PD4)

NOV ‘97

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diagram. While reading this application note, please refer to the Appendix for the code listing.

Initialize

Initialize is a subrout in e tha t con fig ures th e SPI

on the 68HC05 and pl aces the CS5525/6/9 in the command-state. Figure 1 d epi cts how the interface is configured (for more information on configuring

the SPI

tion Guide) . Afte r confi gurin g t he SP I

refer to Moto rol a’s M68HC 05 Applic a-

, the con troller enters a delay state to allow time for the CS5525/6/9’s power-on-reset and oscillator to start-up (oscillator start-up time is typically 500 mS). The last step is to reinitialize the serial port on the ADC (r einitializing t he serial port is unnecessary here, the code was added for demonstration purposes only). This is implemented by sending the converter sixteen bytes of logic 1’s followed by one final byte, with its LSB at logic 0. Once sent, the sequence plac es the serial port of the ADC int o the command-state, where it aw aits a valid co mman d .

After returning to main, the software demo nstrates how to calibra te the convert er’s offset.

START

INITIALIZE

MICROCONTROLLER & CS5525/6/9

SELF-OFFSET CAL.

Self-Offset Calibratio n

Calibrate is a subroutine that calibrates the converter’s offset. Calibrate first sends 0x000001 (Hex) to the conf iguration register. This i nstructs the converter to perform a self-offset calibration. Then the Done Flag (D F) bit in th e configuration register i s polled until set. Onc e DF is set, it indicates that a val id c al ibration is perform ed. To minimize digi tal n oise (whil e perf ormin g a cal ibrat ion or a conversio n), m any syste m d esigners m ay f ind it advantage ous to add a software delay e qui va lent to a convers ion or calib ration cy cle before po lling the DF bit.

Read/Write Gain Register

To modify the gain register the command-byte and data-byte variables are first initialized. This is accomplis hed with the LDA and S TA opcode s. The subroutine write_register u ses t hese va riables to set the conte nts of the gain re gister in the C S552 5/ 6/9 to 0x800000 (HEX). To do this, write_register calls send_spi four tim es (once fo r the command - byte and three additional times for the 24 bits of data). Send_spi is a subroutine used to transfer a byte of informatio n fro m th e 68HC0 5 t o the CS5525/ 6/

9 via the SPI

. A byte is transferred on e bit at a time, MSB (most significant bit) fi rst. Figure 3 depicts the timi ng diagram for the write-cy cle in the CS5525/6/9’s serial port. This algorithm demonstrates how to write to the gai n register. It does not perform a ga in calibrati on. T o perform a gain calibration, follo w the procedu res outlined in th e data sheet.

To verify if 0x800000(HEX) was written to the

MODIFY GAIN

gain register, read_register is call ed. It dup licates the read-cycle timing diagram depicted in Figure 4. Read_register calls send_spi once to transfer the command-byt e to the CS5525/ 6/9. This place s the

ACQUIRE CONVERSION

converter into the data-state where it waits until data is read from its serial port. Read_reg ister calls

Figure 2. CS5525/6/9 Software Flowchart

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receive_spi three times and tra ns f ers three bytes o f

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information from the CS5525/6/9 to the 68HC05

via the SPI

. Similar to send_spi, receive_spi receives a byte one bit at a time MSB first. When the transfer is complete , highbyte, midbyte, and low-

byte byte contain the CS5525/6/9’s 24-bit gain register.

Acquire Conversion

To acquire a c onversion the subroutine convert is called. Convert se nds the command-byte 0x0 C to the converter instructing it to perform a single conversion. Th en the Done Flag bit in th e configuration registe r is polle d. When D F is set , it indica tes

that a conversion was performed. The 68HC05 then reads the conversion data register to acquire the conversion. Figu re 6 dep ic ts ho w 16-bit and 20-bit conversion words are stored in the 68HC05.

An alternate m ethod ca n be used to acquire a conversion. By se tting the Port Flag bit (PF, the fifth bit in the configuration register), SDO’s function is modified to fall to logic 0 when a conversion is complete (refer to Fi gure 5). By tying SDO t o the controller’s interrupt pin, conversions can be acquired via an interrupt service routine.

Figure 3. Write-Cycle Timing

Figure 4. Read-Cycle Timing

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SCLK

SDI

ommand Time

8SCLKs

td = XIN/O WR clock cycles for e ach conversion except t he

first conversion whichwilltakeXIN/OWR+ 7 clockcycles

Figure 5. Conversion/Acquisition Cycle with the PF Bit Asserted

.MSB High-Byte

D19 D18 D17 D16 D15 D14 D13 D12

Mid-Byte

D11 D10 D9 D8 D7 D6 D5 D4

Low-Byte

D3 D2 D1 D0 0 0 OD OF

A) 20-Bit Conversion Data Word

MSB High-Byte

D15 D14 D13 D12 D11 D10 D9 D8

Mid-Byte

D7 D6 D5 D4 D3 D2 D1 D0

Low-Byte

111100ODOF

B) 16-Bit Conversion Data Word

0- always zero, 1

OD - Oscillation Detect, OF - Overflow

Figure 6. Bit Representation/Storage in 68HC05

- always one,

SCLKs Clear SDO Flag

Data SDO Continuous Conversi on Read (PF bit = 1)

MAXIMUM SCLK RATE

A machine cy c le in the 68HC05 consists 2 oscill a-

tor periods or 500 ns if t h e m i crocontrolle r’s osc il lator freq uency i s 4 MHz. Since t he CS 5525/6/9 ’s maximum SCLK rate i s 2MHz, addi ti onal no ope ration (NOP) delays may be necessary to reduce the

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IN/OWR

Clock Cycles

ataTime

D 24 SCLKs

transfer rate if the mic rocon troller system re quires higher rate oscillators.

CONCLUSION

This applicat ion note pre sents an exam ple of how to interface the CS5525/6/9 to the 68HC05. It is divided into tw o main sections: hardware and software. The hardware section illustrates both a threewire and a f our-wire interfac e. The three-wi re in-

terface is SPI

and MICROWIR E The software section il lustrate s how to initia lize the converter and microcontroller, calibrate the converters offset, write to and read from the ADC’s internal register, and acquire a conversion. The software is modularized and illustrates important subroutines, e .g. wr ite_ regi ste r and read _register. The software desc ribed in this note is included in the Appendix at the end of t his document.

SPI MICROWIRE

is a trademark of Motorola.

is a tradem ark of Nati onal Sem i-

conductor.

compatible.

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