Cirrus Logic AN372 User Manual

AN372

Application Note

Design Guide for a CS1612 and CS1613

Dimmer-compatible SSL Circuit

1 Overview of the CS1612/13

The CS1612 and CS1613 are digital control ICs engineered to deliver a high-efficiency, cost-effective, flicker-free, phase-dimmable, solid-state lighting (SSL) solution for the incandescent lamp-replacement market. The CS1612/13 is designed to control a quasi-resonant buck topology. The CS1612 and CS1613 are designed for 120VAC and 230VAC line voltage applications, respectively.

The CS1612/13 integrates a critical conduction mode (CRM) boost converter that provides power factor correction and dimmer compatibility with a constant output current, quasi-resonant buck stage. An adaptive dimmer compatibility algorithm controls the boost stage and dimmer compatibility operation mode to enable flicker-free operation to 2% output current with leading-edge, trailing-edge, and digital dimmers (dimmers with an integrated power supply).

1.1 Features

• Best-in-class Dimmer Compatibility

- Leading-edge (TRIAC) Dimmers

- Trailing-edge Dimmers

- Digital Dimmers (with Integrated Power Supply)

• Up to 90% Efficiency

• Flicker-free Dimming

• 0% Minimum Dimming Level

• Quasi-resonant Buck Stage with Constant-current Output

- Buck for 1612/ 13

• Fast Startup

• Tight LED Current Regulation: Better than ±5%

• Primary-side Regulation (PSR)

• >0.9 Power Factor

• IEC-61000-3-2 Compliant

• Soft Start

• Protections:

- Output Open/Short

- Current-sense Resistor Open /Short

- External Overtemperature Using NTC

Cirrus Logic, Inc.

http://www.cirrus.com

AUG’12

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Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL Core, the EXL Core logo design, TruDim, and the TruDim logo design are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

IMPORTANT SAFETY INSTRUCTIONS

Read and follow all safety instructions prior to using this demonstration board.

This Engineering Evaluation Unit or Demonstration Board must only be used for assessing IC performance in a laboratory setting. This product is not intended for any other use or incorporation into products for sale.

This product must only be used by qualified technicians or professionals who are trained in the safety procedures associated with the use of demonstration boards.

Risk of Electric Shock

• The direct connection to the AC power line and the open and unprotected boards present a serious risk of electric shock and can cause serious injury or death. Extreme caution needs to be exercised while handling this board.

• Avoid contact with the exposed conductor or terminals of components on the board. High voltage is present on exposed conductor and it may be present on terminals of any components directly or indirectly connected to the AC line.

• Dangerous voltages and/or currents may be internally generated and accessible at various points across the board.

• Charged capacitors store high voltage, even after the circuit has been disconnected from the AC line.

• Make sure that the power source is off before wiring any connection. Make sure that all connectors are well

connected before the power source is on.

• Follow all laboratory safety procedures established by your employer and relevant safety regulations and guidelines, such as the ones listed under, OSHA General Industry Regulations - Subpart S and NFPA 70E.

Suitable eye protection must be worn when working with or around demonstration boards. Always

comply with your employer’s policies regarding the use of personal protective equipment.

All components and metallic parts may be extremely hot to touch when electrically active.

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2 Introduction

This application note provides a guide to designing a Solid State Lighting (SSL) LED lamp circuit using Cirrus Logic's CS1612/13. The first half of the document presents a step-by-step design procedure for calculating the required components for each stage of the system. The second half of the document supports the design effort by showing an example of a CS1613 design. See the CS1610/11/12/13 TRIAC Dimmable LED Driver IC data sheet for more details about the CS1612/13 IC.

2.1 Definition of Symbols

Symbol Description

TT Switching period

T1 Buck FET Q4 ‘ON’ time

T2 Catch diode D3 conduction time

T3 Time when the FET and diode are ‘OFF’



Reflected

CLAMP

PK(FB)

FBGAIN

Sense

PK(BST)

L Inductance as measured across the entire buck inductor L4 winding (N+1 turns)

BST

N Buck inductor normalized turns ratio

OUT

 Power stage efficiency

Switching frequency

Duty ratio (T1/TT)

Voltage across the N winding of inductor L4 during T2

Maximum voltage above boost output voltage (V

FET Q4 drain voltage

FET Q4 peak current

A resistor used to program the switching period TT

Current sense resistor R21

Maximum boost inductor current

Boost inductance

Boost output voltage

Secondary output voltage DC = the LED string supply voltage

Load power = power to the LED string

BST

)

2.2 Definition of Acronyms

Acronym Description

PFC Power Factor Correction

OVP Overvoltage Protection

eOTP External Overtemperature Protection

OCP Overcurrent Protection

iOTP Internal Overtemperature Protection

OLP Open Loop Protection

LED Light Emitting Diode

TRIAC

SSL

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TRIode for Alternating Current, which is an electronic component that can conduct current in either direction when it is triggered. It is formally called a bidirectional triode thyristor.

Solid State Lighting. Refers to a type of lighting that uses semiconductor LEDs as a source of illumination rather than electrical filaments, plasma, or gas.

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LED +

LED -

R11

R17R13

R18

NTC

R14

R15

R22

R23

R21

R19

BR1

R12

CS1612 /13

FBGAIN

IAC

FBAUX

BSTOUT

GND

SGNDIPK

CLAMP

FBSENSE

eOTP

VDD

SOURCE

AC Mains

R10

R16

R20

BSTAUX

R24

Boost

Gate Bias

Steady Stat e

Supply

Active Clamp

Second Stage

Buck

EMI

C10

C3C1 C12

C11

Figure 1. Block Diagram of CS1612/13 Design

3 Design Process

The design process for a two-stage power converter system can be partitioned into six circuit blocks (see Figure 1). The AC line voltage is passed through an electromagnetic interference (EMI) filter to suppress conducted interference found on the power line. The output of the EMI filter is then converted to the desired DC output by a boost-buck converter. The power converter system includes the Gate Bias, Steady State Supply, and Active Clamp support circuitry.

3.1 Operating Parameters

To initiate the design procedure, a set of operating parameters is required. Operating parameters required for the analytical process are outlined in the table below. Parameters critical to the overall design, but not specifically addressed in this document, include: EMI compliance, efficiency, footprint, layout, and operating temperature.

Output Power

AC Line Input Voltage

Output Voltage

Parameters Symbol

Load Current

Maximum Switching Frequency*

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* Increasing FSW may reduce the size of the magnetics but increases switching losses in the FET.

OUT

SW(max)

3.2 Overview of Design Steps

The CS1612/13 LED driver IC controls a power converter system that has two distinct power-conversion stages. The IC requires supporting circuitry to provide a steady-state power supply with gate bias, a clamp circuit, and EMI filtering. The recommended design process is outlined below:

1. Start with the buck stage.

2. Design for full power at minimum V parameters.

3. Optimize the buck stage through validation and design iteration.

4. Base the boost stage design on the power requirement of the buck stage.

5. Start the boost stage design in No-dimmer Mode.

6. Determine the peak current in the boost inductor, I

7. Determine a boost inductance, L Consider the impact on the EMI.

8. Pick the boost FET based on peak current ratings.

9. Choose the power supply components.

10.Complete the non-power-converting circuitry: ZCD, OVP, eOTP, Clamp Circuit, Charge Pumps, and Bias Circuits.

11. Design the EMI filter.

12.Lay out the PCB.

. Note that any design may require trade-offs for different operating

BST

PK(BST)

, that adjusts the switching frequency within the defined range.

BST

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The buck stage design is carried out at the full brightness (full load) point. To achieve an optimal solution, several iterations of the design process may be required. The EMI filter is particularly critical because there is a small degree of freedom in selecting the EMI component values that meet the requirements below:

• Comply with EMI regulations

• Achieve compatibility with the largest variety of dimmers

• Smooth dimming, no flicker with a variable number of identical lamps controlled by one dimmer

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3.3 Buck Stage Design

Buck Specification

Determine N, Fsw,

Refle cted

, and V

CLAMP

Estimate T3

Calculate TT

Calculate R

Sense

FBG AIN

, and Buck

Inductance

Sense,RFBG AIN

Fit?

Yes

Calculate T1,

T2, and I

PK(FB)

Calculate RMS Current

and Output Capacitor

Buck Inductor

Specification

Steps for the Buck Design

1. Select a buck topology

2. Set the boost output voltage, V

BST

3. Select a FET that aligns with the quality standards of the designer’s company.

4. Determine the inductor turns ratio from the

BST

, FET

voltage, and reflected voltage, V

Reflected

5. Use the nominal switching frequency and an initial estimate for time T3 to determine the value of time TT at full brightness.

6. Use V

BST

, TT, and V

Reflected

to determine times T1 and T2.

7. Use times T2 and TT, turns ratio N, and load current to determine the value of the peak primary current, I

PK(FB)

8. Use I

PK(FB)

to determine R

Sense

9. Calculate the buck inductance L using time T1.

10. Calculate second stage gain resistor R

FBGAIN

using full load conditions. Ensure linearity of the load versus the dim curve.

11. Calculate RMS currents in the two windings of L using peak current I

PK(FB)

and duty cycle.

12. Select an output capacitor.

13. Determine the buck inductor specifications.

14. Determine if the buck inductor fits into a specified form factor after designing and constructing the buck inductor. Repeat steps 3 to 12 until form factor criteria is met.

15. Refinements to the circuit with final buck inductor design.

16. Validate that the system meets the operating criteria.

Figure 2 illustrates the steps for designing the buck stage.

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Figure 2. Buck Stage Design

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Step 1) Choosing a Buck Topology

The first step in designing the buck stage is to choose a tapped buck or a normal buck. Consider the following advantages and disadvantages of either solution:

Normal Buck Tapped Buck

Most effective with low V

High peak current; low duty cycle Low peak current; high duty cycle

Simple low-value inductor Two windings of different turns and gauges

Reduced quasi-resonant advantage Take advantage of the near zero-voltage switching

Leakage inductance L no snubber is required

Low inductance L allows for high oscillation frequency

Load current has lower RMS ripple and no discontinuity; visualize Figure 1 for N=0.

Higher bulk capacitor ripple current Lower bulk capacitor ripple current

Higher bulk capacitor value Lower bulk capacitor value

Higher conduction losses Lower conduction losses

May be bound by minimum switching period T1 limitations

Lower FET voltage stress Higher FET voltage stress

Higher FET current stress Lower FET current stress

BST/VOUT

losses are not an issue, so

The tapped buck is best suited for a high V

ratios Most effective with high V

losses may require a

BST/VOUT

Leakage inductance L snubber but may self-snub by the inductor winding

capacitance

High inductance L and high parasitic capacitance

gives low oscillation frequency

Load current has higher RMS ripple and a discontinuity step; see Figure 1

Switching period T1 can be extended proportionally to turns ratio N

ratio. The best approach to guarantee the most

BST/VOUT

ratios

convenient buck topology choice is to complete a preliminary design for both, and then determine whether parameter results are impractical or out of range for the available technology and cost constraints.

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R21

GND

FBSENSE

CS1612/13

BST

OUT

N:1

N turns 1 turn

Figure 3. Buck Converter

Figure 3 illustrates a generic implementation of a buck converter using a tapped inductor topology. A normal buck stage can be implemented by neglecting the N turn's extension. The load is composed of a string of LEDs. Diode D3 is the catch diode, also known as the free wheeling diode, and its function is to allow the current to flow in inductor L4 and to the load after FET Q4 opens. Capacitance C parasitic capacitance associated with the FET drain node, usually consisting of the FET drain-source capacitance, inductor winding capacitance, diode D3 reverse bias capacitance, and any additional snubbing capacitance that may be required.

represents the combined

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Leakage inductance, represented by L labeled N turns and 1 turn are tightly coupled; the stray flux is represented by the uncoupled inductance L Leakage inductance L the normalized winding turns. The real inductor will have T turns and (N

is not a concern in a normal buck (non-tapped) design. Inductor winding N and 1 are

, is inevitably associated with a tapped inductor. Inductor windings

 T) turns.

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Area = N ު V

OUT

ު T2

Area = V

OUT

ު T2

Area = (V

BST

- V

OUT)

ު T1

BST

ZERO

N ު V

OUT

Reflected

Figure 4a. FET Drain Voltage

1- '

PK(FB)

(N+1)

ު I

PK(FB)

Figure 4b. Current Through FET Q4 and Diode D3

The buck stage is supplied by the boost output voltage. The boost output voltage is regulated within 10% by the boost stage. The buck control loop regulates the output current as long as the peak current has sufficient margin to rise 10% at the lowest boost output voltage. Figure 4a and Figure 4b show idealized waveforms of the FET Q4 drain voltage and drain current and the diode D3 current.

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Drain maxVBST maxVCLAMP max

[Eq. 1]

OvershootVCLAMPVReflecteed

–=

[Eq. 2]

Margin

CLAMP

BST

Overshoot

Reflected

ET Breakdown Voltage Rating

Clamp

Voltage

Boost Output

Voltage

Margin

Reflected Voltage

Overshoot Voltage

Overshoot is a brief condition above V

Reflected

, required to quickly dissipate the energy stored in the inductor leakage, L

During this time, the primary current is kept from transferring to the secondary, siphoning energy from the load to the clamp zener (snubber).

Figure 5. FET Breakdown Voltage

Step 2) Select a Value for Boost Output Voltage

The value of the boost output voltage, V The maximum V

voltage, V

BST

BST(max)

requirement within economical constraints.

is determined by an internal parameter and changes slightly depending on the type of dimmer detected.

BST

With sense resistors R7, R8, R14, and R15 set to 1.5M, the resulting V system. For a 120V system, sense resistors R7, R8, R14, and R15 are set to 750k each, and the resulting V

is approximately 200V. V

BST

each half line-cycle. V

droops to its lowest value towards the end of each half line-cycle until the boosting

BST

is regulated by charging the boost output capacitor to its nominal value

BST

process starts again in the next half line-cycle.

Step 3) Select an Appropriate FET

Determine the FET breakdown voltage, V voltage, V

Drain(max)

, is calculated using Equation 1.

, must be greater than the maximum input AC line voltage peak.

BST

, should be kept as low as possible to help maintain the FET breakdown

is approximately 405V for a 230V

BST

Breakdown

, and reflected voltage, V

Reflected

. The FET maximum drain

The ringing associated with the inductor leakage, L

, usually does not have enough energy to cause a

destructive avalanche breakdown. Voltages closely approaching the FET breakdown voltage are acceptable.

Ideally, V

Reflected

near 50% duty cycle optimizes efficiency. Alternatively, V rapidly discharge the energy stored in the inductor leakage, L

should have nearly the same value as V

because operating the tapped buck inductor at

BST

should be much greater than V

CLAMP

Reflected

The FET breakdown voltage is constrained by cost and performance. A compromise must be reached in partitioning voltage between V divide V

CLAMP

into V

Reflected

The losses caused by the leakage inductance are inversely proportional to V

BST

, V

CLAMP

, and V

. A second compromise will then determine how to

Margin

and a reasonable overshoot voltage portion, V

Overshoot

, which is determined by

Equation 2.

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