C&H Technology PS11011 User Manual

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Suite 108
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www.chtechnology.com - SPECIALISTS IN POWER ELECTRONIC COMPONENTS AND ASSEMBLIES - www.chtechnology.com

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11011

FLAT-B ASE TYPE

FLA T -B ASE TYPE

INSULA TED TYPE

PS11011

PS11011

INSULA TED TYPE

INTEGRATED FUNCTIONS AND FEATURES

• Converter bridge for 3 phase AC-to-DC power conversion.

• Circuit for dynamic braking of motor regenerative energy.

• 3-phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.

• Inverter output current capability I

Type Name

PS11011

100% load

0.8A (rms)

O (Note 1):

150% over load

1.2A (rms), 1min

(Note 1) : The inverter output current is assumed to be sinu-

soidal and the peak current value of each of the
above loading cases is defined as : I

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:

• For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC).

• For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC).

• For Brake circuit IGBT : Drive circuit

• Warning and Fault signaling :
F

O1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.

F

O2 : N-side control supply abnormality locking (OV/UV).

F

O3 : System over-temperature protection (OT).

CL : Warning for inverter current o verload condition

• For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3φ).

• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.

Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV).
Control supply circuit under- & over- voltage protection (OV/UV).

System over temperature protection (OT). Fault output signaling circuit (F

O) and Current limit warn-

ing signal output (CL).

OP = IO × √2

APPLICATION

Acoustic noise-less 0.1kW/AC200V class 3 phase inverter and other motor control applica­tions

PACKAGE OUTLINES

4-R2

2-φ4

2-R4

3.5

0.5

12 34 56 789

2

2

4.14

31 32 33 34 35 36 37 38 39 40

1.2

22444

5.08

10111213141516 1718 192 021 23

2

± 0.3

± 0.3

✕ 9 = 45.72

LABEL

54

± 0.5

62

± 1

± 0.8

✽

6

22

± 1

20.4

0.5

✽

± 0.8

72

± 0.5

0.6

✽

17.6

✽ Control Pin top

± 1

27

portion details

0.3

0.4

0.5

0~0.8

± 0.03

4

50

4

(12.25)

8.5

± 1

84.2

24

12

1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN

✽ Main terminal top
portion details

± 0.5

0.8

0

± 0.5

12

0

Terminals Assignment:

21 VN
22 WN
23 Br

31 R
32 S
33 T
34 P1
35 P2
36 N
37 B
38 U
39 V
40 W

0.35MAX

0~0.8

0.5

0.6

(Fig. 1)

Jan. 2000

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

INTERNAL FUNCTIONS BLOCK DIAGRAM

C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change
depending on the type PWM control scheme used in the applied system)
C4 ; 2µF R-category ceramic condenser for noise filtering.

Application Specific Intelligent

CZ

P2

B

P1

R
S
T

N

CUCVCW U

Brake resistor
connection,
Inrush prevention
circuit, etc.

AC200V line input

Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit maybe necessary
depending on the application environment].

Analogue signal output corresponding to

Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10)
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10)
Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig.10)
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra
precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins.

each phase current (5V line) Note 1)

Power Module

Current sensing

circuit

Trig signal conditioning

PVPWPUNVNWNBr

Each phase input (PWM)

(5V line) Note 2)

Protection

Circuit

Drive Curcuit

FO Logic

CL FO1 FO2 FO3

Fault output

(5V line) Note 3)

Level shifter

Drive Circuit

Protection

circuit

CBU–

T.S.

Control supply

fault sense

CBU+

CBV–

CBV+

CBW–

CBW+

C4,C3

C2

(15V line)

VDHGND

PS11011

FLAT-B ASE TYPE

INSULA TED TYPE

U
V

M

W

AC 200V line
output

C2 ;

3.3µF or more

(Fig. 2)

MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART (Including Brake Part)

ConditionSymbol Item Ratings Unit

V

CC

VCC(surge)
VP or VN

V

P(S)

±IC(±ICP)

C(ICP)

I

F(IFP)

I

Supply voltage
Supply voltage (surge)

Each output IGBT collector-emitter static voltage
Each output IGBT collector-emitter

or V

N(S)

switching surge voltage
Each output IGBT collector current
Brake IGBT collector current
Brake diode anode current

Applied between P2-N
Applied between P2-N, Surge-value
Applied between P-U, V, W, Br or U, V, W,

Br-N
Applied between P-U, V, W, Br or U, V, W,

Br-N

C = 25°C

T
Note: “( )” means I

C peak value

450
500

600
600

±2 (±4)

2 (4)
2 (4)

CONVERTER PART

Symbol Item Ratings Unit
VRRM
Ea

O

I
IFSM
I2t

Repetitive peak reverse voltage
Recommended AC input voltage
DC output current
Surge (non-repetitive) forward current

2

t for fusing

I

3φ rectifying circuit
1 cycle at 60Hz, peak value non-repetitive
Value for one cycle of surge current

Condition

800
220

25

138

80

CONTROL PAR T

Symbol Item Ratings Unit

DH, VDB

V

VCIN
VFO

IFO
VCL
ICL
ICO

Supply voltage

Input signal voltage –0.5 ~ 7.5
Fault output supply voltage

Fault output current
Current-limit warning (CL) output voltage
CL output current
Analogue current signal output current

Applied between V
C

BV+-CBV–, CBW+-CBW–

Applied between UP · VP · WP · UN · VN ·
W

N · Br-GND

Applied between F
Sink current of F
Applied between CL-GND
Sink current of CL
Sink current of CU · CV · CW

Condition

DH-GND, CBU+-CBU–,

O1 · FO2 · FO3-GND

O1 · FO2 · FO3

20

–0.5 ~ 7

15

–0.5 ~ 7

15
±1

A

mA

mA
mA

V
V

V

V
A

A
A

V
V
A
A

2

s

V

V
V

V

Jan. 2000

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11011

FLAT-B ASE TYPE

INSULA TED TYPE

TOTAL SYSTEM

Symbol

j

T
Tstg
TC

Viso

—

Item
Junction temperature
Storage temperature
Module case operating temperature

Isolation voltage
Mounting torque

60 Hz sinusoidal AC applied between all terminals and
the base plate for 1 minute.

Mounting screw: M3.5

Condition

(Note 2)

—

(Fig. 3)

Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How-

ever, these power elements can endure junction temperature as high as 150°C instantaneously . To make use of this additional tem­perature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested
to be provided before use.

CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)

Ratings Unit
–20 ~ +125
–40 ~ +125
–20 ~ +100

2500

0.78 ~ 1.27

°C
°C
°C

Vrms

kg·cm

TC

(Fig. 3)

THERMAL RESISTANCE

Symbol Item

Q

Rth(j-c)
Rth(j-c)F
Rth(j-c)QB
Rth(j-c)FB
Rth(j-c)
Rth(c-f)

Junction to case Thermal
Resistance

FR

Contact Thermal Resistance

Inverter IGBT (1/6)
Inverter FWDi (1/6)
Brake IGBT
Brake FWDi
Converter Di (1/6)
Case to fin, thermal grease applied (1 Module)

Condition

ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)

Symbol Item

CE(sat)

V
VEC

V

CE(sat)Br VDH = 15V, Input = ON, Tj = 25°C, IC = 2A

FBr

V
IRRM
VFR

Collector-emitter saturation voltage
FWDi forward voltage
Brake IGBT

Collector-emitter saturation voltage
Brake diode forward voltage
Converter diode reverse current

Converter diode voltage
ton
tc(on)
toff

Switching times
tc(off)

trr

FWD reverse recovery time

Short circuit endurance

(Output, Arm, and Load,

Short Circuit Modes)

Switching SOA

VDH = VDB = 15V, Input = ON, Tj = 25°C, IC = 2A
Tj = 25°C, IC = –2A, Input = OFF

Tj = 25°C, I

R = VRRM, Tj = 125°C

V
Tj = 25°C, I

F = 2A, Input = OFF

F = 5A

1/2 Bridge inductive load, Input = ON

CC = 300V, Ic = 2A, Tj = 125°C

V

DH = 15V, VDB = 15V

V
Note : ton, toff include delay time of the internal control

circuit

CC ≤ 400V, Input = ON (one-shot)

V
Tj = 125°C start

13.5V ≤ V
V
Ic < I

13.5V ≤ V

DH = VDB ≤ 16.5V

CC ≤ 400V, Tj ≤ 125°C,

OL(CL) operation level, Input = ON

DH = VDB ≤ 16.5V

Condition

Ratings

Min.

—
—
—
—
—
—

Typ. Max.

—
—
—
—
—
—

7.3

6.1

7.3

6.1

4.8

0.053

Ratings

Min. Typ. Max.

—
—

—
—

—
—

0.3
—

—
—

—

• No destruction

• F

O output by protection operation

—
—

—
—

—
—

0.6

0.2

1.1

0.35

2.9

2.9

3.5

2.9
8

1.5

1.5

0.6

1.8

1.0

—0.1

• No destruction

• No protecting operation

• No F

O output

Unit

°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

Unit

V
V

V
V

mA

V

µs
µs
µs
µs
µs

Jan. 2000

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11011

FLAT-B ASE TYPE

INSULA TED TYPE

ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)

ConditionSymbol

C

= –20°C ~ +100°C

DH = 15V

V

C = –20°C ~ +100°C

T

(Fig. 4)

(Fig. 4)

OP(200%) (Fig. 5)

IDH
Vth(on)
Vth(off)
Ri
fPWM
txx

t

dead

tint
VCO
VC+(200%)

C–

(200%)

V
|∆VCO|

C+

V
VC–
∆VC(200%)

CH

r

d(read)

t
±IOL
ICL(H)
ICL(L)
SC
OT
OTr

DH

UV
UVDHr
OVDH
OVDHr
UVDB
UVDBr
tdV
IFO(H)
IFO(L)

Item

Circuit current
Input on threshold voltage

Input off threshold voltage
Input pull-up resistor

PWM input frequency
Allowable input on-pulse width

Allowable input signal dead time for
blocking arm shoot-through

Input inter-lock sensing

Analogue signal linearity with
output current

Offset change area vs temperature
Analogue signal output voltage limit

Analogue signal over all linear variation
Analogue signal data hold accuracy

Analogue signal reading time
Current limit warning (CL) operation level

Signal output current of
CL operation

Idle
Active

Short circuit over current trip level
Over temperature protection

Trip level
Reset level
Trip level
Reset level
Trip level

Supply circuit under &
over voltage protection

Reset level
Trip level
Reset level
Filter time

Fault output current

Idle
Active

DH = 15V, VCIN = 5V

V

Integrated between input terminal-VDH
TC ≤ 100°C, Tj ≤ 125°C

DH = 15V, TC = –20°C ~ +100°C (Note 3)

V
Relates to corresponding input
(Except brake part) T
Relates to corresponding input (Except brake part)

Ic = 0A
Ic = I

OP(200%)

OP(200%)

Ic = –I
VDH = 15V, TC = –20°C ~ +100°C

OP(200%), VDH = 15V

Ic > I

|V

CO-VC±(200%)|

Correspond to max. 500µs data hold period
only, Ic = I

After input signal trigger point (Fig. 8)
VDH =15V, TC = –20°C ~ +100°C (Note 4)

Open collector output
Tj = 25°C (Fig. 7) (Note 5)

VDH =15V

C = –20°C ~ +100°C

T
Tj ≤ 125°C

Open collector output

(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.

(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.

(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The

circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.

(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-

tarily. The protection function is , thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri­ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its F

O1 pin of the ASIPM indicating a short circuit situation.

Ratings

Min.

0.8

2.5

2.2

1.87

0.77

2.97

4.0

–5

2.64

3.50
100

11.05

11.55

18.00

16.50

10.0

10.5

Typ. Max.

—mA

150—

1.4

3.0

—

150

2
1

—
—

500

—

—

—
—

65

2.27

1.17

3.37
15

—

100

2.57

1.47

3.67

—

—

1.1
—

—

—
—

—

—
—
—

3

3.10
—

1

6.00

110

90

12.00

12.50

19.20

17.50

11.0

11.5

10

—

1

3.60

9.60
120

12.75

13.25

20.15

18.65

12.0

12.5

2.0

4.0
—
20

—

—

0.7
—
—

—

—

—

—

—

Unit

V
V

kΩ

kHz

µs
µs

ns

V
V
V

mV

V
V
V

5

%

µs

A

1

µA

mA

A

°C
°C

V
V
V
V
V
V

µs
µA

1

mA

RECOMMENDED CONDITIONS

Symbol

VCC

DH, VDB Control supply voltage

V
∆VDH, ∆V

VCIN(on)
VCIN(off)
fPWM
tdead

Supply voltage

DB

Supply voltage ripple
Input on voltage
Input off voltage
PWM Input frequency
Arm shoot-through blocking time

Item Ratings

Applied between V
C

BW+-CBW–

DH-GND, CBU+-CBU–, CBV+-CBV–,

Using application circuit
Using application circuit

Condition

15±1.5

±1 (max.)

0 ~ 0.3

4.8 ~ 5.0
2 ~ 20

2.2 (min.)

Unit

V 400 (max.)Applied across P2-N terminals
V

V/µs

V
V

kHz

µs

Jan. 2000

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11011

FLAT-B ASE TYPE

INSULA TED TYPE

Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING

LINEARITY

5

C

–

V

max

4

min

V

C

–

(200%)

VDH=15V
T

C

=–20~100˚C

3

C0

V

2

VC(V)

1

Analogue output signal

data hold range

0

Real load current peak value.(%)(Ic=Io✕ 2)

VC+(200%)

200–200

VC+

4003001000–100–300–400

(Fig. 4)

Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART

Input signal V

Input signal V

Gate signal V
(ASIPM internal)

Gate signal V
(ASIPM internal)

CIN(p) of each phase upper arm

CIN(n) of each phase lower arm

o(p) of each phase upper arm

o(n) of each phase upper arm

0V

0V

0V

0V

Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING

“DATA HOLD” DEFINITION

V

C

500µs

0V

Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.

VCH(5µs) VCH(505µs)

V

CH

rCH=

(505µs)-VCH(5µs)

CH

(5µs)

V

Error output F

O1

0V

Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-

neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F

O

interlock” operation the circuit is latched. The “F

” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,

O” signal is outputted. After an “input

whichever comes in later.

Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

CIN

Input signal V
upper arm

Short circuit sensing signal V

Gate signal Vo of each phase
upper arm(ASIPM internal)

Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by

gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).

of each phase

Error output F

0V

S

0V

0V

O1

0V

SC delay time

Jan. 2000

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART

N-side IGBT Current N-side FWDi Current

CIN

I

off
on

on
off

C

0

+I

CL

0

V

V(hold)

(VS)

PS11011

FLAT-B ASE TYPE

INSULA TED TYPE

–I

CL

Ref

V

C

0

off

V

CL

on

t(hold)

Delay time
td(read)

Fig. 9 START-UP SEQUENCE

Normally at start-up, Fo and CL output signals will be pulled-up
High to Supply voltage (OFF level); however, F
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. F

O1 resetting sequence (together with the boot-strap

charging sequence) is explained in the following graph

DC-Bus voltage

Control voltage supply

Boot-strap voltage
N-Side input signal

P-Side input signal

V

CIN(N)

V

V

V

DH

V

CIN(P)

PN

0

0

DB

0

on

on

O1 output may fall to

PWM starts

a)

b)

Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT

5V

ASIPM

5.1kΩ

R

CPU

10kΩ

R

UP,VP,WP,UN,VN,WN,Br
F01,F02,F03,CL

CU,CV,CW

0.1nF0.1nF

GND(Logic)

V

Brake input signal

F

O

1 output signal

CIN(Br)

F

on

OI

on

a) Boot-strap charging scheme :

Apply a train of short ON pulses at all N-IGBT input pins for ad­equate charging (pulse width = approx. 20µs number of pulses =10
~ 500 depending on the boot-strap capacitor size)

b) F

O1 resetting sequence:

Apply ON signals to the following input pins : Br → Un/Vn/Wn →
Up/Vp/Wp in that order.

Jan. 2000

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.