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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11011
FLAT-B ASE TYPE
FLA T -B ASE TYPE
INSULA TED TYPE
PS11011
PS11011
INSULA TED TYPE
INTEGRATED FUNCTIONS AND FEATURES
• Converter bridge for 3 phase AC-to-DC power conversion.
• Circuit for dynamic braking of motor regenerative energy.
• 3-phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.
• Inverter output current capability I
Type Name
PS11011
100% load
0.8A (rms)
O (Note 1):
150% over load
1.2A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : I
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC).
• For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC).
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling :
F
O1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
F
O2 : N-side control supply abnormality locking (OV/UV).
F
O3 : System over-temperature protection (OT).
CL : Warning for inverter current o verload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV).
Control supply circuit under- & over- voltage protection (OV/UV).
System over temperature protection (OT). Fault output signaling circuit (F
O) and Current limit warn-
ing signal output (CL).
OP = IO × √2
APPLICATION
Acoustic noise-less 0.1kW/AC200V class 3 phase inverter and other motor control applications
PACKAGE OUTLINES
4-R2
2-φ4
2-R4
3.5
0.5
12 34 56 789
2
2
4.14
31 32 33 34 35 36 37 38 39 40
1.2
22444
5.08
10111213141516 1718 192 021 23
2
± 0.3
± 0.3
✕ 9 = 45.72
LABEL
54
± 0.5
62
± 1
± 0.8
✽
6
22
± 1
20.4
0.5
✽
± 0.8
72
± 0.5
0.6
✽
17.6
✽ Control Pin top
± 1
27
portion details
0.3
0.4
0.5
0~0.8
± 0.03
4
50
4
(12.25)
8.5
± 1
84.2
24
12
1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
✽ Main terminal top
portion details
± 0.5
0.8
0
± 0.5
12
0
Terminals Assignment:
21 VN
22 WN
23 Br
31 R
32 S
33 T
34 P1
35 P2
36 N
37 B
38 U
39 V
40 W
0.35MAX
0~0.8
0.5
0.6
(Fig. 1)
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
INTERNAL FUNCTIONS BLOCK DIAGRAM
C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change
depending on the type PWM control scheme used in the applied system)
C4 ; 2µF R-category ceramic condenser for noise filtering.
Application Specific Intelligent
CZ
P2
B
P1
R
S
T
N
CUCVCW U
Brake resistor
connection,
Inrush prevention
circuit, etc.
AC200V line input
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit maybe necessary
depending on the application environment].
Analogue signal output corresponding to
Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10)
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10)
Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig.10)
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra
precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins.
each phase current (5V line) Note 1)
Power Module
Current sensing
circuit
Trig signal conditioning
PVPWPUNVNWNBr
Each phase input (PWM)
(5V line) Note 2)
Protection
Circuit
Drive Curcuit
FO Logic
CL FO1 FO2 FO3
Fault output
(5V line) Note 3)
Level shifter
Drive Circuit
Protection
circuit
CBU–
T.S.
Control supply
fault sense
CBU+
CBV–
CBV+
CBW–
CBW+
C4,C3
C2
(15V line)
VDHGND
PS11011
FLAT-B ASE TYPE
INSULA TED TYPE
U
V
M
W
AC 200V line
output
C2 ;
3.3µF or more
(Fig. 2)
MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART (Including Brake Part)
ConditionSymbol Item Ratings Unit
V
CC
VCC(surge)
VP or VN
V
P(S)
±IC(±ICP)
C(ICP)
I
F(IFP)
I
Supply voltage
Supply voltage (surge)
Each output IGBT collector-emitter static voltage
Each output IGBT collector-emitter
or V
N(S)
switching surge voltage
Each output IGBT collector current
Brake IGBT collector current
Brake diode anode current
Applied between P2-N
Applied between P2-N, Surge-value
Applied between P-U, V, W, Br or U, V, W,
Br-N
Applied between P-U, V, W, Br or U, V, W,
Br-N
C = 25°C
T
Note: “( )” means I
C peak value
450
500
600
600
±2 (±4)
2 (4)
2 (4)
CONVERTER PART
Symbol Item Ratings Unit
VRRM
Ea
O
I
IFSM
I2t
Repetitive peak reverse voltage
Recommended AC input voltage
DC output current
Surge (non-repetitive) forward current
2
t for fusing
I
3φ rectifying circuit
1 cycle at 60Hz, peak value non-repetitive
Value for one cycle of surge current
Condition
800
220
25
138
80
CONTROL PAR T
Symbol Item Ratings Unit
DH, VDB
V
VCIN
VFO
IFO
VCL
ICL
ICO
Supply voltage
Input signal voltage –0.5 ~ 7.5
Fault output supply voltage
Fault output current
Current-limit warning (CL) output voltage
CL output current
Analogue current signal output current
Applied between V
C
BV+-CBV–, CBW+-CBW–
Applied between UP · VP · WP · UN · VN ·
W
N · Br-GND
Applied between F
Sink current of F
Applied between CL-GND
Sink current of CL
Sink current of CU · CV · CW
Condition
DH-GND, CBU+-CBU–,
O1 · FO2 · FO3-GND
O1 · FO2 · FO3
20
–0.5 ~ 7
15
–0.5 ~ 7
15
±1
A
mA
mA
mA
V
V
V
V
A
A
A
V
V
A
A
2
s
V
V
V
V
Jan. 2000