China TV 11AK45 Service Manual

TABLE OF CONTENTS ............................................................................................................. i

1.INTRODUCTION..............................................................................................................................1

2.TUNER.................................................................................................................................................1

3.IF PART (TDA9885/86)..................................................................................................................1

4.VIDEO SWITCH TEA6415............................................................................................................2

5.MULTI STANDARD SOUND PROCESSOR...........................................................................2

6.SOUND OUTPUT STAGE WITH TDA7269A.........................................................................2

7.BERTICAL OUTPUT STAGE WITH STV9379FA.................................................................2

8.VIDEO OUTPUT AMPLIFIER TDA6108...................................................................................2

9.POWER SUPPLY (SMPS)............................................................................................................3

10.MICROCONTROLLER SDA55XX

10.1.General Features..........................................................................................................................3

10.2.External Crystal and Programmable Clock Speed ...................................................................3

10.3.Microcontroller Features.............................................................................................................3

10.4.Memory..........................................................................................................................................3

10.5.Display Features...........................................................................................................................3

10.6.Acquisition Features....................................................................................................................4

10.7.Ports ..............................................................................................................................................4

...........................................................................................3

11.CLASS AB STEREO HEADPHONE DRIVER TDA1308 .................................................4

12.SAW FILTERS................................................................................................................................4

13.IC DESCRIPTIONS.......................................................................................................................5

13.1.LM317T......................................................................................................................................5

13.1.1.Description.............................................................................................................................5

13.1.2.Features..................................................................................................................................5

13.2.TDA1308T.................................................................................................................................5

13.2.1.General Description ..............................................................................................................5

13.2.2.Features..................................................................................................................................5

13.2.3.Pinning....................................................................................................................................6

13.3.MSP34X0G (MSP3410G) ....................................................................................................6

13.3.1.Description.............................................................................................................................6

13.3.2.Features..................................................................................................................................8

13.3.3.Pin connections.....................................................................................................................8

13.4.VDP313xY

13.4.1.Introduction............................................................................................................................9

13.4.2.Features................................................................................................................................10

13.4.3.Pin Connections and short descriptions..........................................................................10

................................................................................................................................9

13.5.TEA6415C ..............................................................................................................................11

13.5.1.General Description ............................................................................................................11

13.5.2.Features................................................................................................................................11

13.5.3.Pinning..................................................................................................................................12

13.6.STV9379FA............................................................................................................................12

13.6.1.Description...........................................................................................................................12

13.6.2.Features................................................................................................................................12

13.6.3.Pinning..................................................................................................................................12

13.7.TDA7269A..............................................................................................................................13

13.7.1.Description...........................................................................................................................13

13.7.2.Features................................................................................................................................13

13.8.LM7800 (LM7805/LM7808)...............................................................................................13

13.8.1.Description...........................................................................................................................13

13.8.2.Features................................................................................................................................13

13.9.AT24C08.................................................................................................................................13

13.9.1.Description...........................................................................................................................13

13.9.2.Features................................................................................................................................13

13.9.3.Pin Configurations ..............................................................................................................14

11ak45 27/10/2007

13.10.SDA5555...............................................................................................................................14

13.10.1.General definition..............................................................................................................14

13.10.2.Features..............................................................................................................................14

13.11.MC44608...............................................................................................................................15

13.11.1.Description.........................................................................................................................15

13.11.2.General Features...............................................................................................................16

13.11.3.Pin Connections................................................................................................................16

13.11.4.Pin Function description .............................................................................................................16

13.12.TCET1102G.........................................................................................................................17

13.12.1.Description.........................................................................................................................17

13.12.2.Applications.......................................................................................................................17

13.12.3.Features..............................................................................................................................17

13.13.TDA9885T............................................................................................................................17

13.13.1.General Description ..........................................................................................................17

13.13.2.Features..............................................................................................................................17

13.13.3.Pinning................................................................................................................................18

13.14.PI5V330.................................................................................................................................18

13.14.1.General Description ..........................................................................................................18

14.AK45 CHASSIS PRODUCTION SERVICE MODE ADJUSTMENTS.........................19

14.1.SERVICE MENU..........................................................................................................................19

14.2.ADJUST MENU ...........................................................................................................................19

White Point Red, White Point Green, White Point Blue:.........................................................19

AGC.........................................................................................................................................19

If PLL negative ........................................................................................................................19

If PLL pozitive.........................................................................................................................19

Y-Delay ....................................................................................................................................19

Y-Delay SECAM.....................................................................................................................20

Y-Delay NTSC.........................................................................................................................20

Y-Delay other...........................................................................................................................20

Vertical Pozition Offset............................................................................................................20

Horizontal Pozition Offset .......................................................................................................20

Vertical Blank Start..................................................................................................................20

Vertical Blank Stop..................................................................................................................20

Angle........................................................................................................................................20

Bow..........................................................................................................................................20

4:3 Horizontal Blank Start .......................................................................................................20

4:3 Horizontal Blank Stop........................................................................................................20

EHTV Compensation...............................................................................................................20

EHTTM Compensation............................................................................................................20

EHTEW Compensation............................................................................................................20

WDR........................................................................................................................................21

WDG........................................................................................................................................21

WDB........................................................................................................................................21

CR............................................................................................................................................21

CG............................................................................................................................................21

CB............................................................................................................................................21

COR coring level .....................................................................................................................21

REGULAR VERT_POS (Regular mode Vertical Position) ....................................................21

REGULAR VERT_AMPL (Regular mode Vertical Amplitude).............................................21

REGULAR VERT_SCOR (Regular mode Vertical S-Correction)..........................................21

REGULAR VERT_SSYM(Regular mode Vertical S Symmetry)...........................................21

REGULAR TRAPEZE (Regular mode Trapeze).....................................................................21

REGULAR CUSHION (Regular mode Cushion)....................................................................21

REGULAR HOR_COR_SYM (Regular mode Horizontal Corner Symmetry).......................21

REGULAR HOR_CORNER (Regular mode Horizontal Corner)...........................................21

REGULAR HORZ_POS (Regular mode Horizontal Position)................................................21

REGULAR HORZ_AMPL (Regular mode Horizontal Amplitude)........................................21

OSD Position............................................................................................................................24

11ak45 27/10/2007

BCLTHR..................................................................................................................................24

REFERENCE WDR RED (NORMAL)...................................................................................24

REFERENCE WDR GREEN (NORMAL) .............................................................................24

REFERENCE WDR BLUE (NORMAL)................................................................................24

REFERENCE CUTOFF GREEN ............................................................................................24

REFERENCE CUTOFF BLUE...............................................................................................24

IBRM .......................................................................................................................................24

WDRV .....................................................................................................................................24

G2 CUTOFF REFERENCE.....................................................................................................24

G2 WDR REFERENCE...........................................................................................................24

REFERENCE WDR RED COOL............................................................................................................25

REFERENCE WDR GREEN COOL ......................................................................................................25

REFERENCE WDR BLUE COOL.........................................................................................................25

REFERENCE WDR RED WARM..........................................................................................................25

REFERENCE WDR GREEN WARM ....................................................................................................25

REFERENCE WDR BLUE WARM.......................................................................................................25

BRIGHT MODE BRIGHTNESS.............................................................................................26

BRIGHT MODE COLOUR.....................................................................................................26

BRIGHT MODE CONTRAST................................................................................................26

14.3.OPTIONS MENU..........................................................................................................................31

Option 0. Video Processor Crystal Indication.............................................................................31

Option 1. (0x01) Video Processor Decoder Mode Register........................................................31

Option 2. (0x18) Video Processor Blanking Control...................................................................31

Option 3. (0x19) Video Processor Cathode Drive Level.............................................................32

Option 4...........................................................................................................................................32

Option 5. CTI Avaliable, Mono AVL...............................................................................................32

Option 6...........................................................................................................................................32

Option 7. OPTIONHOTELACTIVE, PLL_VST, PIP Zoom Mode, PIP Position ...........................32

Option 8. IF Frequency...................................................................................................................33

Option 9. Standard Available.........................................................................................................33

Option 10. Scart, Combfilter, Teletext, Language.......................................................................34

Option 11. PLL Tuner Control 1 Byte............................................................................................34

Option 12. PLL Tuner Control 2 Low Byte...................................................................................34

Option 13. PLL Tuner Control 2 Mid Byte....................................................................................35

Option 14. PLL Tuner Control 2 High Byte ..................................................................................35

Option 15. PLL Tuner VHF LOW – VHF HIGH Crossover Low Byte..........................................35

Option 16. PLL Tuner VHF LOW – VHF HIGH Crossover High Byte.........................................35

Option 17. PLL Tuner VHF HIGH – UHF Crossover Low Byte ...................................................35

Option 18. PLL Tuner VHF HIGH – UHF Crossover High Byte...................................................35

Option 19. PIP PLL Tuner Control 1 Byte.....................................................................................36

Option 20. PIP PLL Tuner Control 2 Low Byte ............................................................................36

Option 21. PIP PLL Tuner Control 2 Mid Byte .............................................................................36

Option 22. PIP PLL Tuner Control 2 High Byte............................................................................36

Option 23. PIP PLL Tuner VHF LOW – VHF HIGH Crossover Low Byte...................................36

Option 24. PIP PLL Tuner VHF LOW – VHF HIGH Crossover High Byte...................................36

Option 25. PIP PLL Tuner VHF HIGH – UHF Crossover Low Byte.............................................37

Option 26. PIP PLL Tuner VHF HIGH – UHF Crossover High Byte............................................37

Option 27. Language Available 1..................................................................................................37

Option 28. Language Available 2..................................................................................................37

Option 29. Language Available 3 and Zoom Mode Available ....................................................37

Option 30. Country .........................................................................................................................38

Option 31. Prescaler MSP FM (AVL=OFF)....................................................................................38

Option 32. Prescaler MSP NICAM (AVL=OFF).............................................................................38

Option 33. Prescaler MSP SCART (AVL=OFF) ............................................................................39

Option 34. Prescaler MSP I2S (AVL=OFF)....................................................................................39

Option 35. Not used........................................................................................................................39

Option 36. Not used........................................................................................................................39

Option 37. Reserved for USA ........................................................................................................39

Option 38. TV Teletext Mode Selection, Child Lock, Equalizer Country...................................39

Option 39. Personal Preferance Equalizer Band 1......................................................................40

Option 40. Personal Preferance Equalizer Band 2......................................................................40

11ak45 27/10/2007

Option 41. Personal Preferance Equalizer Band 3......................................................................40

Option 42. Personal Preferance Equalizer Band 4......................................................................40

Option 43. Personal Preferance Equalizer Band 5......................................................................40

Option 44. Sound Efect (Standard; Music; Speech; Jazz; Pp)...................................................40

Option 45. Volume Offset Left.......................................................................................................40

Option 46. Volume Offset Right ....................................................................................................40

Option 47. Volume Offset Center..................................................................................................41

Option 48. Volume Offset Rear......................................................................................................41

Option 49. Surround Delay............................................................................................................41

Option 50. FM Prescale..................................................................................................................41

Option 51. NICAM Prescale ...........................................................................................................41

Option 52. Scart Input Prescale ....................................................................................................41

Option 53. I2S Prescale..................................................................................................................41

Option 54. Scart Output Prescale .................................................................................................41

Option 55. Speaker Setup..............................................................................................................42

Option 56. Audio Options Available Or Not.................................................................................42

Option 57. Stereo Threshold .........................................................................................................42

Option 58. MSP Audio Flags..........................................................................................................43

Option 59. NICAM Threshold.........................................................................................................43

Option 60. Power Delay Time........................................................................................................43

14.4.OPTION TABLE RECOMMENDED VALUES.............................................................................46

14.5.SCREEN ADJUSTMENT (FBT SCREEN)..................................................................................48

14.6.GEOMETRY ADJUSTMENT.......................................................................................................49

4:3 FORMATS..................................................................................................................................49

16:9 FORMATS................................................................................................................................50

16.BLOCK DIAGRAM......................................................................................................................58

17.CIRCUIT DIAGRAMS.................................................................................................................59

11ak45 27/10/2007

1.INTRODUCTION

11AK45 is a 50Hz colour television capable of driving 24” + CRT sizes( beginning from 24” 16:9 up to 33”). The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L´. Sound system output is supplying 2x10W (10%THD) for left and right outputs of 8ohm speakers. TV supports FASTTEXT. It is possible to decode transmissions including high graphical data. The chassis is equipped with three full EuroScarts, only one of them supports RGB input, one headphone output, one FAV input, one SVHS input (via SCART)

2.TUNER

The hardware and software of the TV is suitable for tuners, supplied by different companies, which are selected from the Service Menu. These tuners can be combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L´, I/I´, and D/K. The tuning is available through the digitally controlled I

C bus

(PLL). Below you will find info on one of the Tuners in use.

General description of UV1316:

The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient.

Features of UV1316:

1. Member of the UV1300 family small sized UHF/VHF tuners

2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K

3. Digitally controlled (PLL) tuning via I

C-bus

4. Off-air channels, S-cable channels and Hyperband

5. World standardized mechanical dimensions and world standard pinning

6. Compact size

7. Complies to “CENELEC EN55020” and “EN55013”

Pinning:

1. Gain control voltage (AGC) : 4.0V, Max: 4.5V

2. Tuning voltage

3. I²C-bus address select : Max: 5.5V

4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V

5. I²C-bus serial data : Min:-0.3V, Max: 5.5V

6. Not connected

7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V

8. ADC input

9. Tuner supply voltage : 33V, Min: 30V, Max: 35V

10. Symmetrical IF output 1

11. Symmetrical IF output 2

3.IF PART (TDA9885/86)

The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL. The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL Both devices can be used for TV, VTR, PC and set-top box applications. The following figure shows the simplified block diagram of the integrated circuit. The integrated circuit comprises the following functional blocks: VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition help, Audio amplifier and mute time constant, I voltage stabilizer.

C-bus transceivers and MAD (module address), Internal

11ak45 27/10/2007

4.VIDEO SWITCH TEA6415

In case of three or more external sources are used, the video switch IC TEA6415 is used. The main function of this device is to switch 8 video-input sources on the 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of sync. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible to have the same input connected to several outputs.

5.MULTI STANDARD SOUND PROCESSOR

The MSP 34x10G family of single-chip Multi-standard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.

6.SOUND OUTPUT STAGE WITH TDA7269A

The TDA7269A is class AB dual Audio power amplifier assembled in the Multi-watt package, specially designed for high quality sound application as Hi-Fi music centers and stereo TV sets.

7.BERTICAL OUTPUT STAGE WITH STV9379FA

The IC STV9379FA is the vertical deflection booster circuit. Two supply voltages, +14V and –14V are needed to scan the inputs VERT+ and VERT-, respectively. And a third supply voltage, +60V for the flyback limiting are needed. The vertical deflection coil is connected in series between the output and feedback to the input.

8.VIDEO OUTPUT AMPLIFIER TDA6108

The TDA6108Q includes three video output amplifiers is intended to drive the three cathodes of a colour picture tube.

11ak45 27/10/2007

9.POWER SUPPLY (SMPS)

The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC MC44608, which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer generates 145V for FBT input, +/-14V for audio amplifier, 5V and

3.3V stand by voltage and 8V, 12V and 5V supplies for other different parts of the chassis. An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation circuit in secondary side. This circuit produces a control voltage according to the changes in 145V DC voltage, via an optocoupler (TCET1102G) to pin3 of the IC. During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations.

10.MICROCONTROLLER SDA55XX

10.1.General Features

• Feature selection via special function register

• Simultaneous reception of TTX, VPS, PDC, and WSS (line 23)

• Supply Voltage 2.5 and 3.3 V

• ROM version package PSDIP52-2, PMQFP64-1

• Romless version package PMQFP100-2, PLCC84-2

10.2.External Crystal and Programmable Clock Speed

• Single external 6MHz crystal, all necessary clocks are generated internally

• CPU clock speed selectable via special function registers.

• Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz

10.3.Microcontroller Features

• 8bit 8051 instruction set compatible CPU.

• 33.33-MHz internal clock (max.)

• 0.360 ms (min.) instruction cycle

• Two 16-bit timers

• Watchdog timer

• Capture compare timer for infrared remote control decoding

• Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)

• ADC (4 channels, 8 bit) UART (rxd, txd)

•

10.4.Memory

• Non-multiplexed 8-bit data and 16 … 20-bit address bus (ROMless Version)

• Memory banking up to 1Mbyte (Romless version)

• Up to 128 Kilobyte on Chip Program ROM

• Eight 16-bit data pointer registers (DPTR)

• 256-bytes on-chip Processor Internal RAM (IRAM)

• 128bytes extended stack memory.

• Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX

• UP to 16KByte on Chip Extended RAM (XRAM) consisting of;

- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX)

- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software

- 3 Kilobyte Display Memory

10.5.Display Features

• ROM Character Set Supports all East and West European Languages in single device

• Mosaic Graphic Character Set

• Parallel Display Attributes

• Single/Double Width/Height of Characters

• Variable Flash Rate

• Programmable Screen Size (25 Rows x 33...64 Columns)

• Flexible Character Matrixes (HxV) 12 x 9...16

• Up to 256 Dynamical Redefinable Characters

Characters in Enhanced Mode

• CLUT with up to 4096 colour combinations

11ak45 27/10/2007

in standard mode; 1024 Dynamical Redefinable

• Up to 16 Colours per DRCS Character

• One out of Eight Colours for Foreground and Background Colours for 1-bit DRCS and ROM

Characters

• Shadowing

• Contrast Reduction

• Pixel by Pixel Shiftable Cursor With up to 4 Different Colours

• Support of Progressive Scan and 100 Hz.

• 3 X 4Bits RGB-DACs On-Chip

• Free Programmable Pixel Clock from 10 MHz to 32MHz

• Pixel Clock Independent from CPU Clock

• Multinorm H/V-Display Synchronization in Master or Slave Mode

10.6.Acquisition Features

• Multi-standard Digital Data Slicer

• Parallel Multi-norm Slic

ing (TTX, VPS, WSS, CC, G+)

• Four Different Framing Codes Available

• Data Caption only limited by available Memory

• Programmable VBI-buffer

• Full Channel Data Slicing Supported

• Fully Digital Signal Processing

• Noise Measurement and Controlled Noise Compensation

• Attenuation Measurement and Compensation

• Group Delay Measurement and Compensation

• Exact Decoding of Echo Disturbed Signals

10.7.Ports

• One 8-bit I/O-port with open drain output and optional I

C Bus emulation support (Port0)

• Two 8-bit multifunction I/O-ports (Port1, Port3)

• One 4-bit port working as digital or analogue inputs for the ADC (Port2)

• One 2-bit I/O port with secondary function (P4.2, 4.3, 4.7)

• One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)

11.CLASS AB STEREO HEADPHONE DRIVER TDA1308

The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

12.SAW FILTERS

K3953M:

Standard

B/G, D/K, I, L/L’

Features

TV IF filter with Nyquist slopes at 33,90 MHz and 38,90 MHz Constant group delay Suitable for CENELEC EN 55020

Terminals

Tinned CuFe alloy

Pin configuration

1 Input 2 Input - ground 3 Chip carrier - ground 4 Output 5 Output

K3958M:

Standard

B/G, D/K, I, L/L’

Features

TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz Constant group delay Terminal and Pin configuration are the same with

K3953M

11ak45 27/10/2007

K9356M:

Standard

B/G, D/K, I, L

Features

TV IF audio filter with pass band for sound carriers at 32,40 MHz (D/K, L), 32,90 MHz (I) and 33,40 MHz (B/G) Terminal and Pin configuration are the same with

K3953M

K9656M:

Standard

B/G, D/K, I, L/L’

Features

TV IF audio filter with two channels Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75 MHz (L’- NICAM) Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32,35 MHz and 33,40 MHz Terminal and Pin configuration are the same with

K3953M

13.IC DESCRIPTIONS

LM317T TDA1308T MSP3410G VDP3130Y TEA6415 STV9379FA TDA7269A LM7805/LM7808 24C08 SDA55XX MC44608 TCET1102G TDA9885T

13.1.LM317T

13.1.1.Description

The LM317T is an adjustable 3 terminal positive voltage regulator capable of supplying in excess of 1.5 amps over an output range of 1.25 to 37 volts. This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage. Further, it employs internal current limiting, thermal shutdown and safe area compensation, making it essentially blow–out proof. The LM317 serves a wide variety of applications including local, on card regulation. This device can also be used to make a programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the LM317 can be used as a precision current regulator.

13.1.2.Features

• Output Current in Excess of 1.5 A

• Output Adjustable between 1.2 V and 37 V

• Internal Thermal Overload Protection

• Internal Short Circuit Current Limiting Constant with Temperature

• Output Transistor Safe–Area Compensation

• Floating Operation for High Voltage Applications

• Available in Surface Mount D

PAK, and Standard 3–Lead Transistor Package

• Eliminates Stocking many Fixed Voltages

13.2.TDA1308T

13.2.1.General Description

The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications. It gets its input from two analog audio outputs (DACA_L and DACA_R) of MSP 34x0G. The gain of the output is adjustable by the feedback resistor between the inputs and outputs.

13.2.2.Features

Wide temperature range

•

• No switch ON/OFF clicks

• Excellent power supply ripple rejection

11ak45 27/10/2007

Low power consumption

•

• Short-circuit resistant

• High performance

• high signal-to-noise ratio

• High slew rate

• Low distortion

• Large output voltage swing.

13.2.3.Pinning

SYMBOL PIN DESCRIPTION

OUTA 1 Output A INA(neg) 2 Inverting input A INA(pos) 3 Non-inverting input A V

INB(pos) 5 Non-inverting input B INB(neg) 6 Inverting input B OUTB 7 Output B V

4 Negative supply

8 Positive supply

13.3.MSP34X0G (MSP3410G)

13.3.1.Description

The MSP 34x0G family of single-chip Multi standard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure shows a simplified functional block diagram of the MSP 34x0G.

This new generation of TV sound processing ICs now includes versions for processing the multi channel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments. All MSP 34x0G versions are pin and software downward compatible to the MSP34x0D. The MSP34x0G further simplifies controlling software. Standard selection requires a single I

C transmission only. The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be

11ak45 27/10/2007

evaluated internally with subsequent switching between mono/stereo/bilingual; no I necessary (Automatic Sound Selection).

C interaction is

11ak45 27/10/2007

13.3.2.Features

Standard Selection with single I

C transmission Automatic Standard Detection of terrestrial TV standards Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Two selectable sound IF (SIF) inputs Automatic Carrier Mute function Interrupt output programmable (indicating status change) Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness AVC: Automatic Volume Correction Subwoofer output with programmable low-pass and complementary high-pass filter 5-band graphic equalizer for loudspeaker channel Spatial effect for loudspeaker channel Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs Complete SCART in/out switching matrix

S inputs; one I2S output

Two I Dolby Pro Logic with DPL 351xA coprocessor All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) ASTRA Digital Radio (ADR) together with DRP 3510A All NICAM standards Korean FM-Stereo A2 standard

13.3.3.Pin connections

NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS

Pin No. Pin Name Type

PLCC 68-pin

1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2 - - - - NC LV Not connected 3 15 13 8 7 ADR_DA OUT LV ADR Data Output 4 14 12 7 6 I2S_DA_IN1 IN LV I2S1 data input 5 13 11 6 5 I2S_DA_OUT OUT LV I2S data output 6 12 10 5 4 I2S_WS IN/OUT LV I2S word strobe 7 11 9 4 3 I2S_CL IN/OUT LV I2S clock 8 10 8 3 2 I2C_DA IN/OUT X I2C data 9 9 7 2 1 I2C_CL IN/OUT X I2C data 10 8 - 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN X Stand-by (low-active) 12 6 5 79 62 ADR_SEL IN X I2C bus address select 13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0 14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1 15 3 - 76 59 NC LV Not connected 16 2 - 75 58 NC LV Not connected 17 - - - - NC LV Not connected

18 1 2 74 57 AUD_CL_OUT OUT LV

19 64 1 73 56 TP LV Test pin 20 63 52 72 55 XTAL_OUT OUT X Crystal oscillator 21 62 51 71 54 XTAL_IN IN X Crystal oscillator 22 61 50 70 53 TESTEN IN X Test pin

23 60 49 69 52 ANA_IN2+ IN

24 59 48 68 51 ANA_IN- IN

25 58 47 67 50 ANA_IN1+ IN LV IF input 2 26 57 46 66 49 AVSUP X Analog power supply 5v

- - - 65 - AVSUP X Analog power supply 5v

- - - 64 - NC LV Not connected

PSDIP 64-pin

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

Connection (if not used)

AVSS via 56 pF/LV

Short Description

Audio clock output (18.432 MHz)

IF Input 2 (can be left vacant, only if IF input 1 is also not in use) IF common (can be left vacant, only if IF input 1 is also not in use)

11ak45 27/10/2007

- - - 63 - NC LV Not connected 27 56 45 62 48 AVSS X Analog ground

- - - 61 - AVSS X Analog ground 28 55 44 60 47 MONO_IN IN LV Mono input

- - - 59 - NC LV Not connected

29 54 43 58 46 VREFTOP X

30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right 31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left 32 51 - 55 43 ASG1 AHVSS Analog Shield Ground 1 33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left 35 48 - 52 40 ASG2 AHVSS Analog Shield Ground 2 36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right 37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left 38 45 - 49 37 ASG4 AHVSS Analog Shield Ground 4 39 44 - 48 36 SC4_IN_R IN LV SCART 4 input, right 40 43 - 47 35 SC4_IN_L IN LV SCART 4 input, left 41 - - 46 - NC LV or AHVSS Not connected 42 42 36 45 34 AGNDC X Analog reference voltage 43 41 35 44 33 AHVSS X Analog ground

- - - 43 - AHVSS X Analog ground

- - - 42 - NC LV Not connected

- - - 41 - NC LV Not connected 44 40 34 40 32 CAPL_M X Volume capacitor MAIN 45 39 33 39 31 AHVSUP X Analog power supply 8V 46 38 32 38 30 CAPL_A X Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left 48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right 49 35 29 35 27 VREF1 X Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right 52 - - 32 - NC LV Not connected 53 32 - 31 24 NC LV Not connected 54 31 26 30 23 DACM_SUB OUT LV Subwoofer output 55 30 - 29 22 NC LV Not connected 56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 19 VREF2 X Reference ground 2 59 26 22 25 18 DACA_L OUT LV Headphone out, left 60 25 21 24 17 DACA_R OUT LV Headphone out, right

- - - 23 - NC LV Not connected

- - - 22 - NC LV Not connected 61 24 20 21 16 RESETQ IN X Power-on-reset 62 23 - 20 15 NC LV Not connected 63 22 - 19 14 NC LV Not connected 64 21 19 18 13 NC LV Not connected 65 20 18 17 12 I2S_DA_IN2 IN LV I2S2-data input 66 19 17 16 11 DVSS X Digital ground

- - - 15 - DVSS X Digital ground

- - - 14 - DVSS X Digital ground 67 18 16 13 10 DVSUP X Digital power supply 5V

- - - 12 - DVSUP X Digital power supply 5V

- - - 11 - DVSUP X Digital power supply 5V 68 17 15 10 9 ADR_CL OUT LV ADR clock

Reference voltage IF A/D converter

13.4.VDP313xY

13.4.1.Introduction

The VDP 313xY is a video IC family of high-quality single-chip video processors. Modular design and a sub-micron technology allow the economic integration of features in all classes of TV sets. The VDP 313xY family is based on the VDP 31xxB including YC

RCB inputs for DVD component signals.

The VDP 313xY includes complete video, display and deflection processing. All processing is done digitally, the video frontend and video backend are interfacing to the analog world. Most functions of the VDP can be controlled by software via I

C-Bus interface

11ak45 27/10/2007

13.4.2.Features Video Decoding and Processing

– four CVBS, one S-VHS input, one YC

R C B component input

– integrated high-quality A/D converters and associated clamp and AGC circuits – adaptive 2H comb filter Y/C separator – multistandard colour decoder PAL/NTSC/SECAM including all substandards – multistandard sync decoder – automatic standard recognition – black-line detector – linear horizontal scaling (0.25...4), as well as nonlinear horizontal scaling “Panoramavision” – black-level expander – dynamic peaking – soft limiter (gamma correction) – colour transient improvement

RGB Processing and Deflection

– programmable RGB matrix – two analog RGB / Fastblank inputs – half-contrast switch – picture frame generator – scan velocity modulation output – high-performance H/V deflection – separate ADC for tube measurements – EHT compensation – angle and bow correction – one 20.25 MHz crystal, few external components

C-Bus Interface

–I – 64-pin PSDIP package

13.4.3.Pin Connections and short descriptions

= not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram IN = Input OUT = Output SUPPLY = Supply Pin

Pin no PSDIP 64-pin

1 TEST IN GNDD Test Input 2 RESQ IN X Reset Input 3 SCL IN/OUT X I2C Bus Clock 4 SDA IN/OUT X I2C Bus Data 5 GNDD SUPPLY X Digital Ground 6 HCS IN LV Half Contrast Switch Input 7 FSY OUT LV Front Sync Output 8 CSY OUT LV Composite Sync Output 9 VS OUT LV Vertical Sync Output

10 INTLC OUT LV Intefrace Control Output 11 VPROT IN GNDAB Vertical Protection Input 12 SAFETY IN GNDAB Safety Input 13 HFLB IN HOUT Horizontal Flyback Input 14 GNDD SUPPLY X Digital Ground 15 VSUPD SUPPLY X Digital Supply Voltage (3.3V) 16 GNDD SUPPLY X Digital Ground 17 VSUPD SUPPLY LV Digital Supply Voltage (3.3V) 18 P0 IN/OUT LV Port 1, Bit 0 19 P1 IN/OUT LV Port 1, Bit 1 20 P2 IN/OUT GNDD Port 1, Bit 2 21 P3 IN/OUT GNDD Port 1, Bit 3 22 P4 IN/OUT GNDD Port 1, Bit 4 23 P5 IN/OUT GNDD Port 1, Bit 5 24 P6 IN/OUT GNDD Port 1, Bit 6 25 GNDD SUPPLY X Digital Ground

Pin name Type Connection

(if not used)

Short description

(=VS Bit of MSY for TPU)

11ak45 27/10/2007

26 RSW2 OUT GNDAB Range Switch 2 for Measurement ADC 27 RSW1 OUT GNDAB Range Switch 1 for Measurement ADC 28 SENSE IN GNDAB Sense ADC Input 29 GNDM SUPPLY X Ground, MADC ınput 30 VERTQ OUT LV Inverted Vertical Sawtooth Output 31 VERT OUT LV Vertical Sawtooth Output 32 E/w OUT LV Vertical Parabola Output 33 XREF IN X Reference Input for RGB DACs 34 SVMOUT OUT VSUPAB Analog Scan Velocity Modulation Output 35 GNDAB SUPPLY X Analog Ground Backend 36 VSUPAB SUPPLY X Analog Supply Voltage (5.0V) Backend 37 ROUT OUT VSUPAB Analog Red Output 38 GOUT OUT VSUPAB Analog Green Output 39 BOUT OUT VSUPAB Analog Blue Output 40 VRD IN X DAC Reference 41 RIN IN GNDAB Analog Red Input 42 GIN IN GNDAB Analog Green Input 43 BIN IN GNDAB Analog Blue Input 44 FBLIN IN GNDAB Fast Blank Input 45 RIN2 IN GNDAB Analog Red Input2 46 GIN2 IN GNDAB Analog Green Input2 47 BIN2 IN GNDAB Analog Blue Input2 48 FBLIN2 IN GNDAB Fast Blank Input2 49 CLK20 OUT LV 20.25 MHz System Clock Output 50 HOUT OUT X Horizontal Drive Output 51 XTAL 1 IN X Analog Crystal Input 52 XTAL 2 OUT X Analog Crystal Output 53 CIN 2/CRIN LV Analog Chroma 2/Component CR Input 54 CBIN IN LV Component CB Input 55 GNDAF SUPPLY X Analog Ground Frontend 56 SGND IN GNDAF Signal Ground for Analog Input 57 VRT IN X Reference Voltage Top, Video ADC 58 VSUPAF SUPPLY X Analog Supply Voltage (5.0V) Frontend 59 VOUT OUT LV Analog Video Output 60 CIN1 IN VRT Analog Chroma 1 Input 61 VIN1 IN VRT Analog Video 1 Input 62 VIN2 IN VRT Analog Video 2 Input 63 VIN3 IN VRT Analog Video 3 Input 64 VIN4 IN VRT Analog Video 4 Input

13.5.TEA6415C

13.5.1.General Description

The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 V

DC on the input. Each input can be used as a normal input or as a MAC or

Chroma input (with external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75 load needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration.

13.5.2.Features

• 20MHz Bandwidth

• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)

• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)

• 6 Outputs

• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge

Bus controlled

•

11ak45 27/10/2007

• 6.5dB gain between any input and output

• 55dB crosstalk at 5mHz

• Fully ESD protected

13.5.3.Pinning

Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

2. Data : Low level : -0.3V Max: 1.5V, High level : 3.0V Max : Vcc+0.5V

3. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

4. Clock : Low level : -0.3V Max: 1.5V, High level : 3.0V Max : Vcc+0.5V

5. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

6. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

7. Prog

8. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA

9. Vcc : 12V

10. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

11. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

12. Ground

13. Output : 5.5Vpp, Min : 4.5Vpp

14. Output : 5.5Vpp, Min : 4.5Vpp

15. Output : 5.5Vpp, Min : 4.5Vpp

16. Output : 5.5Vpp, Min : 4.5Vpp

17. Output : 5.5Vpp, Min : 4.5Vpp

18. Output : 5.5Vpp, Min : 4.5Vpp

19. Ground

20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA

13.6.STV9379FA

13.6.1.Description

Designed for monitors and high performance TVs, the STV9379FA vertical deflection booster can handle flyback voltage up to 90V. Further to this, it is possible to have a flyback voltage, which is more than the double of the supply (Pin 2). This allows to decrease the power consumption, or to decrease the flyback time for a given supply voltage. The STV9379FA operates with supplies up to 42V and provides up to 2.6APP output current to drive the yoke. The STV9379FA is offered in HEPTAWATT package.

13.6.2.Features

Power Amplifier Thermal Protection Output Current Up To 2.6

APP

Flyback Voltage Up To 90V (on Pin 5) Suitable For DC Coupling Application External Flyback Supply

13.6.3.Pinning

Pin1 : Output Stage Supply Pin2 : Output Pin3 : GND or Negative Supply Pin4 : Flyback Supply Pin5 : Supply Voltage Pin6 : Inverting Input Pin7 : Non-inverting Input

11ak45 27/10/2007

13.7.TDA7269A

13.7.1.Description

The TDA7269A is class AB dual Audio power amplifier assembled in the Multiwatt package, specially designed for high quality sound application as Hi-Fi music centers and stereo TV sets.

13.7.2.Features

Wide Supply Voltage Range Up To ±20V Split Supply High Output Power 14 + 14W @THD =10%, R

=8,V

= +16V

No Pop at Turn-On/Off Mute (Pop Free) Stand-By Feature (Low I

)

Short Circuit Protection To Gnd Thermal Overload Protection

13.8.LM7800 (LM7805/LM7808)

13.8.1.Description

The L7800 series of three-terminal positive regulators is available in TO-220 TO-220FP TO-3 and D 2 PAK packages and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type employs internal current limiting, thermal shutdown and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.

13.8.2.Features

Output Current Up To 1.5 A Output Voltages of 5; 5.2; 6; 8; 8.5; 9; 12; 15; 18; 24V Thermal Over load protection Short Circuit Protection Output Transition SOA Protection

13.9.AT24C08

13.9.1.Description

The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-pin PDIP, (AT24C01A/02/04/08/16), 8-lead TSSOP (AT24C01A/02/04/08/16) and 8-lead JEDEC SOIC (AT24C01A/02/04/08/16) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to

5.5V) versions.

13.9.2.Features

• Low-voltage and Standard-voltage Operation – 5.0 (V CC = 4.5V to 5.5V) – 2.7 (V CC = 2.7V to 5.5V) – 2.5 (V CC = 2.5V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)

• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)

• 2-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bi-directional Data Transfer Protocol

• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

• Write Protec

11ak45 27/10/2007

t Pin for Hardware Data Protection

• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

• Partial Page Writes are Allowed

• Self-timed Write Cycle (10 ms max)

• High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead JEDEC SOIC, 8-pin PDIP and 8-lead TSSOP Packages

13.9.3.Pin Configurations

Pin name Function

A0-A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect

13.10.SDA5555

13.10.1.General definition

The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking, data pointers, and additional interrupts etc. The onchip display unit for displaying Level 1.5 teletext data can also be used for customer defined on screen displays. Internal XRAM consists of up to 16 Kbytes. Device has an internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS, PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5 TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented characters (DRCS).

13.10.2.Features General

• Feature selection via special function register

• Simultaneous reception of TTX, VPS, PDC, and WSS (line 23)

• Supply Voltage 2.5 and 3.3 V

• ROM version package PSDIP52-2, PMQFP64-1

• Romless version package PMQFP100-2, PLCC84-2

External Cry

stal and Programmable Clock Speed

• Single external 6MHz crystal, all necessary clocks are generated internally

• CPU clock speed selectable via special function registers.

• Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz

Microcontroller Features

• 8bit 8051 instruction set compatible CPU.

• 33.33-MHz internal clock (max.)

• 0.360ms (min.) instruction cycle

• Two 16-bit timers

• Watchdog timer

• Capture compare timer for infrared remote control decoding

• Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)

• ADC (4 channels, 8 bit)

• UART

11ak45 27/10/2007

Memory

• Non-multiplexed 8-bit data and 16 … 20-bit address bus (ROMless Version)

• Memory banking up to 1Mbyte (Romless version)

• Up to 128 Kilobyte on Chip Program ROM

• Eight 16-bit data pointer registers (DPTR)

• 256-bytes on-chip Processor Internal RAM (IRAM)

• 128bytes extended stack memory.

• Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX

• UP to 16KByte on Chip Extended RAM (XRAM) consisting of;

- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX)

- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software

- 3 Kilobyte Display Memory

Display Features

• ROM Character Set Supports all East and West European Languages in single device

• Mosaic Graphic Character Set

• Parallel Display Attributes

• Single/Double Width/Height of Characters

• Variable Flash Rate

• Programmable Screen Size (25 Rows x 33...64 Columns)

• Flexible Character Matrixes (HxV) 12 x 9...16

• Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable Characters in Enhanced Mode

• CLUT with up to 4096 colour combinations

• Up to 16 Colours per DRCS Character

• One out of Eight Colours for Foreground and Background Colours for 1-bit DRCS and ROM Characters

• Shadowing

• Contrast Reduction

• Pixel by Pixel Shiftable Cursor With up to 4 Different Colours

• Support of Progressive Scan and 100 Hz.

• 3 X 4Bits RGB-DACs On-Chip

• Free Programmable Pixel Clock from 10 MHz to 32MHz

• Pixel Clock Independent from CPU Clock

• Multinorm H/V-Display Synchronization in Master or Slave Mode

Acquisition Features

• Multistandard Digital Data Slicer

• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)

• Four Different Framing Codes Available

• Data Caption only Limited by available Memory

• Programmable VBI-buffer

• Full Channel Data Slicing Supported

• Fully Digital Signal Processing

• Noise Measurement and Controlled Noise Compensation

• Attenuation Measurement and Compensation

• Group Delay Measurement and Compensation

• Exact Decoding of Echo Disturbed Signals

Ports

• One 8-bit I/O-port with open drain output and optional I

C Bus emulation support (Port 0)

• Two 8-bit multifunction I/O-ports (Port 1, Port 3)

• One 4-bit port working as digital or analog inputs for the ADC (Port 2)

• One 2-bit I/O port with secondary functions (P4.2, 4.3, 4.7)

• One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)

13.11.MC44608

13.11.1.Description

The MC44608 is a high performance voltage mode controller designed for off–line converters. This high voltage circuit that integrates the start–up current source and the oscillator capacitor, requires few

11ak45 27/10/2007

external components while offering a high flexibility and reliability. The device also features a very high efficiency stand–by management consisting of an effective Pulsed Mode operation. This technique enables the reduction of the stand–by power consumption to approximately 1W while delivering 300mW in a 150W SMPS.

• Integrated Start–Up Current Source

• Lossless Off–Line Start–Up

• Direct Off–Line Operation

• Fast Start–Up

13.11.2.General Features

• Flexibility

Duty Cycle Control

•

• Under voltage Lockout with Hysteresis

• On Chip Oscillator Switching Frequency 40, or 75kHz

• Secondary Control with Few External Components

Protections

• Maximum Duty Cycle Limitation

• Cycle by Cycle Current Limitation

• Demagnetization (Zero Current Detection) Protection

• “Over V

CC Protection” Against Open Loop

• Programmable Low Inertia Over Voltage Protection Against Open Loop

• Internal Thermal Protection

GreenLine

Controller

• Pulsed Mode Techniques for a Very High Efficiency Low Power Mode

• Lossless Startup

• Low dV/dT for Low EMI Radiations

13.11.3.Pin Connections

13.11.4.Pin Function description

Pin Name Description

1 Demag The Demag pin offers 3 different functions: Zero voltage crossing detection (50mV), 24mA current

2 ISENSE The Current Sense pin senses the voltage developed on the series resistor inserted in the source

3 Control Input A feedback current from the secondary side of the SMPS via the opto–coupler is injected into this

4 Ground This pin is the ground of the primary side of the SMPS. 5 Driver The current and slew rate capability of this pin are suited to drive Power MOSFETs. 6 VCC This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes

7 This pin is to provide isolation between the Vi pin 8 and the VCC pin 6. 8 Vi This pin can be directly connected to a 500V voltage source for start–up function of the IC. During

detection and 120mA current detection. The 24mA level is used to detect the secondary reconfiguration status and the 120mA level to detect an Over Voltage status called Quick OVP.

of the power MOSFET. When I sense reaches 1V, the Driver output (pin 5) is disabled. This is known as the Over Current Protection function. A 200mA current source is flowing out of the pin 3 during the start–up phase and during the switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the sense resistor and the pin 3; thus a programmable peak current detection can be performed during the SMPS stand–by mode.

pin. A resistor can be connected between this pin and GND to allow the programming of the Burst duty cycle during the Stand–by mode.

higher than 15V and the operating range is between 6.6V and 13V. An intermediate voltage level of 10V creates a disabling condition called Latched Off phase.

the Start–up phase a 9 mA current source is internally delivered to the VCC pin 6 allowing a rapid charge of the VCC capacitor. As soon as the IC starts–up, this current source is disabled.

11ak45 27/10/2007

13.12.TCET1102G

13.12.1.Description

The TCET110/ TCET2100/ TCET4100 consists of a phototransistor optically coupled to a gallium arsenide infrared-emitting diode in a 4-lead up to 16-lead plastic dual inline package. The elements are

mounted on one lead frame using a coplanar technique, providing a fixed distance between input and

output for highest safety requirements.

13.12.2.Applications

Circuits

for safe protective separation against electrical shock according to safety class II (reinforced

isolation): For appl. class I – IV at mains voltage 300 V For appl. class I – III at mains voltage 600 V

According to VDE 0884, table 2, suitable for: Switch-mode power supplies, line receiver, computer

peripheral interface, microprocessor system interface.

13.12.3.Features VDE 0884 related features:

Rated impulse voltage (transient overvoltage) V Isolation test voltage (partial discharge test voltage) V Rated isolation voltage (RMS includes DC) V Rated recurring peak voltage (repetitive) V

IOTM = 8 kV peak

pd = 1.6 kV

IOWM = 600 V RMS (848 V peak)

IORM = 600 V RMS

General features:

CTR offered in 9 groups Isolation materials according to UL94-VO Pollution degree 2 (DIN/VDE 0110 / resp. IEC 664) Climatic classification 55/100/21 (IEC 68 part 1)

Special construction: Therefore, extra low coupling capacity of typical 0.2pF, high Common Mode Rejection

Low temperature coefficient of CTR G = Leadform 10.16 mm; provides creepage distance > 8 mm, for TCET2100/ TCET4100 optional; suffix letter ‘G’ is not marked on the optocoupler Coupling System U

13.13.TDA9885T

13.13.1.General Description

The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.

13.13.2.Features

• 5 V supply voltage

• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)

• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation,

good intermodulation figures, reduced harmonics, excellent pulse response)

• Gated phase detector for L/L accent standard

• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all

negative and positive modulated standards via I

• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz

• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as

crystal oscillator

• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals

• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC bits via I

• TakeOver Point (TOP) adjustable via I

• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator

• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)

C -bus readable

C-bus or alternatively with potentiometer

C-bus

11ak45 27/10/2007

• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I

• AM demodulator without extra reference circuit

• Alignment-free selective FM-PLL demodulator with high linearity and low noise

C-bus control for all functions

• I

C-bus transceiver with pin programmable Module Address (MAD).

• I

C-bus

13.13.3.Pinning

SYMBOL PIN DESCRIPTION

VIF1 1

VIF2 OP1 FMPLL DEEM AFD DGND AUD TOP SDA SCL SIOMA n.c. TAGC REF VAGC CVBS AGND VPLL

AFC OP2 SIF1 SIF2

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

VIF differential input 1 VIF differential input 2 output 1 (open-collector) FM-PLL for loop filter de-emphasis output for capacitor AF decoupling input for capacitor digital ground audio output tuner AGC TakeOver Point (TOP) I2C-bus data input/output I2C-bus clock input sound intercarrier output and MAD select not connected tuner AGC output 4 MHz crystal or reference input VIF-AGC for capacitor; note 1 video output analog ground VIF-PLL for loop filter supply voltage (+5 V) AFC output output 2 (open-collector) SIF differential input 1 SIF differential input 2

13.14.PI5V330

13.14.1.General Description

The PI5V330 is well suited for video applications when switching composite or RGB analog. A picturein-picture application will be described in this brief. The pixel-rate creates video overlays so two or more pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by superimposing the output of a character generator on a standard composite video background.

11ak45 27/10/2007

+ 49 hidden pages