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TFT LCD Preliminary Specification
MODEL NO.: V470H2 – L03
Customer: _________________________________
Approved by:_______________________________
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Model No.: V470H2-L03
Approval
Note:
TV Product Marketing & Management Div
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
Hsin-nan Chen WT Lin
Prepared By
LCD TV Marketing and Product Management Div.
CY Chang TC Chao
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Model No.: V470H2-L03
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CONTENTS
REVISION HISTORY ......................................................................................................................................................... 4
1. GENERAL DESCRIPTION ............................................................................................................................................ 5
1.1 OVERVIEW .......................................................................................................................................................... 5
1.2 FEATURES........................................................................................................................................................... 5
1.3 APPLICATION ...................................................................................................................................................... 5
1.4 GENERAL SPECIFICATIONS ............................................................................................................................. 5
1.5 MECHANICAL SPECIFICATIONS ....................................................................................................................... 6
2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT ........................................................................................................ 7
2.2 PACKAGE STORAGE .......................................................................................................................................... 8
2.3 ELECTRICAL ABSOLUTE RATINGS .................................................................................................................. 8
2.3.1 TFT LCD MODULE .................................................................................................................................... 8
2.3.2 BACKLIGHT INVERTER UNIT .................................................................................................................. 8
3. ELECTRICAL CHARACTERISTICS ............................................................................................................................. 9
3.1 TFT LCD MODULE .............................................................................................................................................. 9
3.2 BACKLIGHT UNIT .............................................................................................................................................. 12
3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS .............................................................. 12
3.2.2 INVERTER CHARACTERISTICS ............................................................................................................ 12
3.2.3 INVERTER INTERFACE CHARACTERISTICS ...................................................................................... 14
4. BLOCK DIAGRAM OF INTERFACE ........................................................................................................................... 16
4.1 TFT LCD MODULE ............................................................................................................................................ 16
5. INPUT TERMINAL PIN ASSIGNMENT ....................................................................................................................... 17
5.1 TFT LCD Module Input ....................................................................................................................................... 17
5.2 BACKLIGHT UNIT .............................................................................................................................................. 19
5.3 INVERTER UNIT ................................................................................................................................................ 20
5.4 BLOCK DIAGRAM OF INTERFACE .................................................................................................................. 21
5.5 LVDS INTERFACE ............................................................................................................................................. 22
5.6 COLOR DATA INPUT ASSIGNMENT ................................................................................................................ 24
6. INTERFACE TIMING ................................................................................................................................................... 25
6.1 INPUT SIGNAL TIMING SPECIFICATIONS ...................................................................................................... 25
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6.2 POWER ON/OFF SEQUENCE .......................................................................................................................... 28
7. OPTICAL CHARACTERISTICS .................................................................................................................................. 29
7.1 TEST CONDITIONS ........................................................................................................................................... 29
7.2 OPTICAL SPECIFICATIONS ............................................................................................................................. 30
8. PRECAUTIONS ........................................................................................................................................................... 33
8.1 ASSEMBLY AND HANDLING PRECAUTIONS ................................................................................................. 33
8.2 SAFETY PRECAUTIONS .................................................................................................................................. 33
9. DEFINITION OF LABELS ............................................................................................................................................ 34
9.1 CMO MODULE LABEL ...................................................................................................................................... 34
10. PACKAGING.............................................................................................................................................................. 36
10.1 PACKING SPECIFICATIONS ........................................................................................................................... 36
10.2 PACKING METHOD ......................................................................................................................................... 36
11. MECHANICAL CHARACTERISTICS ........................................................................................................................ 38
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REVISION HISTORY
Version D ate
Ver.2.0 Nov. 30, 2009 All
Page
(New)
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Model No.: V470H2-L03
Approval
Section Description
All The approval specification was first issued.
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g (3H)
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V470H2-L03 is a 47” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display true 16.7M colors (8-bit/color). The inverter
module for backlight is built-in.
1.2 FEATURES
Ё High brightness (500 nits)
Ё High contrast ratio (4000:1)
Ё Fast response time (Gray to gray average 6.5 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for response time for 50/60 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHS compliance
1.3 APPLICATION
Ё Standard Living Room TVs.
Ё Public Display Application.
Ё Home Theater Application.
Ё MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1039.68 (H) x584.82 (V) (47” diagonal) mm
Bezel Opening Area 1049(H) x 539 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
(1)
Pixel Pitch(Sub Pixel) 0.5415 (V) x 0.1805 (H) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
Anti-Glare coating (Haze 11%)/
Hard coatin
- (2)
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) - 1096 - mm
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Module Size
Depth (D) - 52.7 - mm
Weight - 12100 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to ˜˸˸ cover.
(1), (2)Vertical (V) - 640 - mm
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
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Value
Unit Note
Min. Max.
X,Y
Shock (Non-Operating) SNOP
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
axis
Z axis 35 G (3), (5)
- 50 G (3), (5)
the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
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Value
Unit Note
Min. Max.
(1)
2.3.2 BACKLIGHT INVERTER UNIT
Value
Item Symbol
Min. Max.
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
Ё
Ё
-0.3 7 V (1), (3)
3000 VRMS
Unit Note
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
CMOS
interface
Note (1) The module should be always operated within the above ranges.
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage |VID| 200
Terminating Resistor RT
Input High Threshold Voltage V
Input Low Threshold Voltage VIL 0
RUSH
ЁЁ
ЁЁ
ЁЁ
V
LVT H
V
LVT L
2.7
IH
+100
Ё Ё
0.48
1.2 1.4 A
0.51
Ё Ё
Ё Ё
Ё
Ё
100
Ё
Ё
4.4 A (2)
Ё
Ё
-100 mV
600 mV
Ё
3.3 V
0.7 V
A
(3) Horizontal Stripe
A
mV
(4)
ohm
Note (2) Measurement condition:
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Model No.: V470H2-L03
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GND
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60 Hz,
whereas a power dissipation check pattern below is displayed.
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a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT UNIT
3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
Lamp Input Voltage VL - 1200 - VRMS Lamp Current IL 8.8 9.3 9.8 mARMS (1)
Lamp Turn On Voltage VS
Operating Frequency FL 40 - 70 KHz
Lamp Life Time LBL 50,000 - Hrs (2)
3.2.2 INVERTER CHARACTERISTICS
- - 2090 VRMS Ta = 0 ºC
- - 1700 VRMS Ta = 25 ºC
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Model No.: V470H2-L03
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Unit Note
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Consumption PBL - 130 138 W (5), IL =9.3mA
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - 5.4 - A Non Dimming
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 37 40 43 kHz
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN - 20 - %
Note (1) Lamp current is measured by utilizing AC current probe
Note (2) The lamp starting voltage V
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
should be applied to the lamp for more than 1 second after startup.
S
Min. Typ. Max.
Value
Unit Note
defined as an area that has equal to or more than 70% brightness compared to the brightness at
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
2к and I
Note (5) The power supply capacity should be higher than the total inverter power consumption P
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 47" backlight unit under input voltage 24V,
average lamp current 9.6 mA and lighting 30 minutes later.
=9.0~ 9.6mArms.
L
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BL
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LCD
Module
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
HV (Pink)
HV (White)
1
2
1
2
1
2
Inverter
1
2
1
2
1
2
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3.2.3 INVERTER INTERFACE CHARACTERISTICS
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Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
MAX
MIN
HI
LO
VIPWM
VEPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Te st
Condition
Ё
Ё
Ё
Min. Typ. Max.
2.0
0
2.85 3.0 3.15 V maximum duty ratio
Ё Ё
Ё
Ё
Ё
Ё
Ё
Ё
2.0
0
3.0 3.3 3.6 V
0
30
30
Ё Ё Ё
Value
Ё
Ё
0
Ё
Ё
Ё
Ё Ё
Ё Ё
Unit Note
5.0 V
0.8 V
Ё
V minimum duty ratio
5.0 V
0.8 V
0.8 V
ms
ms
100 ms
Duty on
Duty off
Normal
Abnormal
10%-90%V
BL
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
on
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё
Ё
Ё
1
100
300
Ё Ё
Ё Ё
Ё Ё
100 ms
50 us
50 us
M
ms
ms
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
Ё
300
300
Ё Ё
Ё Ё
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
Ш PWM signal Ш BLON
Ш PWM signal Ш VBL
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V
VBLON
V
EPWM
V
IPWM
9%/
Toff
Tf1
9
%/
Tr1
BL
0
9
0
%/
2.0V
0.8V
9
Ton
%/
Ton1
Backlight on duration
Tr
Tf
Ext. Dimming Function
TPWMR
PWMF
2.0V
0
0.8V
T
PWM
T
Floating
3.0V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
SELLVDS
ODSEL
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
Vcc
GND
(FI-RE51S-HF (JAE) or equivalent
INPUT CONNECTOR
FRAME
BUFFER
TIMING
CONTROLLER
DC/DC CONVERTER
& REFERENCE
VOLTAGE
GENERATOR
SCAN DRIVER
TFT LCD PANEL
(1920x3x1080)
DATA DRIVER
(Mini-LVDS)
VBL
GND
Status
E_PWM
I_PWM
BLON
CN1
INVERTER
CONNECTOR
CN1:S14B-PH-SM4-TB
(D)(LF) or equivalent
BACKLIGHT
UNIT
CN3-CN26:SM02 (12.0)B-BHS-1-TB(LF)(JST)
or equivalent
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
SELLVDS LVDS data format Selection
7
8 N.C. No Connection (2)
9 ODSEL Overdrive Lookup Table Selection (4)(6)
10 N.C. No Connection (2)
11 GND Ground
ERX0- Even pixel Negative LVDS differential data input. Channel 0
12
ERX0+ Even pixel Positive LVDS differential data input. Channel 0
13
ERX1- Even pixel Negative LVDS differential data input. Channel 1
14
ERX1+ Even pixel Positive LVDS differential data input. Channel 1
15
ERX2- Even pixel Negative LVDS differential data input. Channel 2
16
ERX2+ Even pixel Positive LVDS differential data input. Channel 2
17
18 GND Ground
19 ECLK20 ECLK+
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
21 GND Ground
22 ERX3-
ERX3+ Even pixel Positive LVDS differential data input. Channel 3
23
Even pixel Negative LVDS differential data input. Channel 3
24 N.C. No Connection (2)
25 N.C. No Connection (2)
26 GND Ground
27 GND Ground
28 ORX029 ORX0+
30 ORX1-
Odd pixel Negative LVDS differential data input. Channel 0
Odd pixel Positive LVDS differential data input. Channel 0
Odd pixel Negative LVDS differential data input. Channel 1
31 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
32 ORX233 ORX2+
Odd pixel Negative LVDS differential data input. Channel 2
Odd pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK36 OCLK+
Odd pixel Negative LVDS differential clock input
Odd pixel Positive LVDS differential clock input
37 GND Ground
38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
39
40 N.C. No Connection (2)
41 N.C. No Connection (2)
42 GND Ground
43 GND Ground
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (2)
48 VCC Power input (+12V)
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(2)
(3)(5)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
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49 VCC Power input (+12V)
50 VCC Power input (+12V)
51 VCC Power input (+12V)
Note (1) LVDS connector pin orderdefined as follows
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Note (2) Reserved for internal use. Please leave it open.
Note (3)
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
Low = Open or connect to GND, High = Connect to +3.3V
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
Low = Open or connect to GND: VESA Format, High = Connect to +3.3V: JEIDA Format.
frame rate to optimize image quality.
ODSEL Note
L or open Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
R2
R2
R3
R3
Setting
Setting
Selector (pin7)
R1
R1
TCON
TCON
System side
Note (6) ODSEL signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
LCM sideSystem side
LCM side
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Selector (pin9)
Selector (pin9)
System side
System side
Notes (7) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
R1
R1
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R2
R3
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TCON
TCON
Setting
Setting
LCM side
LCM side
5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN3~CN26: BHR-04VS-1 (JST).
Pin Name Description Wire Color
1 HV High Voltage Pink
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1, manufactured by JST. The
mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF).
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
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5.3 INVERTER UNIT
CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin Symbol Feature
1
2
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3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN3~CN26: SM02(12.0)B-BHS-1-TB(LF)(JST) or equivalent
Pin Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
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G0-EG
0
G0-EG
0
r
0
p
ORx0
O
p
OG0
OB0
C
OG0
OB0
5.4 BLOCK DIAGRAM OF INTERFACE
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Model No.: V470H2-L03
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CNF1
ER0-ER7
E
EB
OR0-OR7
Host
Graphics
Controller
-EB7
DE
-OG7
-OB7
LK
D
7
TxIN
PLL
ERx0+
ERx
-
ERx1+
ERx1-
ERx2+
ERx2-
ERx3+
ERx3-
ECLK+
-
ORx0+
-
ORx1+
ORx1-
100Ө
100pF
100Ө
100Ө
F
100
100Ө
100Ө
100pF
100Ө
100Ө
100pF
100Ө
RxOUT
ER0-ER7
E
-EB7
EB
DE
OR0-OR7
-OG7
7
-OB7
100Ө
100pF
100Ө
PLL
DCLK
Timing
100Ө
100pF
100Ө
100Ө
F
100
Controlle
ORx2+
Rx2-
ORx3+
ORx3-
OCLK+
PLL
LVDS Transmitter
100Ө
100pF
100Ө
100Ө
100pF
100Ө
100Ө
-
100pF
100Ө
LVDS Receiver
PLL
THC63LVDM83A
(LVDF83A)
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ER0~ER7 : Even pixel R data
EG0~EG7 : Even pixel G data
EB0~EB7 : Even pixel B data
OR0~OR7 : Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7 : Odd pixel B data
DE : Data enable signal
DCLK : Data clock signal
Notes (1) The system must have the transmitter to drive the module.
Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
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is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
5.5 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=L or OPEN)
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
Current F\FOH
Current F\FOH
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
G3 G2G4
G3 G2G4
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
R5G0 R4 R3 R2 R1
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
G3 G2G4
G3 G2G4
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R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
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JEDIA LVDS formatΚ(SELLVDS pin=H)
RXCLK
RXCLK
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Current F\FOH
Current F\FOH
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ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
G5 G4G6
G5 G4G6
G5 G4G6
G5 G4G6
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus
data input.
Color
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (253)
Red (254)
Red (255)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (253)
Green (254)
Green (255)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (253)
Blue (254)
Blue (255)
MSB LSB
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
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Red
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
:
:
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
Data Signal
Green
MSB LSB
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Blue
MSB LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency
Input cycle to
LVDS
Receiver
Clock
cycle jitter
Spread spectrum
modulation range
F
Spread spectrum
modulation frequency
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F
clkin
(=1/Tc)
-200
T
rcl
clkin_mod
200 KHz
F
SSM
60 74.25 80 MHz
Ё
F
-2%
clkin
Ё
200 ps (3)
F
+2% MHz
clkin
Issue Date:Nov.30 2009
Model No.: V470H2-L03
Approval
(4)
LVDS
Receiver
Data
Vertical
Active
Display
Te rm
Horizontal
Active
Display
Te rm
Setup Time Tlvsu 600
Hold Time Tlvhd 600
47 50 53 Hz
F
r5
Frame Rate
Fr6 57 60 63 Hz
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Th 1050 1100 1150 Tc
Display Thd 960 960 960 Tc
Blank Thb 90 140 190 Tc
Ё Ё
Ё Ё
ps
(5)
ps
(6)
Tv=Tvd+Tvb
Ё
Ё
Th=Thd+Thb
Ё
Ё
Note (1) ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˼˸˿ʳ˶˿˶˾ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼Κʳ ʳ ʳ
˙
˶˿˾˼ʻ˴ʼʳЊʳ˙ˉʳѼʳ˧ʳѼʳ˧˻ʳ
˙ˈʳѼʳ˧ʳѼʳ˧˻ʳЊʳ˙˶˿˾˼ʻ˼ʼʳ
Note (2) ˧˻˼ʳmodule is operated in DE only mode and please follow the input signal timing diagram beloΚʳ
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INPUT SIGNAL TIMING DIAGRAM
DE
Th
DCLK
Tc
DE
DATA
Tvd
Thb
Tv
Tvb
Thd
Valid display data ( 960 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T
– TI
1
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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
Tc
1T
14
Note (6) : (ODSEL) = H/L or open for 50/60Hz frame rate. Please refer to 5.1 for detail information
3T
14
5T
14
7T
14
9T
14
11T
14
13T
14
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Љ
Љ
Љ
Љ
Љ
P
Љ
Љ
Љ
6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the
diagram below.
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50ms
50ms
4
T
0V
0.5ЉT1Љ10ms
0
0
500ms
2
T
3
T
0.1V
CC
3 T1
T
2
T
0.1V
cc
T4
VALID
LVDS Signals
0V
Power On
0ЉT7ЉT2
8
0
T3
T
T7
8
T
Option Signals
(SELLVDS, ODSEL)
Backlight (Recommended)
T
5
500ms
100msЉT6
50%
T
5
50%
T
6
Power ON/OFF Sequence
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0,that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
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(
)
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Model No.: V470H2-L03
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL
Oscillating Frequency (Inverter) FW
Vertical Frame Rate Fr 60 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
LCD M odule
25r2
50r10
9.3r0.5
40r3
oC
%RH
mA
KHz
LCD P anel
Field of View = 1º
500 mm
CS -2000
Light Shield Room
Ambient
L
uminance < 2 lu x
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
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Contrast Ratio CR
Response Time
Center Luminance of White LC 400 500 - cd/m2Note (4)
White Variation
Cross Talk CT - - 4 % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Gray to
gray
GW
Rx
Ry
Gx 0.272 -
Gy 0.599 -
Bx 0.152 -
By 0.067 -
Wx 0.285 -
Wy 0.293 -
Tx=0q, Ty =0q
Viewing angle
at normal direction
3000 4000 - - Note (2)
- 6.5 12 ms Note (3)
- - 1.3 - Note (6)
Typ.
-0.03
0.634
0.332
Typ.
+0.03
-
-
-
Color Gamut C.G 71 72 - % NTSC
Tx+
Horizontal
Tx-
Viewing Angle
TY+
Vertical
TY-
Note (1) Definition of Viewing Angle (Tx, Ty):
Viewing angles are measured by Eldim EZ-Contrast 160R
CRt20
80 88 -
80 88 -
Deg. Note (1)
80 88 -
80 88 -
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Issue Date:Nov.30 2009
Model No.: V470H2-L03
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Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
Note (3) Definition of Gray-to-Gray Switching Time:
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
The driving signal means the signal of gray level 0, 63, 127, 191, and 255.Gray to gray average
time means the average switching time of gray level 0, 63,127,191,255 to each other.
Note (4) Definition of Luminance of White (LC, LAVE):
Measure the luminance of gray level 255 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
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Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA u 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
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128
Note (6) Definition of White Variation (GW):
Measure the luminance of gray level 255 at 5 points
GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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Issue Date:Nov.30 2009
Model No.: V470H2-L03
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35кat normal humidity without
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
CHI MEI
OPTOELECTRONICS
V470H2 -L03 Rev. XX
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X X X X X X X Y M D L N N N N
Issue Date:Nov.30 2009
Model No.: V470H2-L03
E207943
MADE IN TAIWAN
RoHS
GEMN
Approval
Model Name: V470H2-L03
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
CHI MEI
OPTOELECTRONICS
V470H2 -L03 Rev. XX
X X X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
E207943
MADE IN TAIWAN
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Serial ID includes the information as below:
Manufactured Date:
Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
CMO Internal Use
Revision
CMO Internal Use
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Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
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Issue Date:Nov.30 2009
Model No.: V470H2-L03
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10. PACKAGING
10.1 PACKING SPECIFICATIONS
(1) 3 LCD TV modules / 1 Box
(2) Box dimensions : 1190(L)x280(W)x725(H)mm
(3) Weight : approximately 42 Kg ( 3 modules per box)
10.2 PACKING METHOD
Figures 10-1 and 10-2 are the packing method
LCD TV Module
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Issue Date:Nov.30 2009
Model No.: V470H2-L03
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Anti-static Bag
Carton
PP Belt
Cushion(Bottom)
Figure.10-1 packing method
Carton Label
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(
)
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Issue Date:Nov.30 2009
Model No.: V470H2-L03
Approval
Air Transportation &
Sea / Land Transportation (40ft Container)
(L1130*50*50mm)
Film
(L1150*W1190*H140mm)
(L1400*50*50mm)
Sea / Land Transportation (40ft HQ Container)
(L1130*50*50mm)
(L625*50*50mm)
Film
(L1400*50*50mm)
L1150*W1190*H140mm
Gross: 534kg
Figure.10-2 packing method
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11. MECHANICAL CHARACTERISTICS
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Issue Date:Nov.30 2009
Model No.: V470H2-L03
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࡛ભሽٝڶૻֆ
%*+/'+
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