CHIMEI INNOLUX V470H2-L02 Specification

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TFT LCD Approval Specification

MODEL NO.: V470H2 – L02

Customer: _________________________________

Approved by:_______________________________

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Model No.: V470H2-L02

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Note:

TV Product Marketing & Management Div

Approved By

Chao-Chun Chung

Reviewed By

QA Dept. Product Development Div.

Hsin-nan Chen WT Lin

Prepared By

LCD TV Marketing and Product Management Div.

CY Chang TC Chao

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CONTENTS

REVISION HISTORY ..................................................................................................................................................4

1. GENERAL DESCRIPTION......................................................................................................................................5

1.1 OVERVIEW....................................................................................................................................................5

1.2 FEATURES ....................................................................................................................................................5

1.3 APPLICATION................................................................................................................................................5

1.4 GENERAL SPECIFICATIONS ........................................................................................................................5

2. ABSOLUTE MAXIMUM RATINGS ...........................................................................................................................7

2.1 ABSOLUTE RATINGS OF ENVIRONMENT....................................................................................................7

2.2 PACKAGE STORAGE....................................................................................................................................8

2.3 ELECTRICAL ABSOLUTE RATINGS..............................................................................................................8

2.3.1 TFT LCD MODULE...............................................................................................................................8

2.3.2 BACKLIGHT INVERTER UNIT .............................................................................................................8

3. ELECTRICAL CHARACTERISTICS........................................................................................................................9

3.1 TFT LCD MODULE.........................................................................................................................................9

3.2 BACKLIGHT UNIT........................................................................................................................................ 11

3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS ...........................................................11

3.2.2 INVERTER CHARACTERISTICS ....................................................................................................... 11

3.2.3 INVERTER INTERFACE CHARACTERISTICS...................................................................................13

4. BLOCK DIAGRAM OF INTERFACE ...................................................................................................................... 15

4.1 TFT LCD MODULE.......................................................................................................................................15

5. INPUT TERMINAL PIN ASSIGNMENT..................................................................................................................16

5.1 TFT LCD Module Input .................................................................................................................................16

5.2 BACKLIGHT UNIT........................................................................................................................................ 17

5.3 INVERTER UNIT..........................................................................................................................................18

5.4 BLOCK DIAGRAM OF INTERFACE .............................................................................................................19

5.5 LVDS INTERFACE .......................................................................................................................................20

5.6 COLOR DATA INPUT ASSIGNMENT............................................................................................................22

6. INTERFACE TIMING............................................................................................................................................. 23

6.1 INPUT SIGNAL TIMING SPECIFICATIONS..................................................................................................23

6.2 POWER ON/OFF SEQUENCE..................................................................................................................... 25

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7. OPTICAL CHARACTERISTICS.............................................................................................................................26

7.1 TEST CONDITIONS..................................................................................................................................... 26

7.2 OPTICAL SPECIFICATIONS........................................................................................................................27

8. PRECAUTIONS ....................................................................................................................................................30

8.1 ASSEMBLY AND HANDLING PRECAUTIONS .............................................................................................30

8.2 SAFETY PRECAUTIONS ............................................................................................................................. 30

9. DEFINITION OF LABELS......................................................................................................................................31

9.1 CMO MODULE LABEL.................................................................................................................................31

10. PACKAGING ....................................................................................................................................................... 33

11. MECHANICAL CHARACTERISTICS ...................................................................................................................35

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REVISION HISTORY

Version Date

Ver. 1.0

Jul. 23,
2009

Page
(New)

All

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Section Description

All

The Preliminary specification was first issued.

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Model No.: V470H2-L02

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V470H2-L02 is a 47” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.

This module supports 1920 x 1080 Full HDTV format and can display true 16.7M colors (8-bit/color). The inverter

module for backlight is built-in.

1.2 FEATURES

Ё

High brightness (450 nits)

Ё

High contrast ratio (4000:1)

Ё

Fast response time (Gray to gray average 6.5 ms)

Ё

High color saturation (NTSC 72%)

Ё

Full HDTV (1920 x 1080 pixels) resolution, true HDTV format

Ё

DE (Data Enable) only mode

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Ё

LVDS (Low Voltage Differential Signaling) interface

Ё

Optimized response time for response time for 50/60 Hz frame rate

Ё

Ultra wide viewing angle : Super MVA technology

Ё

RoHS compliance

1.3 APPLICATION

Ё

Standard Living Room TVs.

Ё

Public Display Application.

Ё

Home Theater Application.

Ё

MFM Application.

1.4 GENERAL SPECIFICATIONS

Item Specification Unit Note

Active Area 1039.68 (H) x584.82 (V) (47” diagonal) mm

Bezel Opening Area 1049(H) x 539 (V) mm

Driver Element a-si TFT active matrix - -

Pixel Number 1920 x R.G.B. x 1080 pixel -

(1)

Pixel Pitch(Sub Pixel) 0.5405 (V) x 0.1805 (H) mm -

Pixel Arrangement RGB vertical stripe - -

Display Colors 16.7M color -

Display Operation Mode Transmissive mode / Normally black - -

Surface Treatment

Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.

Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this

feature.

Anti-Glare coating (Haze 11%)/
Hard coating (3H)

- (2)

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1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal (H) - 1096 - mm

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Vertical (V) - 640 - mm Module Size

Depth (D) - 48.5 - mm

Weight - 12300 - g -

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Module Depth is between bezel to T-CON cover.

(1), (2)

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1)

Operating Ambient Temperature TOP 0 50 ºC (1), (2)

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Value

Unit Note

Min. Max.

X,Y

Shock (Non-Operating) SNOP

Vibration (Non-Operating) VNOP - 1.0 G (4), (5)

Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in final product design to prevent the surface temperature of

display area from being over 65 ºC. The range of operating temperature may degrade in case of

improper thermal management in final product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that

Љ

40 ºC).

axis

Z axis 35 G (3), (5)

- 50 G (3), (5)

the module would not be twisted or bent by the fixture.

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2.2 PACKAGE STORAGE

When storing modules as spares for a long time, the following precaution is necessary.

(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to

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store the module with temperature from 0 to 35

(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent

light.

к

at normal humidity without condensation.

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE

Value

Item Symbol

Power Supply Voltage VCC -0.3 13.5 V

Logic Input Voltage VIN -0.3 3.6 V

2.3.2 BACKLIGHT INVERTER UNIT

Item Symbol

Lamp Voltage VW

Min. Max.

Value

Min. Max.

Ё

3000 VRMS

Unit Note

(1)

Unit Note

Power Supply Voltage VBL 0 30 V (1)

Ё

Control Signal Level

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

should be restricted to the conditions described under Normal Operating Conditions.

Note (2) No moisture condensation or freezing.

Note (3) The control signals include On/Off Control and Internal PWM Control.

-0.3 7 V (1), (3)

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE

(Ta = 25 ± 2 ºC)

Parameter Symbol

Power Supply Voltage VCC 10.8 12 13.2 V (1)

Power Supply Ripple Voltage VRP - - 200 mV

Rush Current IRUSH - - 4.4 A (2)

White Pattern - - 0.47 - A

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Value

Unit Note

Min. Typ. Max.

Power Supply Current

LVDS
interface

CMOS
interface

Note (1) The module should be always operated within the above ranges.

Note (2) Measurement condition:

Common Input Voltage VLVC 1.125 1.25 1.375 V

Terminating Resistor RT - 100 - ohm

Input High Threshold Voltage VIH 2.7 - 3.3 V

Input Low Threshold Voltage VIL 0 - 0.7 V

Vertical Stripe

Black Pattern - - 0.46 - A

-

- 1.0 1.2 A

(3)

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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60 Hz,

whereas a power dissipation check pattern below is displayed.

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a. White Pattern

Active Area

c. Vertical Stripe Pattern

b. Black Pattern

Active Area

Active Area

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3.2 BACKLIGHT UNIT

3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS

(Ta = 25 ± 2 ºC)

Value

Parameter Symbol

Min. Typ. Max.

Lamp Input Voltage VL - 1175 - VRMS -

Lamp Current IL 11.0 11.5 12 mARMS (1)

- - 1820 VRMS Ta = 0 ºC

Lamp Turn On Voltage VS

- - 1620 VRMS Ta = 25 ºC

Operating Frequency FL 40 - 70 KHz

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Model No.: V470H2-L02

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Unit Note

Lamp Life Time LBL 50,000 - Hrs (2)

3.2.2 INVERTER CHARACTERISTICS

(Ta = 25 ± 2 ºC)

Value

Parameter Symbol

Min. Typ. Max.

Power Consumption PBL - 163.2 168 W (5), IL =9.3mA

Power Supply Voltage VBL 22.8 24.0 25.2 VDC

Power Supply Current IBL - 6.8 - A Non Dimming

Input Ripple Noise - - - 912 mVP-P VBL=22.8V

Oscillating Frequency FW 37 40 43 kHz

Dimming Frequency FB 150 160 170 Hz

Minimum Duty Ratio DMIN - 20 - %

Note (1) Lamp current is measured by utilizing AC current probe

Unit Note

Note (2) The lamp starting voltage V

Otherwise the lamp may not be turned on.

Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the

display input signals, and it may result in line flow on the display. In order to avoid interference, the

lamp frequency should be detached from the horizontal synchronous frequency and its harmonics

as far as possible.

Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and

the effective discharge length is longer than 80% of its original length (Effective discharge length is

defined as an area that has equal to or more than 70% brightness compared to the brightness at

should be applied to the lamp for more than 1 second after startup.

S

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the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25

2к

and IL =11.0~ 12.0mArms.

Note (5) The measurement condition of Max. value is based on 47" backlight unit under input voltage

24V, average lamp current 11.8 mA and lighting 30 minutes later.

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LCD

Module

HV (Pink)
HV (White)

HV (Pink)
HV (White)

HV (Pink)

HV (White)

HV (Pink)

HV (White)

HV (Pink)

HV (White)

HV (Pink)
HV (White)

1

2

1
2

1
2

Inverter

1

2

1

2

1

2

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3.2.3 INVERTER INTERFACE CHARACTERISTICS

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Parameter Symbol

ON

On/Off Control Voltage

VBLON

OFF

Internal PWM Control
Voltage

External PWM Control
Voltage

MAX

MIN

HI

LO

VIPWM

VEPWM

HI

Status Signal

Status

LO

VBL Rising Time Tr1

VBL Falling Time Tf1

Control Signal Rising Time Tr

Te st

Condition

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Value

Unit Note

Min. Typ. Max.

Ё

2.0

5.0 V

Ё

0

0.8 V

2.85 3.0 3.15 V maximum duty ratio

Ё

0

2.0

0

Ё

Ё

3.0 3.3 3.6 V

0

30

30

Ё

Ё

Ё

Ё

Ё

Ё

5.0 V

0.8 V

0.8 V

Ё

Ё

100 ms

V minimum duty ratio

Duty on

Duty off

Normal

Abnormal

ms

10%-90%V

BL

ms

Control Signal Falling Time Tf

PWM Signal Rising Time TPWMR

PWM Signal Falling Time TPWMF

Input Impedance Rin

PWM Delay Time TPWM

T

on

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Ё

Ё

1

100

300

Ё

100 ms

Ё

50 us

Ё

50 us

Ё

Ё

Ё

Ё

Ё

Ё

MΩ

ms

ms

BLON Delay Time

T

on1

BLON Off Time Toff

Ё

300

300

Ё

Ё

Ё

ms

Ё

ms

Ё

Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to

change the internal/external PWM signal during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure. For a certain

reason, the inverter has a possibility to be damaged with wrong power sequence and control

signal timing.

Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:

Turn ON sequence: VBL

Turn OFF sequence: BLOFF

Ш

PWM signal Ш BLON

Ш

PWM signal Ш VBL

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V

V

V

BL

V

BLON

EPWM

IPWM

9

Toff

%/

Tf1

9

%/

Tr1

9

%/

9

%/

2.0V

0.8V

Ton

Ton1

0

0

Backlight on duration

Tr

Tf

Ext. Dimming Function

T

PWMR

2.0V

0

0.8V

T

PWM

T

PWMF

Floating

3.0V

0

Floating

Int. Dimming Function

V

W

External

PWM

Period

External

PWM Duty

Minimun Duty100%

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(

)

4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

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ERX0(+/-)

ERX1(+/-)

ERX2(+/-)

ERX3(+/-)

ECLK(+/-)

DCLK(+/-)

DE

ORX0(+/-)

ORX1(+/-)

ORX2(+/-)

ORX3(+/-)

OCLK(+/-)

Vcc

GND

(GS13512-1411S-7F or equivalent )

BUFFER

INPUT CONNECTOR

TIMING

CONTROLLER

FRAME

DC/DC CONVERTER

& REFERENCE

VOLTAGE

GENERATOR

SCAN DRIVER

TFT LCD PANEL

(1920x3x1080)

DATA DRIVER

Mini-LVDS

VBL

GND

Status

E_PWM

I_PWM

BLON

CN1

INVERTER

CONNECTOR

CN1:S14B-PH-SM4-TB

(D)(LF) or equivalent

BACKLIGHT

UNIT

CN3-CN26:SM02 (12.0)B-BHS-1-TB(LF)(JST)

or equivalent

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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module Input

Pin Name Description Note

1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection

SELLVDS LVDS data format Selection

7
8 N.C. No Connection (2)

9 ODSEL Overdrive Lookup Table Selection (4)(5)
10 N.C. No Connection (2)
11 N.C.
12
13
14
15
16
17

ERX0- Even pixel Negative LVDS differential data input. Channel 0

ERX0+ Even pixel Positive LVDS differential data input. Channel 0

ERX1- Even pixel Negative LVDS differential data input. Channel 1

ERX1+ Even pixel Positive LVDS differential data input. Channel 1

ERX2- Even pixel Negative LVDS differential data input. Channel 2

ERX2+ Even pixel Positive LVDS differential data input. Channel 2

No Connection (2)

18 GND Ground
19 ECLK­20 ECLK+

Even pixel Negative LVDS differential clock input.

Even pixel Positive LVDS differential clock input.

21 GND Ground
22 ERX3­23 ERX3+

Even pixel Negative LVDS differential data input. Channel 3

Even pixel Positive LVDS differential data input. Channel 3

24 N.C. No Connection (2)
25 N.C. No Connection (2)
26 N.C. No Connection (2)
27 N.C. No Connection (2)
28 ORX0­29 ORX0+
30 ORX1­31 ORX1+
32 ORX2­33 ORX2+

Odd pixel Negative LVDS differential data input. Channel 0

Odd pixel Positive LVDS differential data input. Channel 0

Odd pixel Negative LVDS differential data input. Channel 1

Odd pixel Positive LVDS differential data input. Channel 1

Odd pixel Negative LVDS differential data input. Channel 2

Odd pixel Positive LVDS differential data input. Channel 2

34 GND Ground
35 OCLK­36 OCLK+

Odd pixel Negative LVDS differential clock input

Odd pixel Positive LVDS differential clock input

37 GND Ground
38 ORX3­39 ORX3+

Odd

pixel Negative LVDS differential data input. Channel 3

Odd pixel Positive LVDS differential data input. Channel 3

40 N.C. No Connection (2)
41 N.C. No Connection (2)
42 N.C. No Connection (2)
43 N.C. No Connection (2)
44 GND Ground
45 GND Ground
46 GND Ground
47 GND Ground
48 VCC Power input (+12V)

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(2)

(3)(5)

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p

49 VCC Power input (+12V)
50 VCC Power input (+12V)
51 VCC Power input (+12V)

Note (1) Connector part no.: GS13512-1411S-7F (Foxconn KunShan). or equivalent

Note (2) Please be reserved to open.

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Note (3)

Low : VESA LVDS Format (default), High : JEIDA LVDS Format

.

Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in

accordance to the frame rate to optimize image quality.

ODSEL Note
L or NC Lookup table was optimized for 60 Hz frame rate.

HLooku

table was optimized for 50 Hz frame rate.

Note (5) Low = Open or connect to GND, High = Connect to +3.3V

5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.

CN3~CN26: BHR-04VS-1 (JST).

Pin Name Description Wire Color

1 HV High Voltage Pink

2 HV High Voltage White

Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1, manufactured by JST. The

mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF).

1 HV(White)

2 HV(Pink)

1 HV(White)

2 HV(Pink)

1 HV(White)

2 HV(Pink)

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5.3 INVERTER UNIT

CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent

Pin № Symbol Feature

1

2

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3

4

5

6

7

8

9

10

11 STATUS

12 E_PWM External PWM Control Signal

13 I_PWM Internal PWM Control Signal

14 BLON BL ON/OFF

Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.

VBL +24V

GND GND

Normal (3.3V)
Abnormal(GND)

Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.

Note (3) Pin 12 and Pin 13 can’t open in the same period.

CN3~CN26: SM02(12.0)B-BHS-1-TB(LF)(JST) or equivalent

Pin № Symbol Description

1 CCFL HOT CCFL high voltage

2 CCFL HOT CCFL high voltage

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p

p

OR0

5.4 BLOCK DIAGRAM OF INTERFACE

ER0-ER7

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CNF1

ERx0+

51

Ө

-

100pF

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Preliminary

RxOUT

ER0-ER7

-

-

ERx1+

ERx1-

ERx2+

OR0-OR7

-

-

ERx3+

ERx3-

ECLK+

Host

Graphics

Controller

ORx0+

ORx1+

ORx1-

-

-

-

51

Ө

51Ө

100

F

Ө

51

51

Ө

100pF

51

Ө

51

Ө

100pF

51

Ө

-

-

-OR7

-

-

51

Ө

100pF

51

Ө

Timing

51

Ө

100pF

51

Ө

51Ө

100

F

Controller

LVDS Transmitter

THC63LVDM83A

(LVDF83A)

ORx2+

ORx3+

ORx3-

OCLK+

51

Ө

51
51

51

51

51

100pF

Ө
Ө

100pF

Ө

Ө

100pF

Ө

-

-

LVDS Receiver

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ER0~ER7 : Even pixel R data

EG0~EG7 : Even pixel G data

EB0~EB7 : Even pixel B data

OR0~OR7 : Odd pixel R data

OG0~OG7: Odd pixel G data

OB0~OB7 : Odd pixel B data

DE : Data enable signal

DCLK : Data clock signal

Notes: (1) The system must have the transmitter to drive the module.

(2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it

is used differentially.

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Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

(3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and

the second pixel is even pixel.

5.5 LVDS INTERFACE

VESA LVDS formatΚ(SELLVDS pin=L or OPEN)

RXCLK

RXCLK





ORX0

ORX0

ORX1

ORX1

ORX2

ORX2

ORX3

ORX3

ERX0

ERX0





















Current F\FOH

Current F\FOH

R5G0 R4 R3 R2 R1

R5G0 R4 R3 R2 R1

B0 G5B1

B0 G5B1

R5G0 R4 R3 R2 R1

R5G0 R4 R3 R2 R1

G3 G2G4

G3 G2G4

R0

R0

G1

G1

B2B4 B3B5VS HSDE

B2B4 B3B5VS HSDE

R6G6 R7G7B7 B6RSVD

R6G6 R7G7B7 B6RSVD

R0

R0

ERX1



ERX1



ERX2



ERX2



ERX3



ERX3



B0 G5B1

B0 G5B1

G3 G2G4

G3 G2G4

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G1

G1

B2B4 B3B5VS HSDE

B2B4 B3B5VS HSDE

R6G6 R7G7B7 B6RSVD

R6G6 R7G7B7 B6RSVD

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JEDIA LVDS formatΚ(SELLVDS pin=H)



RXCLK

RXCLK



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Current F\FOH

Current F\FOH

Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

ORX0

ORX0

ORX1

ORX1

ORX2

ORX2

ORX3

ORX3

ERX0

ERX0





ERX1

ERX1

ERX2

ERX2

ERX3

ERX3

R0~R7: Pixel R Data (7; MSB, 0; LSB)

G0~G7: Pixel G Data (7; MSB, 0; LSB)

B0~B7: Pixel B Data (7; MSB, 0; LSB)

DE : Data enable signal

R7G2 R6 R5 R4 R3

R7G2 R6 R5 R4 R3

B2 G7B3

B2 G7B3

R7G2 R6 R5 R4 R3

R7G2 R6 R5 R4 R3

B2 G7B3

B2 G7B3

G5 G4G6

G5 G4G6

G5 G4G6

G5 G4G6

R2

R2

G3

G3

B4B6 B5B7VS HSDE

B4B6 B5B7VS HSDE

R0G0 R1G1B1 B0RSVD

R0G0 R1G1B1 B0RSVD

R2

R2

G3

G3

B4B6 B5B7VS HSDE

B4B6 B5B7VS HSDE

R0G0 R1G1B1 B0RSVD

R0G0 R1G1B1 B0RSVD

DCLK : Data clock signal

Notes: (

1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.

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5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.

The higher the binary input, the brighter the color. The table below provides the assignment of the color versus

data input.

Color

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Black
Red

Green
Basic
Colors

Gray
Scale
Of
Red

Gray
Scale
Of
Green

Gray
Scale
Of
Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Blue

Cyan

Magenta

Yellow

White

Red (0) / Dark

Red (1)

Red (2)

:

:
Red (253)
Red (254)
Red (255)
Green (0) / Dark
Green (1)
Green (2)

:

:
Green (253)
Green (254)
Green (255)
Blue (0) / Dark
Blue (1)
Blue (2)

:

:
Blue (253)
Blue (254)
Blue (255)

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

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Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

Data Signal

Red Green Blue

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

0

0

0

0

0

0

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

:

:

:

:

0

0

0

0

0

0
0

0

0

0

0

0

:

:

:

:

0

0

0

0
0

0

0

0

0

0

0

0

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

:

:

:

:

:

:

:

:

1

1

0

1
1
1

0

1

1

1

1

1

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6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

(Ta = 25 ± 2 ºC)

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

Frequency 1/Tc 60 74.25 80 MH

Clock

Data

Vertical Active
Display Term

Horizontal Active
Display Term

Note (1) (ODSEL) = (H). Please refer to 5.1 for detail information.

Input cycle to cycle jitter Trcl - - 200 ps ­Setup Time Tlvsu 600 - - ps LVDS Receiver
Hold Time Tlvhd 600 - - ps

Fr

Frame Rate

Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb
Display Tvd 1080 1080 1080 Th ­Blank Tvb 35 45 55 Th ­Total Th 1050 1100 1150 Tc Th=Thd+Thb
Display Thd 960 960 960 Tc ­Blank Thb 90 140 190 Tc -

Fr

5

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Model No.: V470H2-L02

Preliminary

Z

47 50 53 Hz (1)
57 60 63 Hz (2)

- LVDS Receiver

(2) (ODSEL) = (L). Please refer to 5.1 for detail information.

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LVDS INPUT INTERFACE TIMING DIAGRAM

RXCLK +

RXn +/-

Tlvsu Tlvhd

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Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

Tc

1T
14

3T
14

5T
14

7T
14

9T
14

11T

14

13T

14

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6.2 POWER ON/OFF SEQUENCE

(Ta = 25 ± 2 ºC)

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the

diagram below.

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Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

10ms

50ms

50ms

ЉЉЉЉ

T4

0V

0.5

ЉЉЉЉ

T

1

ЉЉЉЉ

ЉЉЉЉ

T

2

ЉЉЉЉ

ЉЉЉЉ

T

3

ЉЉЉЉ

0

0

500ms

0.1V

CC

3

T1

T

2

T

0.1V

T4

cc

VALI D

LVDS Signals

0V

Power On

Power Off

0

ЉЉЉЉ

T

7

ЉЉЉЉ

ЉЉЉЉ

T2

T

8

ЉЉЉЉ

T3

T7

8

T

0

Option Signals

(SELLVDS, ODSEL)

Backlight (Recommended)

ЉЉЉЉ

ЉЉЉЉ

T5

T

6

500ms

100ms

50%

5

T

50%

6

T

Note.

Power ON/OFF Sequence

(1) The supply voltage of the external system for the module input should follow the definition of Vcc.

(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the

LCD operation or the LCD turns off before the backlight turns off, the display may momentarily

become abnormal screen. There is no reliability issue when the T5, T6 timing missing the range.

(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.

(4) T4 should be measured after the module has been fully discharged between power off and on

period.

(5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit

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Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

Ambient Temperature Ta

Ambient Humidity Ha

Supply Voltage VCC 12 V

Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"

Lamp Current IL

Oscillating Frequency (Inverter) FW

Vertical Frame Rate Fr 60 Hz

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during

measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1

hour in a windless room.

LCD Module

LCD Panel

25±2

50±10

11.5±0.5

40±3

oC

%RH

mA

KHz

Center of the Screen

Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

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7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

measured under the test conditions described in 7.1 and stable environment shown in 7.1.

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR 3000 4000 - - Note (2)

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Model No.: V470H2-L02

Preliminary

Response Time

Center Luminance of White LC 350 450 - cd/m2Note (4)

White Variation

Cross Talk CT - - 4 % Note (5)

Red

Green

Color
Chromaticity

Blue

White

Gray to

gray

δW

Rx 0.642 -

Ry

Gx 0.272 -

Gy 0.601 -

Bx 0.150 -

By 0.068 -

Wx 0.285 -

Wy

θx=0°, θy =0°

Viewing angle

at normal direction

- 6.5 12 ms Note (3)

- - 1.3 - Note (6)

-

-

Typ.

-0.03

0.334

Typ.

+0.03

0.293

-

Color Gamut C.G

θx+

Horizontal

θx-

Viewing Angle

θY+

Vertical

θY-

Note (1) Definition of Viewing Angle (θx, θy):

Viewing angles are measured by Eldim EZ-Contrast 160R

CR≥20

- 72 - % NTSC

80 88 -

80 88 -

Deg. Note (1)

80 88 -

80 88 -

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Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) =

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).

Note (3) Definition of Gray-to-Gray Switching Time:

pixels whiteall withLuminance Surface
pixels black all withLuminance Surface

The driving signal means the signal of gray level 0, 63, 127, 191, and 255.Gray to gray average

time means the average switching time of gray level 0, 63,127,191,255 to each other.

Note (4) Definition of Luminance of White (LC, LAVE):

Measure the luminance of gray level 255 at center point and 5 points

LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).

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Note (5) Definition of Cross Talk (CT):

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Model No.: V470H2-L02

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CT = | YB – YA | / YA

Where:

YA = Luminance of measured location without gray level 0 pattern (cd/m2)

YB = Luminance of measured location with gray level 0 pattern (cd/m2)

Note (6) Definition of White Variation (

Measure the luminance of gray level 255 at 5 points

×

100 (%)

128

δ

W):

δ

W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Horizontal Line

D

W

4

W

D

4

D

2

1 2

5

3D

4

X

Test point :

X = 1 ~ 5

2

3 4

3W

4

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Model No.: V470H2-L02

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8. PRECAUTIONS

8.1 ASSEMBLY AND HANDLING PRECAUTIONS

[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.

[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.

[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.

[ 6 ] Do not disassemble the module.

[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily

scratched.

[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.

[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.

[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly

к

recommended to store the module with temperature from 0 to 35

condensation.

[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or

fluorescent light.

[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of CCFL will be higher than that of room

temperature.

at normal humidity without

8.2 SAFETY PRECAUTIONS

[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while

assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.

[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of

contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.

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9. DEFINITION OF LABELS

9.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

CHI MEI

OPTOELECTRONICS

V470H2 -L02 Rev. XX

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X X X X X X X Y M D L N N N N

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Model No.: V470H2-L02

Preliminary

E207943

MADE IN TAIWAN

RoHS

GEMN

Model Name: V470H2-L02

Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

Serial ID: X X X X X X X Y M D L N N N N

CHI MEI

OPTOELECTRONICS

V470H2 -L02 Rev. XX

X X X X X X X Y M D L N N N N

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

E207943

MADE IN TAIWAN

MADE IN CHINA

LEOO(or CAPG or CANO)

RoHS

Serial ID includes the information as below:

Manufactured Date:

Year: 0~9, for 2000~2009

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.

CMO Internal Use

Revision

CMO Internal Use

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Revision Code: Cover all the change

Serial No.: Manufacturing sequence of product

Product Line: 1 -> Line1, 2 -> Line 2, …etc.

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Model No.: V470H2-L02

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10. PACKAGING

10.1 PACKING SPECIFICATIONS

(1) 3 LCD TV modules / 1 Box

(2) Box dimensions : 1190(L)x280(W)x725(H)mm

(3) Weight : approximately 42 Kg ( 3 modules per box)

10.2 PACKING METHOD

Figures 10-1 and 10-2 are the packing method

LCD TV Module

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Model No.: V470H2-L02

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Anti-static Bag

Carton

PP Belt

Cushion(Bottom)

Figure.10-1 packing method

Carton Label

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(

)

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Air Transportation &

Sea / Land Transportation (40ft Container)

(L1130*50*50mm)

Film

(L1150*W1190*H140mm)

(L1400*50*50mm)

Sea / Land Transportation (40ft HQ Container)

(L1130*50*50mm)

(L625*50*50mm)

Film

(L1400*50*50mm)

L1150*W1190*H140mm

Gross: 534kg

Figure.10-2 packing method

34

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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

www.panelook.com

Global LCD Panel Exchange Center

11. MECHANICAL CHARACTERISTICS

www.panelook.com

Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

࡛ભሽ՗ٝڶૻֆ׹

CHI MEI

35

Version 1. 0

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

www.panelook.com

Global LCD Panel Exchange Center

www.panelook.com

Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

36

Version 1. 0

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

www.panelook.com

Global LCD Panel Exchange Center

www.panelook.com

Issue Date:Jul.23 2009

Model No.: V470H2-L02

Preliminary

37

Version 1. 0

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

www.panelook.com