CHIMEI INNOLUX V460HK2-PS5 Specification

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MODEL NO.: V460HK2

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PRODUCT SPECIFICATION

ϭ Tentative Specification
Ϯ Preliminary Specification
ϭ Approval Specification

SUFFIX: PS5

Customer:

APPROVED BY SIGNATURE

Name / Title

Note

Please return 1 copy for your confirmation with your signature and
comments.

Approved By Checked By Prepared By

Chao-Chun Chung Ken Wu HT Hung

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PRODUCT SPECIFICATION

CONTENTS

REVISION HISTORY........................................................................................................................................................ 4

1. GENERAL DESCRIPTION ........................................................................................................................................... 5

1.1 OVERVIEW ........................................................................................................................................................ 5

1.2 FEATURES......................................................................................................................................................... 5

1.3 MECHANICAL SPECIFICATIONS .....................................................................................................................5

2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 6

2.1 ABSOLUTE RATINGS OF ENVIRONMENT...................................................................................................... 6

2.2ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)...............................................................................7

2.3 ELECTRICAL ABSOLUTE RATINGS ................................................................................................................7

2.3.1 TFT LCD OPEN CELL............................................................................................................................7

3. ELECTRICAL CHARACTERISTICS............................................................................................................................. 8

3.1 TFT LCD OPEN CELL........................................................................................................................................8

4. BLOCK DIAGRAM OF INTERFACE............................................................................................................................11

4.1 TFT LCD MODULE .......................................................................................................................................... 11

5. INPUT TERMINAL PIN ASSIGNMENT....................................................................................................................... 12

5.1 TFT LCD Module Input .....................................................................................................................................12

5.2 BLOCK DIAGRAM OF INTERFACE................................................................................................................19

5.3 LVDS INTERFACE ...........................................................................................................................................21

5.4COLOR DATA INPUT ASSIGNMENT ...............................................................................................................22

5.5 FLICKER (Vcom) ADJUSTMENT ....................................................................................................................24

6. INTERFACE TIMING .................................................................................................................................................. 25

6.1 INPUT SIGNAL TIMING SPECIFICATIONS (Ta = 25 ± 2 ºC)..........................................................................25

6.1.1 Timing spec for Frame Rate = 100Hz................................................................................................... 25

6.1.2 Timing spec for Frame Rate = 120Hz................................................................................................... 26

6.2 POWER ON/OFF SEQUENCE........................................................................................................................29

6.2.1 POWER ON/OFF SEQUENCE(Ta = 25 ± 2 ºC) ................................................................................... 29

6.2.2 D/3D MODE CHANGE SIGNAL SEQUENCE WITHOUT VCC TURN OFF AND TURN ON..............30

7. OPTICAL CHARACTERISTICS.................................................................................................................................. 31

7.1 TEST CONDITIONS......................................................................................................................................... 31

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PRODUCT SPECIFICATION

7.2 OPTICAL SPECIFICATIONS ...........................................................................................................................32

8. DEFINITION OF LABELS ........................................................................................................................................... 36

8.1 OPEN CELL LABEL .........................................................................................................................................36

8.2 CARTON LABEL ..............................................................................................................................................37

9. PACKAGING ............................................................................................................................................................... 38

9.1 packing specifications ......................................................................................................................................38

9.2 packing Method ................................................................................................................................................38

10. PRECAUTIONS ........................................................................................................................................................ 40

10.1 ASSEMBLY AND HANDLING PRECAUTIONS .............................................................................................40

10.2 SAFETY PRECAUTIONS ..............................................................................................................................40

11. MECHANICAL CHARACTERISTIC .......................................................................................................................... 41

APPENDIX 1: PANEL MODULE DESIGN AND MANUFACTURE REFERENCE GUIDE ............................................. 43

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Version Date Page(New) Section Description

Ver. 1.0 Nov 02, 2011 All All The preliminary specification was first issued.

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PRODUCT SPECIFICATION

REVISION HISTORY

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V460HK2-PS5 is a 46” TFT Liquid Crystal Display product with driver ICs and 4ch-LVDS interface. This product

supports 1920 x 1080 Full HDTV format and can display 1.07G colors ( 8-bit+FRC).

1.2 FEATURES

CHARACTERISTICS ITEMS SPECIFICATIONS

Screen Diagonal [in] 46

Pixels [lines] 1920  1080

Active Area [mm] 1018.08(H) x 572.67(V) (46” diagonal)

Sub-Pixel Pitch [mm] 0.17675(H) x 0.53025(V)

Pixel Arrangement RGB vertical stripe

Weight [g] TYP. 2445g

Physical Size [mm] 1047.76(W)  625.82(H)  1.78(D) Typ.

Display Mode Transmissive mode / Normally black

Contrast Ratio 5000:1 Typ.

Glass thickness (Array / CF) [mm] 0.7 / 0.7

Viewing Angle (CR>20) +88/-88(H), +88/-88(V) Typ. (CRЊ20)

Color Chromaticity * Please refer to “color chromaticity” on p.32

Cell Transparency [%] ˉˁ˅ʸ

Polarizer Surface Treatment Anti-Glare coating (Haze 3.5%), Hard coating (H)

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PRODUCT SPECIFICATION

(Typical value measure at CMI’s module)

(Typical value measure at CMI’s module)

1.3 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Weight 2395 2445 2495 g -

I/F connector mounting position

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Connector mounting position

The mounting inclination of the connector makes the
screen center within  0.5mm as the horizontal.

+/-

(2)

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

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PRODUCT SPECIFICATION

Value

Unit Note

Min. Max.

(1)

Storage Temperature TST -20 +60 ºC

Operating Ambient Temperature TOP 0 50 ºC

Note (1)Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta Љ 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in final product design to prevent the surface temperature

of display area from being over 65 ºC. The range of operating temperature may degrade in case of

improper thermal management in final product design.

With CMI

Module

(1), (2)

With CMI

Module

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PRODUCT SPECIFICATION

2.2ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)

Storage Condition: With shipping package.

Storage temperature range: 25±5 к

Storage humidity range: 50±10%RH

Shelf life: a month

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD OPEN CELL

Item Symbol

Min. Max.

Power Supply Voltage VCC -0.3 13.5 V

Logic Input Voltage VIN -0.3 3.6 V

Value

Unit Note

(1)

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation should

be restricted to the conditions described under Normal Operating Conditions.

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD OPEN CELL

(Ta = 25 ± 2 ºC)

Parameter Symbol

Power Supply Voltage VCC 10.8 12 13.2 V (1)

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PRODUCT SPECIFICATION

Value

Unit Note

Min. Typ. Max.

Rush Current I

White Pattern

Power Supply Current

Horizontal Stripe

Black Pattern

Differential Input High
Threshold Voltage

Differential Input Low
Threshold Voltage

RUSH

ЁЁ

ЁЁ

ЁЁ

V

LVT H

V

LVT L

ЁЁ

0.66 0.79 A

1.49 1.83 A

0.64 0.77 A

+100

ЁЁ

ЁЁ

LVDS

Common Input Voltage VCM 1.0 1.2 1.4 V

interface

Ё

100

Ё

Ё

CMOS

interface

Differential input voltage |VID| 200

Terminating Resistor R

T

Ё

Input High Threshold Voltage VIH 2.7

Input Low Threshold Voltage V

0

IL

Note (1) The module should be always operated within the above ranges.

Note (2) Measurement condition:

3.0 A (2)

(3)

mV

-100 mV

(4)

600 mV

Ё

ohm

3.3 V

0.7 V

Version 1.0

Vcc
(LCD Module Input)

(Low to Hi gh )

Control Signal

SW

+12V

Q1 Si4485DY

Fus e

R1

1k

VR1

47k

C1

0.01uF

R2

Q2

2N7002

1k

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C3

1uF

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GND

Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,

whereas a power dissipation check pattern below is displayed.

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PRODUCT SPECIFICATION

Vcc rising time is 470us

Vcc

0.9Vcc

0.1Vcc

470us

a. White Pattern

Active Area

c. Horizontal Stripe Pattern

b. Black Pattern

Active Area

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g

Note (4) The LVDS input characteristics are as follows:

Mini-LVDS signal: 4path-6pair.

Control signals of data drivers.

(CLK , Data )

Voltages of data drivers.

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PRODUCT SPECIFICATION

Control si

nals and voltages of scan

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d

d

4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

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PRODUCT SPECIFICATION

TFT LCD PANEL

(1920x3x1080)

X(R) Boar

INPUT CONNECTOR

CNF2: WF23-400-413C,

٤ൈ

٤ൈ(FCN),or

٤ൈ٤ൈ

equivalent

CH3_0(+/-)
CH3_1(+/-)
CH3_2(+/-)
CH3_3(+/-)
CH3_4(+/-)
CH3_CLK(+/-)

CH4_0(+/-)
CH4_1(+/-)
CH4_2(+/-)
CH4_3(+/-)
CH4_4(+/-)

+

-

C Board

X(L) Boar

INPUT CONNECTOR

CNF1: WF23-400-513C,

٤ൈ

٤ൈ(FCN),or

٤ൈ٤ൈ

CH1_0(+/-)
CH1_1(+/-)
CH1_2(+/-)
CH1_3(+/-)
CH1_4(+/-)
CH1_CLK(+/-)

CH2_0(+/-)
CH2_1(+/-)
CH2_2(+/-)
CH2_3(+/-)
CH2_4(+/-)
CH2_CLK(+/-)

equivalent

SELLVDS
2D/3D

LD_EN

LR

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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module Input

CNF1 Connector Pin Assignment: (WF23-400-513C,٤ൈ(FCN),or equivalent)

Pin Name Description Note

1 N.C. No Connection (1)

2 SCL EEPROM Serial Clock (for local dimming demo function)

3 SDA EEPROM Serial Data (for local dimming demo function)

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PRODUCT SPECIFICATION

(11)

4 N.C. No Connection

5 L/R_O Output signal for Left Right Glasses control

6 N.C. No Connection (1)

7 SELLVDS LVDS Data Format Selection (2)(7)

8 N.C. No Connection

9 N.C. No Connection

10 N.C. No Connection

11 GND Ground

12 CH1[0]- First pixel Negative LVDS differential data input. Pair 0

13 CH1[0]+ First pixel Positive LVDS differential data input. Pair 0

14 CH1[1]- First pixel Negative LVDS differential data input. Pair 1

15 CH1[1]+ First pixel Positive LVDS differential data input. Pair 1

16 CH1[2]- First pixel Negative LVDS differential data input. Pair 2

17 CH1[2]+ First pixel Positive LVDS differential data input. Pair 2

(1)

(10)

(1)

(9)

18 GND Ground

19 CH1CLK- First pixel Negative LVDS differential clock input.

20 CH1CLK+ First pixel Positive LVDS differential clock input.

21 GND Ground

22 CH1[3]- First pixel Negative LVDS differential data input. Pair 3

23 CH1[3]+ First pixel Positive LVDS differential data input. Pair 3

24 CH1[4]- First pixel Negative LVDS differential data input. Pair 4

25 CH1[4]+ First pixel Positive LVDS differential data input. Pair 4

26 2D/3D Input signal for 2D/3D Mode Selection (3)(6)(8)

27 L/R Input signal for Left Right eye frame synchronous (4)(8)

28 CH2[0]- Second pixel Negative LVDS differential data input. Pair 0

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29 CH2[0]+ Second pixel Positive LVDS differential data input. Pair 0

30 CH2[1]- Second pixel Negative LVDS differential data input. Pair 1

31 CH2[1]+ Second pixel Positive LVDS differential data input. Pair 1

32 CH2[2]- Second pixel Negative LVDS differential data input. Pair 2

33 CH2[2]+ Second pixel Positive LVDS differential data input. Pair 2

34 GND Ground

35 CH2CLK- Second pixel Negative LVDS differential clock input.

36 CH2CLK+ Second pixel Positive LVDS differential clock input.

37 GND Ground

38 CH2[3]- Second pixel Negative LVDS differential data input. Pair 3

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PRODUCT SPECIFICATION

(9)

39 CH2[3]+ Second pixel Positive LVDS differential data input. Pair 3

(9)

40 CH2[4]- Second pixel Negative LVDS differential data input. Pair 4

41 CH2[4]+ Second pixel Positive LVDS differential data input. Pair 4

42 LD_EN Input signal for Local Dimming Enable (5)(7)

43 SCN_EN Input signal for Scanning Enable (6)(8)

44 GND Ground

45 GND Ground

46 GND Ground

47 N.C. No Connection (1)

48 VCC +12V power supply

49 VCC +12V power supply

50 VCC +12V power supply

51 VCC +12V power supply

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CNF2 Connector Pin Assignment (WF23-400-413C,٤ൈ(FCN),or equivalent)

Pin Name Description Note

1 N.C. No Connection

2 N.C. No Connection

3 N.C. No Connection

4 N.C. No Connection

5 N.C. No Connection

6 N.C. No Connection

7 N.C. No Connection

8 N.C. No Connection

9 GND Ground

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PRODUCT SPECIFICATION

(1)

10 CH3[0]- Third pixel Negative LVDS differential data input. Pair 0

11 CH3[0]+ Third pixel Positive LVDS differential data input. Pair 0

12 CH3[1]- Third pixel Negative LVDS differential data input. Pair 1

13 CH3[1]+ Third pixel Positive LVDS differential data input. Pair 1

14 CH3[2]- Third pixel Negative LVDS differential data input. Pair 2

15 CH3[2]+ Third pixel Positive LVDS differential data input. Pair 2

16 GND Ground

17 CH3CLK- Third pixel Negative LVDS differential clock input.

18 CH3CLK+ Third pixel Positive LVDS differential clock input.

19 GND Ground

20 CH3[3]- Third pixel Negative LVDS differential data input. Pair 3

21 CH3[3]+ Third pixel Positive LVDS differential data input. Pair 3

22 CH3[4]- Third pixel Negative LVDS differential data input. Pair 4

23 CH3[4]+ Third pixel Positive LVDS differential data input. Pair 4

(9)

(9)

(9)

24 GND Ground

25 GND Ground

26 CH4[0]- Fourth pixel Negative LVDS differential data input. Pair 0

27 CH4[0]+ Fourth pixel Positive LVDS differential data input. Pair 0

28 CH4[1]- Fourth pixel Negative LVDS differential data input. Pair 1

29 CH4[1]+ Fourth pixel Positive LVDS differential data input. Pair 1

30 CH4[2]- Fourth pixel Negative LVDS differential data input. Pair 2

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31 CH4[2]+ Fourth pixel Positive LVDS differential data input. Pair 2

32 GND Ground

33 CH4CLK- Fourth pixel Negative LVDS differential clock input.

34 CH4CLK+ Fourth pixel Positive LVDS differential clock input.

35 GND Ground

36 CH4[3]- Fourth pixel Negative LVDS differential data input. Pair 3

37 CH4[3]+ Fourth pixel Positive LVDS differential data input. Pair 3

38 CH4[4]- Fourth pixel Negative LVDS differential data input. Pair 4

39 CH4[4]+ Fourth pixel Positive LVDS differential data input. Pair 4

40 GND Ground

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PRODUCT SPECIFICATION

(9)

(9)

41 GND Ground

CN6 Connector Pin Assignment (LM123S-010-H-TF1-3 (UNE) or equivalent)

1 N.C. No Connection

2 N.C. No Connection

3 N.C. No Connection

4 GND Ground

5 N.C. No Connection

6 L/R_O Output signal for Left Right Glasses control

7 N.C. No Connection

8 N.C. No Connection

9 N.C. No Connection

10 N.C. No Connection

(1)

(1)

(10)

(1)

Note (1) Reserved for internal use. Please leave it open.

Note (2) LVDS format selection.

L= Connect to GND, H=Connect to +3.3V or Open

SELLVDS Note

L JEIDA Format

H or Open VESA Format

Note (3) 2D/3D mode selection.

L= Connect to GND or Open, H=Connect to +3.3V

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2D/3D Note

L or Open 2D Mode

H3D Mode

Note (4) Input signal for Left Right eye frame synchronous

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PRODUCT SPECIFICATION

V

Note (5) Local dimming enable selection.

Note (6) Scanning enable selection.

Note (7) SELLVDS, LD_EN signal pin connected to the LCM side has the following diagram.

=0~0.8 V, VIH=2.0~3.3 V

IL

L/R Note

LRi

H Left synchronous signal

L= Connect to GND, H=Connect to +3.3V or Open

LD_EN Note

L Local Dimming Disable

H or Open Local Dimming Enable

L= Connect to GND or Open, H=Connect to +3.3V

SCN_EN Note

L or Open Scanning Disable

H Scanning Enable

R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)

ht synchronous signal

Note (8) 2D/3D, L/R and SCN_EN signal pin connected to the LCM side has the following diagram.

R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)

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Note (9) LVDS 4-port Data Mapping

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PRODUCT SPECIFICATION

Port Channel of LVDS Data Stream

1st Port First Pixel 1, 5, 9, ……1913, 1917

2nd Port Second Pixel 2, 6, 10, ….1914, 1918

3rd Port Third Pixel 3, 7, 11, ….1915, 1919

4th Port Fourth Pixel 4, 8, 12, ….1916, 1920

Note (10) The definition of L/R_O signal as follows

L= 0V , H= +3.3V

L/R_O Note

LRi

H Left glass turn on

Note (11) Please reference Appendix A

ht glass turn on

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Note (12) The screw hole which is distant from the connector is merged with Ground

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PRODUCT SPECIFICATION

!

!

!

!

!

!

!

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5.2 BLOCK DIAGRAM OF INTERFACE

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PRODUCT SPECIFICATION

ARx0 +

ARx0 -

ARx1 +

ARx1 -

ARx2 +

ARx2 -

ARx3 +

ARx3 -

ARx4 +

ARx4 -

ACLK +

ACLK -

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

100pF

100pF

100pF

100pF

100pF

100pF

RxOUT

AR0 Ω AR9

AG0 Ω AG9

AB0 Ω AB9

DE

PLL

BRx0 +

BRx0 -

BRx1 +

BRx1 -

BRx2 +

BRx2 -

BRx3 +

BRx3 -

BRx4 +

BRx4 -

BCLK +

BCLK -

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

51Ω

100pF

100pF

100pF

100pF

100pF

100pF

PLL

BR0 Ω BR9

BG0 Ω BG9

BB0 Ω BB9

DCLK

DCLK
Timing
Controller

LVDS Receiver
(MASTER)

LVDS INPUT

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AR0~AR9: First pixel R data

AG0~AG9: First pixel G data

AB0~AB9: First pixel B data

BR0~BR9: Second pixel R data

BG0~BG9: Second pixel G data

BB0~BB9: Second pixel B data

DE: Data enable signal

DCLK: Data clock signal

The third and fourth pixel are followed the same rules.

CR0~CR9: Third pixel R data

CG0~CG9: Third pixel G data

CB0~CB9: Third pixel B data

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PRODUCT SPECIFICATION

DR0~DR9: Fourth pixel R data

DG0~DG9: Fourth pixel G data

DB0~DB9: Fourth pixel B data

Note (1) A ~ D channel are first, second, third and fourth pixel respectively.

Note (2) The system must have the transmitter to drive the module.

Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is

used differentially.

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5.3 LVDS INTERFACE

JEIDA Format : SELLVDS = L

VESA Format : SELLVDS = H or Open

VESA Format

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PRODUCT SPECIFICATION

Current Cycle

AR 0P

AR 0N

AR 1P

AR 1N

AR 2P

AR 2N

AR 3P

AR 3N

AR 4P
AR 4N

JEIDA Format

AR 0P

AR 0N

AR 1P

AR 1N

AR0

AG1

AB2

AR6

AR4

AG5

AG0 AR5

AB1

DE VS HS AB5 AB4 AB3 AB2

REV AB7 AB6 AG7 AG6 AR7 AR6

REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV

AG4 AR7

AB5

AB0 AG5 AG4 AG3 AG2 AG1

AB4 AG7 AG6 AG5AG9 AG8

AR4 AR3 AR2 AR1 AR0

AR6 AR5 AR4AR9 AR8

AG0

AB1

DE

REV

AG4

AB5

AR 2P

AR 2N

AR 3P

AR 3N

AR 4P
AR 4N

AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)

AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)

AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)

DE : Data enable signal

DCLK : Data clock signal

RSV: Reserved

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AB6

AR2

DE VS HS AB7 AB6AB9 AB8

REV AB3 AB2 AG3 AG2 AR3 AR2

REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV

DE

REV

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5.4COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the color.

The higher the binary input, the brighter the color. The table below provides the assignment of the color versus

data input.

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PRODUCT SPECIFICATION

Data Signal

Basic

Colors

Gray

Scale

Of

Red

Color

Black

Red

Green

Blue

Cyan

Magenta

Yellow

White

Red (0) / Dark

Red (1)

Red (2)

:

:

Red (1021)

Red (1022)

Red Green Blue

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

0

0

0

0

0

0

0

:

:

:

:

;

:

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

1

1

1

0

1

0

0

0

:

:

0

0

Gray

Scale

Of

Green

Gray

Scale

Of

Blue

Red (1023)

Green (0) / Dark

Green (1)

Green (2)

:

:

Green (1021)

Green (1022)

Green (1023)

Blue (0) / Dark

Blue (1)

Blue (2)

:

:

Blue (1021)

Blue (1022)

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

1

:

:

:

:

:

:

0

1

0

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

1

0

0

1

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

:

:

:

:

:

:

1

0

1

1

1

0

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Blue (1023) 00000000000000000000111111111 1

Note (1) 0: Low Level Voltage, 1: High Level Voltage

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PRODUCT SPECIFICATION

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5.5 FLICKER (Vcom) ADJUSTMENT

(1) Adjustment Pattern:

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PRODUCT SPECIFICATION

Flick pattern was shown as below. If customer need below pattern, please directly contact with Account FAE.

. Frame N Frame N+1

!

(2) Adjustment method: (Digital V-com)

Programmable memory IC is used for Digital V-com adjustment in this model. CMI provide Auto Vcom tools to

adjust Digital V-com.The detail connection and setting instruction, please directly

or refer CMI Auto V-com adjustment OI. Below items is suggested to be ready before Digital V-com

contact with Account

FAE

adjustment in customer LCM line.

a. USB Sensor Board.

b. Programmable software

.

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PRODUCT SPECIFICATION

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS (Ta = 25 ± 2 ºC)

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

F

Frequency

clkin

(=1/TC)

60 74.25 80 MHz

LVDS

Input cycle to

cycle jitter

Receiver

Spread spectrum

Clock

modulation range

Spread spectrum

modulation frequency

LVDS

Setup Time Tlvsu 600 - - ps

Receiver

Data

Hold Time Tlvhd 600 - - ps

6.1.1 Timing spec for Frame Rate = 100Hz

Signal Item Symbol Min. Typ. Max. Unit Note

2D mode Fr5 94 100 106 Hz

Frame rate

3D mode F

Total Tv 1090 1350 1395 Th

Vertical

2D Mode

Display Tvd 1080 1080 1080 Th

T

- - 200 ps (3)

rcl

clkin_mo

F

d

F

SSM

F

-2% - F

clkin

+2% MHz

clkin

- - 200 KHz

100 100 100 Hz (7)

r5

Tv=Tvd+Tv

(4)

(5)

b

Ё

Active

Display

Te rm

Horizontal

Active

Display

Te rm

Version 1.0

Blank Tvb 10 270 315 Th

Total Tv 1350 Th

3D Mode

Display Tvd 1080 Th

Blank Tvb 270 Th

Total Th 520 550 670 Tc

2D Mode

Display Thd 480 480 480 Tc

Blank Thb 40 70 190 Tc

Total Th 520 550 670 Tc

3D Mode

Display Thd 480 480 480 Tc

Blank Thb 40 70 190 Tc

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Ё

(6)(8)

Th=Thd+T

hb

Ё

Ё

Th=Thd+T

hb

Ё

Ё

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6.1.2 Timing spec for Frame Rate = 120Hz

Signal Item Symbol Min. Typ. Max. Unit Note

2D mode Fr6 114 120 126 Hz

Frame rate

3D mode F

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PRODUCT SPECIFICATION

120 120 120 Hz (7)

r6

Vertical

Active

Display

Te rm

Horizontal

Active

Display

Te rm

2D Mode

3D Mode

2D Mode

3D Mode

Total Tv 1090 1125 1395 Th

Tv=Tvd+Tv

Display Tvd 1080 1080 1080 Th

Blank Tvb 10 45 315 Th

Ё

Ё

Total Tv 1125 Th

Display Tvd 1080 Th

(6)(8)

Blank Tvb 45 Th

Th=Thd+T

Total Th 520 550 670 Tc

hb

Display Thd 480 480 480 Tc

Blank Thb 40 70 190 Tc

Ё

Ё

Th=Thd+T

Total Th 520 550 670 Tc

hb

Display Thd 480 480 480 Tc

Ё

b

Blank Thb 40 70 190 Tc

Ё

Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low

logic level. Otherwise, this module would operate abnormally.

Note (2) Please make sure the range of pixel clock has follow the below equation:

F

clkin(max)

F

r

5

ʳ

ʳ

Њ F

r

6

Ѽ Tv Ѽ Th

Ѽ Tv Ѽ Th Њ F

clkin(min)

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DE

T

h

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PRODUCT SPECIFICATION

INPUT SIGNAL TIMING DIAGRAM

T

v

T

vd

T

vb

DCLK

T

hd

DE

DAT

Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI

Valid display data ( 480 clocks)

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PRODUCT SPECIFICATION

Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.

Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.

LVDS RECEIVER INTERFACE TIMING DIAGRAM

Tc

RXCLK+/-

RXn+/-

Tlvsu

Tlvhd

1T

3T

5T

7T

9T

11T

13T

14

Note (6) Please fix the Vertical timing (Vertical Total =1350 / Display =1080 / Blank = 270) in 100Hz 3D mode

and Vertical timing (Vertical Total =1125 / Display =1080 / Blank = 45) in 120Hz 3D mode

Note (7)In 3D mode, the set up Fr5 and Fr6 in Typ. ²3 HZ .In order to ensure that the electric function performance

to avoid no display symptom.(Except picture quality symptom.)

Note (8)In 3D mode, the set up Tv and Tvb in Typ. ²30.In order to ensure that the electric function performance to

14

14

14

14

14

14

avoid no display symptom.(Except picture quality symptom.)

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6.2 POWER ON/OFF SEQUENCE

6.2.1 POWER ON/OFF SEQUENCE(Ta = 25 ± 2 ºC)

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram

below.

0.1V

0.5ЉЉЉЉT1ЉЉЉЉ10ms

2

0ЉЉЉЉT

ЉЉЉЉ50ms

3

ЉЉЉЉ50ms

0ЉЉЉЉT

500ms ЉЉЉЉT

0V

4

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PRODUCT SPECIFICATION

CC

T

1

T

2

0.1V

cc

T

3

T

4

LVDS Signals

0V

Power On

0ЉЉЉЉT7ЉЉЉЉT

0ЉЉЉЉT8ЉЉЉЉT

2

3

T

7

Option Signals
(SELLVDS,2D/3D L/R,LD_EN

Backlight (Recommended)

500msЉЉЉЉT

100ms

ЉЉЉЉ

5

T

6

Power ON/OFF Sequence

T

8

,

50%

T

5

50%

6

T

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PRODUCT SPECIFICATION

6.2.2 D/3D MODE CHANGE SIGNAL SEQUENCE WITHOUT VCC TURN OFF AND TURN ON

0.9V

CC

VCC

0.1V

CC

T

1

T

2

0.5ЉЉЉЉT1ЉЉЉЉ10ms

0ЉЉЉЉT

2

ЉЉЉЉ50ms

0V

LVDS Signals

0ЉЉЉЉT10ЉЉЉЉ10ms

0ЉЉЉЉT9ЉЉЉЉ10ms

10ЉЉЉЉT12ЉЉЉЉ20ms

Scalar Black Pattern
Insertion

Backlight ON/OFF
500msЉЉЉЉT
500msЉЉЉЉT11

0ЉЉЉЉT7ЉЉЉЉT2

2D/3D

5

0V

Power On

T

7

Black Pattern

T

10

T

9

T

T

5

11

T

12

Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.

Note (2) Apply the LED voltage within the LCD operation range. When the backlight turns on before the LCD

operation or the LCD turns off before the backlight turns off, the display may momentarily become

abnormal screen.

Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If T2<0,

that maybe cause electrical overstress failure.

Note (4) T4 should be measured after the module has been fully discharged between power off and on period.

Note (5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit

Ambient Temperature Ta

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PRODUCT SPECIFICATION

25±2

o

C

Ambient Humidity Ha

Supply Voltage VCC 12 V

Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"

LED Current IL 130 mA

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during

measuring in a windless room.

50±10

%RH

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PRODUCT SPECIFICATION

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown as below. The following items should be

measured under the test conditions described in 7.1 and stable environment shown in 7.1.

Item Symbol Condition Min. Typ. Max. Unit Note

Rcx

0.654

-

Red

Color

Chromaticity

Green

Blue

Rcy

Gcx

Gcy

Bcx

Bcy

Wcx

θ

=0°, θY =0°

x

Viewing Angle at Normal

Direction

Standard light source “C”

0.329

0.275

0.600

-

-

0.147

0.106

0.320

-

-

­(0)

-

-

-

White

Wcy

Center Transmittance T% - 6.1 - % (1),(6)

Contrast Ratio CR

Gray to

Response Time

with CMI Module@60Hz

White Variation

gray

δW

=0°, θY =0°

θ

x

with CMI module

=0°, θY =0°

θ

x

=0°, θY =0°

θ

x

800

- 6.5 12 (1),(4)

- - 1.3 - (1),(5)

0.365

- - (1),(3)

-

with CMI module

θx+

88

Horizontal

Viewing

-

θ

x

CR≥20

88

Deg. (1),(2)

Angle

θY+

With CMO module

88

Vertical

-

θ

Y

88

Transmission direction

of the up polarizer

ӥ

up-P

- -

90(VA)

- Deg. (7)

135(TN)

135(VA)

slow axis of the QWP

ӥ

up-Q

- ­180(TN)

- Deg. (7)

Note (0) Light source is the standard light source ”C” which is defined by CIE and driving voltage are based on

suitable gamma voltages. The calculating method is as following:

1. Measure Module’s and BLU’s spectrum at center point. White is without signal input and R,G,B are with

signal input. BLU (for V460HK2-PS5) is supplied by CMO.

2. Calculate cell’s spectrum.

3. Calculate cell’s chromaticity by using the spectrum of standard light source “C”.

Note (1) Light source is the BLU which supplied by CMI and driving voltage are based on suitable gamma

voltages.

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Note (2) Definition of Viewing Angle (θx, θy):

Viewing angles are measured by Autronic Conoscope Cono-80 ( or Eldim EZ-Contrast 160R )

www.panelook.com

PRODUCT SPECIFICATION

Normal

θx = θy = 0º

θX- = 90º

6 o’clock

θ

y-

= 90º

Note (3) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) =

L255: Luminance of gray level 255

L 0: Luminance of gray level 0

x-

y-

θy-

θx−

θy+

θx+

12 o’clock

y+

direction

x+

θX+ = 90º

L255of LuminanceSurface

L0 of LuminanceSurface

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (5).

Note (4) Definition of Gray-to-Gray Switching Time: (VA case)

100%

90%

Optical

Response

10%

0%

Gray to gray

switching time

The driving signal means the signal of gray level 0, 124, 252, 380, 508, 636, 764, 892 and 1023.

Gray to gray average time means the average switching time of gray level 0, 124, 252, 380, 508, 636,

764, 892 and 1023 to each other.

Gray to gray

Time

switching time

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k

k

Note (5) Definition of White Variation (δW):

Measure the luminance of gray level 255 at 5 points

δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

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PRODUCT SPECIFICATION

Horizontal Line

D

D/4 D/2 3D/4

12

5

W

W/4

W/2

Vertical Line

3W/4

Note (6) Definition of Transmittance (T%) :

Measure the luminance of gray level 255 at 5 points of LCD module.

Transmittance (T%) =

34

Active Area

(5)] L (4), L (3), L (2), L (1),[L

(5)] L (4), L (3), L (2), L (1),[L

The 5 point is corresponding of the point X at the figure in Note (5).

Note (7) This is a reference for designing the shutter glasses of 3D application.

Definition of the transmission direction of the up polarizer (ӥ

LCD Module:

) and the slow axis of QWP (ӥ

up-P

: Test Point

X

X=1 to 5

unitbacklighof average

moduleLCDof average

100%

×

) on

up-Q

y-

6 o’cloc

x-

12 o’clock

y+

ӥ

x

+

ӥ=0

x-

y-

o

6 o’cloc

12 o’clock

y+

ӥ

up-Q

x

+

ӥ=0

o

Up Polarizer QWP

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The slow axis of the QWP on shutter glasses should be perpendicular to the QWP on LCD Module to get better

3D performance.

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PRODUCT SPECIFICATION

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PRODUCT SPECIFICATION

8.0 DEFINITION OF LABELS

8.1 OPEN CELL LABEL

The barcode nameplate is pasted on each open cell as illustration for CMI internal control.

V460HK2 –PS5 Rev. XX

Model Name: V460HK2-PS5

Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

Serial ID: X X X X X X X Y M D L N N N N

X X X X X X X Y M D L N N N N

Figure.8-1 Serial No. Label on SPWB

Serial No.

Year, Month, Date

CMI Internal Use

Revision

Serial ID includes the information as below:

CMI Internal Use

Manufactured Date:

Year: 2010=0, 2011=1,2012=2…etc.

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.

Revision Code: Cover all the change

Serial No.: Manufacturing sequence of product

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8.2 CARTON LABEL

The barcode nameplate is pasted on each box as illustration, and its definitions are as following explanation.

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PRODUCT SPECIFICATION

P.O. NO.

Part ID. Quantities

Model Name V460HK2-PS5 Rev.

Carton ID.

XXXXXXXYMDXXXX

Carton label includes the information as below:

(a) Model Name: V460HK2– PS5

(b) Carton ID: X X X X X X X Y M D X X X X

Made In Taiwan (Made In China)

RoHS

CMI Internal Use

Year, Month, Date

CMI Internal Use

Revision

CMI Internal Use

Serial ID includes the information as below:

Manufactured Date:

Year: 2010=0, 2011=1,2012=2…etc.

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.

Revision Code: Cover all the change

(c) Quantities: 8

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9. PACKAGING

9.1 packing specifications

(1) 8 LCD TV Panels / 1 Box

(2) Box dimensions : 1260 (L) X960 (W) X99 (H)mm

(3) Weight : approximately 33Kg ( 8 panels per box)

(4) 96 LCD TV Panels / 1 Group

9.2 packing Method

Figures 9-1 and 9-2 are the packing method

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PRODUCT SPECIFICATION

Figure.9-1 packing method

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PRODUCT SPECIFICATION

Figure.9-2 packing method

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PRODUCT SPECIFICATION

10. PRECAUTIONS

10.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the product during assembly.

(2) To assemble backlight or install module into user’s system can be only in clean working areas. The dust

and oil may cause electrical short or worsen the polarizer.

(3) It’s not permitted to have pressure or impulse on the module because the LCD panel will be damaged.

(4) Always follow the correct power sequence when the product is connecting and operating. This can

prevent damage to the CMOS LSI chips during latch-up.

(5) Do not pull the I/F connector in or out while the module is operating.

(6) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(7) It is dangerous that moisture come into or contacted the product, because moisture may damage the

product when it is operating.

(8) High temperature or humidity may reduce the performance of module. Please store this product within

the specified storage conditions.

(9) When ambient temperature is lower than 10ºC may reduce the display quality. For example, the

response time will become slowly.

10.2 SAFETY PRECAUTIONS

(1) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case

of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(2) After the product’s end of life, it is not harmful in case of normal operation and storage.

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11. MECHANICAL CHARACTERISTIC

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PRODUCT SPECIFICATION

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PRODUCT SPECIFICATION

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PRODUCT SPECIFICATION

APPENDIX 1: PANEL MODULE DESIGN AND MANUFACTURE REFERENCE GUIDE

A.1 FFC CONNECTOR

A.2 PCBA GROUNDING

A.3 LCM ASSEMBLY GUIDELINE

ELINE

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