CHIMEI INNOLUX V460H1-LH9 Specification

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MODEL NO.: V460H1 - LH9
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
Customer:
Approved by:
ote:
TV Product Marketing & Management Div
Approved By
Chao-Chun Chung
QA Dept. Product Development Div.
Reviewed By
Hsin-Nan Chen WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
Ken Wu John Yen
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
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CONTENTS
REVISION HISTORY ------------------------------------------------------- 3
1. GENERAL DESCRIPTION
1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
------------------------------------------------------- 4
2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT INVERTER UNIT
3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 7
3.1 TFT LCD MODULE
3.2 BACKLIGHT UNIT
3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS
3.2.2 INVERTER CHARACTERISTICS
3.2.3 INVERTER INTERFACE CHARACTERISTICS
4. BLOCK DIAGRAM ------------------------------------------------------- 15
4.1 TFT LCD MODULE
5. INTERFACE PIN CONNECTION ------------------------------------------------------- 16
5.1 TFT LCD MODULE
5.2 BACKLIGHT UNIT
5.3 INVERTER UNIT
5.4 BLOCK DIAGRAM OF INTERFACE
5.5 LVDS INTERFACE
5.6 COLOR DATA INPUT ASSIGNMENT
6. INTERFACE TIMING ------------------------------------------------------- 25
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 28
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. DEFINITION OF LABELS ------------------------------------------------------- 32
9. PACKAGING
9.1 PACKING SPECIFICATIONS
9.2 PACKING METHOD
------------------------------------------------------- 34
10. PRECAUTIONS ------------------------------------------------------- 37
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
10.2 SAFETY PRECAUTIONS
10.3 SAFETY STANDARDS
11. MECHANICAL CHARACTERISTICS ------------------------------------------------------- 38
12. APPENDIX
------------------------------------------------------- 41
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
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REVISION HISTORY
Version Date
Ver2.0 Feb. 12,’10 All All Approval Specification was first issued.
Page
(New)
Section Description
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V460H1-LH9 is a 46” TFT Liquid Crystal Display module with 14-CCFL Backlight unit and 2ch-LVDS
interface. This module supports 1920 x 1080 HDTV format and can display true 16.7M colors (8-bit/color).
The inverter for backlight is built-in.
1.2 FEATURES
- High brightness (450nits)
- High contrast ratio (6000:1)
- Fast response time (Gray to Gray average 4.5 ms)
- High color saturation (72% NTSC)
- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
- Optimized response time for 120 Hz frame rate
- Ultra wide viewing angle: Super MVA technology
1.3 APPLICATION
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- Standard Living Room TVs.
- Public Display Application.
- Home Theater Application.
- MFM Application.
1.4 GENERAL SPECIFICATI0NS
Item Specification Unit Note Active Area 1018.08(H) x 572.67(V) (46” diagonal) mm Bezel Opening Area 1024.4(H) x 579.2(V) mm Driver Element a-si TFT active matrix - ­Pixel Number 1920x R.G.B. x 1080 pixel ­Pixel Pitch(Sub Pixel) 0.17675(H) x 0.53025(V) mm ­Pixel Arrangement RGB vertical stripe - ­Display Colors 16.7M color ­Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and
back outlines.
Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to
change this feature.
Anti-Glare coating (Haze 11%)
Hardness (3H)
- (2)
(1)
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) - 1083 - mm
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth does not include connectors.
Vertical (V) - 627 - mm
Depth (D) - 51.2 - mm
Weight - 13270 - g -
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
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Item Symbol
Storage Temperature T
Operating Ambient Temperature T
Shock (Non-Operating) S
Vibration (Non-Operating) V
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 ºC).Љ
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in your product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in your product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, and ± Z.
ST
OP
X, Y axis - 50 G (3), (5)
NOP
Z axis - 35 G (3), (5)
NOP
Min. Max.
Value
Unit Note
-20 +60 ºC (1)
0 50 ºC (1), (2)
- 1.0 G (4), (5)
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture. The module would not be twisted or bent by the
fixture.
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10
Storage Range
Temperature (ºC)
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2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
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Item Symbol
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
Value
Unit Note
(1)
2.2.2 BACKLIGHT INVERTER UNIT
Item Symbol
Lamp Voltage V
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
W
Value
Min. Max.
Ё
3000 V
Unit Note
RMS
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)
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Parameter Symbol
Unit Note
Min. Typ. Max.
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Value
Rush Current I
- - 4.5 A (2)
RUSH
White Pattern - 0.9 - A
Power Supply Current
Differential Input High Threshold Voltage Differential Input Low
LVDS Interface
Threshold Voltage
Common Input Voltage V
Differential input voltage (Singled end) Terminating Resistor R
CMOS interface
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage V
Black Pattern - 0.86 - A
Horizontal Stripe
I
CC
(3)
- 1.68 - A
+100 - - mV
V
LVT H
V
- - -100 mV
LVT L
1.0 1.2 1.4 V
CM
|V
| 200 - 600 ohm
ID
- 100 -
T
0 - 0.7 V
IL
(4)
Note (1) The module should be always operated within the above ranges.
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Note (2) Measurement condition:
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GND
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
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Note (3) The specified power supply current is under the conditions at Vcc = 12V, Ta = 25 ± 2 ºC, fv = 60 Hz,
whereas a power dissipation check pattern below is displayed.
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a. White Pattern
Active Area
C. Horizontal Pattern
b. Black Pattern
Active Area
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Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT UNIT
3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC)
Parameter Symbol
Lamp Input Voltage VL - 1100 - V Lamp Current IL 10.5 11.0 11.5 mA
Lamp Turn On Voltage V
Operating Frequency FL 30 - 80 KHz (3) Lamp Life Time LBL 50,000 - - Hrs (4)
3.2.2 INVERTER CHARACTERISTICS (Ta = 25 ± 2 ºC)
S
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Value
Min. Typ. Max.
- - 1820 V
- - 1650 V
Unit Note
RMS
RMS
RMS
Approval
-
RMS
(2), Ta = 0 ºC (2), Ta = 25 ºC
(1)
Parameter Symbol
Unit Note
Min. Typ. Max.
Value
Total Power Consumption P
255
- 156 163
Power Supply Voltage VBL 22.8 24 25.2
Power Supply Current IBL - 6.5 6.8
Input Ripple Noise - - - 912
V (6)
V
Arms No Dimming
kHz
Oscillating Frequency FW 37 40 43 mA H.V (5)
Dimming frequency FB 150 160 170 Hz Dimming frequency
Minimum Duty Ratio D
MIN
- 20 - % Minimum Duty Ratio
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
master and slave board.
Note (2) The lamp starting voltage V
should be applied to the lamp for more than 1 second after startup.
S
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
±2 and Iк
=10.5~ 11.5mArms.
L
Note (5) The power supply capacity should be higher than the total inverter power consumption P
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 46" backlight unit under input voltage 24V,
average lamp current 11.3 mA and lighting 30 minutes later.
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1
A
2
A
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HV (Blue +(-) ) HV (White +(-) )
Inverter
A A
A A
HV (Blue -(+) )
1
HV (White -(+) )
2
HV (Blue +(-) )
1
HV (White +(-) )
2
LCD Module
HV (Blue -(+) )
1
A A
A A
A A
A A
HV (White -(+) )
2
HV (Blue +(-) )
1
HV (White +(-) )
2
HV (Blue -(+) )
1
HV (White -(+) )
2
HV (Blue +(-) )
1
HV (White +(-) )
2
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V
V
V
V
V
V
V
V
A
3.2.3 INVERTER INTERFACE CHARACTERISTICS
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Parameter Symbol
On/Off Control Voltage
Voltage
Voltage
Status Signal
ON
OFF
MAX 2.85 3.0 3.15
MIN
HI 2.0
LO
LO
V
BLON
V
IPWM
V
EPWM
Status
Test
Condition
Ё
Ё
Ё
Ё
Ё
Min. Typ. Max.
2.0 0
Ё
0
0
VBL Rising Time Tr1 Ё 30 ЁЁ ms VBL Falling Time Tf1 Ё 30 ЁЁ ms Control Signal Rising Time Tr Control Signal Falling Time Tf PWM Signal Rising Time T PWM Signal Falling Time T
PWMR
PWMF
Input impedance R PWM Delay Time T
BLON Delay Time
BLON Off Time T
PWM
T
T
on
on1
off
IN
ЁЁЁ
ЁЁЁ
ЁЁЁ
ЁЁЁ
Ё
1
Ё 100 Ё ms Ё 300 ЁЁ ms
Ё
Ё 300 ЁЁЁЁ Ё ms
ЁЁ
Ё 300 ЁЁ ms
alue
Ё
Ё
0
Ё
Ё
Ё
5.0
0.8
Ё
5.0
0.8
0.8
100 ms 100 ms
50 us 50 us
ЁЁ
Unit Note
Maximum duty ratioInternal PWM Control Minimum duty ratio Duty onExternal PWM Control Duty off
10%-90%V
M
bnormal
BL
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
PWM signal BLON
Turn OFF sequence: BLOFF PWM signal VBL
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V
V
V
BL
V
BLON
EPWM
IPWM
9
Toff
%/
Tf1
9
%/
Tr1
9
%/
9
%/
2.0V
0.8V
Ton
Ton1
0
0
Backlight on duration
Tr
Tf
Ext. Dimming Function
T
PWMR
2.0V
0
0.8V
T
PWM
T
PWMF
Floating
3.0V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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R
4.
BLOCK DIAGRAM OF INTERFACE
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4.1 TFT LCD MODULE
ODD_RIN0+/­ODD_RIN1+/­ODD_RIN2+/­ODD_RIN3+/­ODD_RIN4+/­ODD_CLK+/-
EVEN_RIN0+/­EVEN_RIN1+/­EVEN_RIN2+/­EVEN_RIN3+/­EVEN_RIN4+/­EVEN_CLK+/-
RPF MEN MCFG0 MCFG 1 LVDS8b GV_mode SELLVDS ODSE SCL SDA
VCC GND
P-TWO 187059-51221 or equivalent
INPUT CONNECTOR
FRAME
BUFFE
TIMING
ME
CONTROLLER
DC/DC CONVERTER
& REFERENCE VOLTAGE
GENERATOR
SCAN DRIVE
TFT LCD PANEL
(1920x3x1080)
Data Driver (mini-LVDS)
VBL
GND
Status
E_PWM
I_PWM
BLON
INVERTER
CONNECTOR
CN1:
Cvilux
CI0114M1HR0-LA!
or equivalent
CN2-CN8: CP042EP1MFB-LF (Cvilux)
BACKLIGHT
UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module
CNF1 Connector Part No.: 187059-51221 (P-TWO) or equivalent
Pin Name Description
1 RPF Reverse picture function (default low) 2 MEN MEMC function selection 3 MCFG0 MEMC function selection 4 MCFG1 MEMC function selection 5 LVDS8b 8bit/10bit LVDS input selection 6 GV_mode Graphic / Video mode selection 7 SELLVDS LVDS data format Selection 8 SCL I2C CLK Signal
9 SDA. I2C Data Signal 10 ODSEL Overdrive Lookup Table Selection 11 GND Ground 12 ERX0- 2nd pixel Negative LVDS differential data input. Channel 0 13 ERX0+ 2nd pixel Positive LVDS differential data input. Channel 0 14 ERX1- 2nd pixel Negative LVDS differential data input. Channel 1 15 ERX1+ 2nd pixel Positive LVDS differential data input. Channel 1 16 ERX2- 2nd pixel Negative LVDS differential data input. Channel 2 17 ERX2+ 2nd pixel Positive LVDS differential data input. Channel 2 18 GND Ground 19 ECLK- 2nd pixel Negative LVDS differential clock input. 20 ECLK+ 2nd pixel Positive LVDS differential clock input. 21 GND Ground 22 ERX3- 2nd pixel Negative LVDS differential data input. Channel 3
23 ERX3+ 2nd pixel Positive LVDS differential data input. Channel 3 24 ERX4- 2nd pixel Negative LVDS differential data input. Channel 4 25 ERX4+ 2nd pixel Positive LVDS differential data input. Channel 4 26 N.C. No Connection 27 N.C. No Connection 28 ORX0- 1st pixel Negative LVDS differential data input. Channel 0 29 ORX0+ 1st pixel Positive LVDS differential data input. Channel 0 30 ORX1- 1st pixel Negative LVDS differential data input. Channel 1 31 ORX1+ 1st pixel Positive LVDS differential data input. Channel 1 32 ORX2- 1st pixel Negative LVDS differential data input. Channel 2 33 ORX2+ 1st pixel Positive LVDS differential data input. Channel 2 34 GND Ground 35 OCLK- 1st pixel Negative LVDS differential clock input. 36 OCLK+ 1st pixel Positive LVDS differential clock input. 37 GND Ground 38 ORX3- 1st pixel Negative LVDS differential data input. Channel 3 39 ORX3+ 1st pixel Positive LVDS differential data input. Channel 3 40 ORX4- 1st pixel Negative LVDS differential data input. Channel 4 41 ORX4+ 1st pixel Positive LVDS differential data input. Channel 4 42 N.C. No Connection 43 N.C. No Connection 44 GND Ground 45 GND Ground 46 GND Ground 47 N.C. No Connection 48 VCC +12V power supply 49 VCC +12V power supply 50 VCC +12V power supply 51 VCC +12V power supply
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Note
8 5 5 5 6 7 3
4
2 2
2 2
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Note (1) LVDS connector pin orderdefined as follows
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Note (2 ) Reserved for internal use. Please leave it open.
Note (3 )
SELLVDS Mode
L(default) VESA
H JEIDA
L: Connect to GND, H: Connect to +3.3V
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
ODSEL Description
L(default) Lookup table was optimized for 60 Hz frame rate input.
H Lookup table was optimized for 50 Hz frame rate input.
L: Connect to GND, H: Connect to +3.3V
Note (5) Motion Engine (ME) Level & Demo Function Table
Motion engine level must be adjusted after video mode is selected (or entered).
Adjusting the motion engine level in graphic mode has no effect
MEN MCFG1 MCFG0 Notes
Blanking disable 0 0 0 (a)
Blanking
Demo mode (d) 0 1 1 Demo Window
Level
Auto blanking 0 0 1 (b) Blanking enable
Strong 1 0 0 Enable Strong Strong Medium(Default) 1 0 1 Enable Normal Normal
ME
Weak 1 1 0 Enable Weak × OFF 1 1 1 × × ×
0 1 0 (c)
Effect of ME De blur De judder Halo
(e) (f) (g)
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(a) Module re-starts processing video signals from Frontend scaler control board.
(b) During sync unstable period such as format change, 60Hz <-> 50Hz .
MCFG0 can be used to insert blanking of 500ms. This signal is toggled.
(c) Module continues to insert blanking until blanking disable signal is received from frontend scaler board.
(d) Demo window mode: Demo Window appears to the left half of display area. Left side with frame is
120Hz with MEMC, and right side is 120Hz w/o motion compensation.
(e) GPIO (General Purpose I/O) sequence of ME Level: (1) MEN; (2) MCFG1; (3) MCFG0.
GPIO sequence of Blanking Enable, Blanking Disable and Demo window: (1) MCFG1; (2) MCFG0; (3)
MEN.
(f) Each scaler command must be maintained the same voltage level at least 100ms.
(g) 0 : Connect to GND, 1 : +3.3V
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Note (6) 8bit/10bit LVDS input selection
LVDS8b Bit depth
H(default) 8bit
L 10bit
L : Connect to GND, H : Connect to +3.3V
Note (7) Graphic / Video mode selection
There is no prohibited time period for switching between Graphic mode and Video mode.
When this switching signal is input, LCD will be reset and will re-start selected mode.
GV_mode Mode select MEMC ON/OFF
H(default) Graphic mode MEMC OFF
L Video mode MEMC ON
L : Connect to GND, H : Connect to +3.3V
Note (8)
SELLVDS Mode
L(default) Normal Display
H Rotation Display
L: Connect to GND, H: Connect to +3.3V
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)
)
)
)
)
)
5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN2-CN8: CP042ESFA00 (Cvilux)
Pin Name Description Wire Color
1 HV High Voltage Blue
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model CP042ESFA00,
manufactured by Cvilux. The mating header on inverter part number is
CP042EP1MFB-LF (Cvilux)
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1.HV (Blue
2.HV(White
1.HV (Blue
2.HV (White
1.HV (Blue
2.HV (White
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5.3 INVERTER UNIT
CN1: CI0114M1ER0-LA (Cvilux) or equivalent
Symbol Feature
Pin
1
2
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3
4
5
6
7
8
9
10
11
12
13
14
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL +24V
GND GND
STATUS
Normal (3.3V) Abnormal(GND)
E_PWM External PWM Control Signal
I_PWM Internal PWM Control Signal
BLON BL ON/OFF
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN2~CN8: CP042EP1MFB-LF (Cvilux)
Symbol Description
Pin
1
2
CCFL HOT CCFL high voltage
CCFL HOT CCFL high voltage
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5.4 BLOCK DIAGRAM OF INTERFACE
www.panelook.com
Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
ARx0 +
ARx0 -
ARx1 +
ARx1 -
ARx2 +
ARx2 -
ARx3 +
ARx3 -
ARx4 +
ARx4 -
ACLK +
ACLK -
51
51
51
51
51
51
51
51
51
51
51
51
100pF
100pF
100pF
100pF
100pF
100pF
RxOUT
AR0 Ω AR9
AG0 Ω AG9
AB0 Ω AB9
DE
PLL
BRx0 +
BRx0 -
BRx1 +
BRx1 -
BRx2 +
BRx2 -
BRx3 +
BRx3 -
BRx4 +
BRx4 -
BCLK +
BCLK -
51
51
51
51
51
51
51
51
51
51
51
51
100pF
100pF
100pF
100pF
100pF
100pF
PLL
BR0 Ω BR9
BG0 Ω BG9
BB0 Ω BB9
DCLK
DCLK Timing Controller
LVDS Receiver (MASTER)
LVDS INPUT
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
Notes:
 The system must have the transmitter to drive the module.
 LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line
when it is used differentially.
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
 Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel
and the second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
www.panelook.com
Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DE VS HS AB7 AB6AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV
DE
REV
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the
color versus data input.
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black Red
Green Basic Colors
Gray Scale Of Red
Gray Scale Of Green
Gray Scale Of Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
: Red (253) Red (254) Red (255) Green (0) / Dark Green (1) Green (2)
:
: Green (253) Green (254) Green (255) Blue (0) / Dark Blue (1) Blue (2)
:
: Blue (253) Blue (254) Blue (255)
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
Data Signal
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1 1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1 0
0
0
0
0
0 : :
0
0
0
0
0
0
0
0
0
1
1
0 : :
0
1
1
0
1
1
0
0
0
0
0
0
: :
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
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0
5
0
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
Signal Item Symbol Min. Typ. Max. Unit Note
www.panelook.com
Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
LVDS Receiver Clock
LVDS Receiver Data
Vertical Active Display Term
Horizontal Active Display Term
Frequency 1/Tc
Input cycle to cycle jitter Spread spectrum modulation range Spread spectrum modulation frequency
Setup Time Tlvsu
Hold Time Tlvhd
Frame Rate
Total Tv
Display Tvd
Blank Tvb
Total Th
Display Thd
Trcl
clkin_mod
F
F
SSM
Fr6
Fr5
60 74.25 78
ЁЁ
F
-2%
clkin
30
600
600
47 50 53
57 60 62
1080 108
30 45 55
1050
960 960 960
111
MHZ -
200
Ё
Ё
F
clkin
+2%
50
MHz
KHz
ЁЁ
ЁЁ
112
110
0
1135
1080
1150
ps (3)
(4)
ps
ps
Hz
Th Tv=Tvd+Tvb
Th -
Th -
Tc Th=Thd+Thb
Tc -
-
-(5)
(6)
Blank Thb
Note (1) Please make sure the range of frame rate has follow the below equationΚ
Fr(max) Fclkin
Note (2) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
Њ Я Tv×Th Fr(min)Љ
90 140 190
Tc -
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Note (3) The SSCG (Spread spectrum clock generator) is defined as below figures.
www.panelook.com
Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
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6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
0V
0.5ЉЉЉЉT1ЉЉЉЉ10ms
0ЉЉЉЉT
0ЉЉЉЉT
500ms ЉЉЉЉT
LVDS Signals
2Љ
Љ50ms
ЉЉ
3Љ
Љ50ms
ЉЉ
4
0ЉЉЉЉT7ЉЉЉЉT2
0ЉЉЉЉT
8
0V
Option Signals
(SELLVDS,GPIO setting..…)
Backlight (Recommended)
1500msЉЉЉЉT
100msЉЉЉЉT6
5
0.1VCC
Power On
T7
0.1Vcc
T3T1
T2
T4
VA L I D
Power Off
T8
50%
50%
T5
Power ON/OFF Sequence
6
T
Note:
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit Ambient Temperature Ta Ambient Humidity Ha Supply Voltage V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" Lamp Current I Oscillating Frequency (Inverter) F Vertical Frame Rate Fr 120 Hz
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR 4000 6000 - - Note (2)
Response Time
Center Luminance of White L
White Variation Cross Talk CT - - 4 % Note (5)
Red
Color Chromaticity
Viewing Angle
Green
Blue
White
Color Gamut
Horizontal
Vertical
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
o
±2
25
±10
50
CC
L
W
Gray to
gray
C
δW
θ
=0°, θY =0°
Rx 0.633 -
Ry
x
Viewing angle at
normal direction
12V V
11.0±0.5 40±3
- 4.5 9 ms Note (3)
360 450 -
- - 1.3 - Note (7)
0.324 Gx 0.289 ­Gy Bx 0.147 -
Typ.-
0.03
By
0.603
0.050
Typ.+
0.03
Wx 0.285 ­Wy
0.293
72 - % NTSC
θ
+
x
θ
-
x
θ
+
Y
θ
-
Y
CR
20
80 88 ­80 88 ­80 88 ­80 88 -
C
%RH
mA
KHz
cd/
Note (4)
2
m
-
-
Note (6)
-
-
Deg. Note (1)
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Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
Normal
θx = θy = 0º
θ
X-
= 90º
6 o’clock
θ
y-
= 90º
x-
y-
Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note
(7)
θy- θ
θx
y+
θx+
12 o’clock direction
y+
θ
y+
= 90º
x+
θ
X+
= 90º
Note (3) Definition of Gray to Gray Switching Time :
100%
90%
Optical
Response
10%
0%
Gray to gray switching time
Gray to gray switching time
The driving signal means the signal of gray level 0, 63, 127, 191, and 255.
Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each
other .
Time
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A
(
)
A
(
)
(
)
Note (4) Definition of Luminance of White (LC):
Measure the luminance of gray level 255 at center point.
L
= L (5), where L (x) is corresponding to the luminance of the point X at the figure in Note (7).
C
Note (5) Definition of Cross Talk (CT):
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
CT = | Y
– YA | / Y
B
Where:
= Luminance of measured location without gray level 255 pattern (cd/m2)
Y
A
Y
= Luminance of measured location with gray level 255 pattern (cd/m2)
B
ctive Area
Gray 51
Gray 128
Y
(D/8,W/2)
A, L
Y
(D/2,7W/8)
A, D
(0, 0)
Note (6) Measurement Setup:
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt
temperature change during measuring. In order to stabilize the luminance, the measurement
should be executed after lighting backlight for 1 hour in a windless room.
× 100 (%)
A
Y
A, U
Y
A, R
D, W
(D/2,W/8)
(7D/8,W/2)
(D/4,W/4)
Y
(D/8,W/2)
B, L
Y
(D/2,7W/8)
B, D
0, 0
ctive Area
Gray 0
Gray 255
Gray128
Y
(D/2,W/8)
B, U
Y
(7D/8,W/2)
B, R
(3D/4,3W/4)
D, W
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Note (7) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
Horizontal Line
D
D/4 D/2 3D/4
W/4
W/2
W
Vertical Line
3W/4
12
: Test Point
5
34
Active Area
X
X=1 to 5
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8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
CHI MEI
OPTOELECTRONICS
CHI MEI
OPTOELECTRONICS
(a) Model Name: V460H-LH9
V460H1 -LH9 Rev. XX
GEMN
X X X X X X X Y M D L N N N N
V460H1 - LH9 Rev. XX
X X X X X X X Y M D L N N N N
(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
(c) Serial ID: X X
(d) Production Location: XXXX, for example: TAIWAN or CHINA.
X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
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Serial ID includes the information as below:
(a) Manufactured Date: Year: 2003=3, 2004=4….2010=0,2011=1,2012=2…
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1
(b) Revision Code: Cover all the change
(c) Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
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st
to 31st, exclude I ,O, and U.
Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
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9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 3 LCD TV modules / 1 Box
(2) Box dimensions : 1175(L)x 282(W)x 725(H)mm
(3) Weight : approximately 45Kg (3 modules per box)
9.2 PACKING METHOD
Figures 9-1 and 9-2 are the packing method
LCD TV Module
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
Cushion(Bottom)
Anti-static Bag
PP Belt
Carton Label
Figure.9-1 packing method
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Air Transportation &
Sea / Land Transportation (40ft Container)
(L1130*50*50mm)
Film
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
(L1150*W1190*H140mm)
(L1400*50*50mm)
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Sea / Land Transportation (40ft HQ Container)
(L1130*50*50mm)
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Issued Date: Feb. 12, 2010
Model No.: V460H1 - LH9
Approval
(L625*50*50mm)
(L1150*W1190*H140mm)
Film
(L1130*50*50mm)
(L1400*50*50mm)
Figure.9-2 packing method
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10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD
modules in the specified storage conditions.
(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
10.2 SAFETY PRECAUTIONS
(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling
with the inverter. Do not disassemble the module or insert anything into the backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In
case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(3) After the module’s end of life, it is not harmful in case of normal operation and storage.
10.3 SAFETY STANDARDS
The LCD module should be certified with safety regulations as follows:
Regulatory Item Standard
UL UL 60950-1: 2003
Information Technology equipment
Audio/Video Apparatus
If the module displays the same pattern for a long period of time, the phenomenon of image sticking may be
occurred.
cUL CAN/CSA C22.2 No.60950-1-03
CB IEC 60950-1:2001
UL UL 60065: 2003
cUL CAN/CSA C22.2 No.60065-03
CB IEC 60065:2001
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11. MECHANICAL CHARACTERISTIC
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12. APPENDIX – TWO Wire BUS INTRODUCTION
12.1 PIN ASSIGNMENT
51pins LVDS connector
Pin8: SCL
Pin9: SDA
12.2 I2C BUS APPLICATION NOTE
I2C bus: (The I2C bus must for MEMC only or prevent the I2C bus voltage drop down in initial state)
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12.3 TWO WIRE BUS DEVICE ADDRESS
Two wire device address: default is 0x40, 1 byte
Two wire command: the range is 0x00 to 0xFF, 1 byte, see the two wire command table.
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Two wire bus format:
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12.4 TWO WAY TO CONTROL THE TWO WIRE BUS
There are two options to control the two wires bus command.
Two wire bus 6 bytes format
Issued Date: Feb. 12, 2010
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Two wire bus 3 bytes format
Note:
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP
condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the
wired-ANDing of the SCL line can be used to implement handshaking between the master and the slave. The slave
can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the master is too
fast for the slave, or the slave needs extra time for processing between the data transmissions. The slave extending
the SCL low period will not affect the SCL high period, which is determined by the master. As a consequence, the
slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle.
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12.5 TWO WIRE BUS COMMAND TABLE
There is two wire bus command table.
Command Name All OSD Protection 0x00 R/W OSDx Enable Flag Contorl OSD1_Start_Protection 0x01 R/W OSD1 Protection Start Position OSD2_Start_Protection 0x02 R/W OSD2 Protection Start Position OSD3_Start_Protection 0x03 R/W OSD3 Protection Start Position OSD4_Start_Protection 0x04 R/W OSD4 Protection Start Position OSD1_End_Protection 0x05 R/W OSD1 Protection End Position OSD2_End_Protection 0x06 R/W OSD2 Protection End Position OSD3_End_Protection 0x07 R/W OSD3 Protection End Position OSD4_End_Protection 0x08 R/W OSD4 Protection End Position Demo Window 0x09 R/W ME Performance Demo MEMC Level 0x0A R/W ME Performance GV Mode 0x0B R/W ME Operation Blanking 0x0C R/W Blinking the screen RPF 0x0D R/W Rotation picture function
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Access Mode
Description
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Enable All OSD Protection
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OSD # 1~4 Start Protection
OSD # 1~4 End Protection
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Demo Window
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MEMC Level
GV Mode
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Blanking (Enable/Disable)
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Rotation Panel Function
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12.6 TWO WIRE BUS REQUIREMENT
Symbol Parameter Condition Min Max Unit
V
L
V
H
t
r
t
cf
I
i
C
i
f
SCL
R
P
t
HDST A
t
LOW
t
HIGH
t
SU ST A
t
HDDAT
t
SUDAT
t
SU ST O
t
QLF
Input Low-voltage
Input High- voltage
˃˃ˁˊ
˅ˁˊ ˆˁˆ
Rise Time for both SDA and SCL 20 + 0.1C
Output Fall Time from V
Input Current each I/O Pin 0.1VCC < Vi < 0.9V
IHmin
to V
ILmax
10 pF < Cb < 400 pF 20 + 0.1C
CC
ˀ˄˃ ˄˃
Capacitance for each I/O Pin NA
SCL Clock Frequency
Value of Pull-up resistor f
Ho ld Time (re pea t e d) S TAR C o nditio n f
Low Period of the SCL Clock f
High Period of the SCL Clock f
Set-up time for a repeated STAR Condition f
Da ta hold time f
Data setup time f
Se t up time for S TO P C ond itio n f
Bus free time between a STOP and START Condition f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
50KHz
Љ
50KHz
Љ
50KHz
Љ
50KHz
Љ
50KHz
Љ
50KHz
Љ
50KHz
Љ
50KHz
Љ
50KHz
Љ
ˇˈ˃
ˆ˃˃˃
ˇ
ˇˁˊ
ˇ
ˇˁˊ
˃ˆˁˇˈ
˅ˈ˃
ˇ
ˇˁˊ
ˆ˃˃
b
˅ˈ˃
b
˄˃
1000ns/C
NA us
NA us
NA us
NA us
NA ns
NA us
NA us
KHz
b
V
V
ns
ns
uA
pF
Ө
us
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12.7 THE TWO WIRE BUS SEQUENCE
I. Initial state
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II. Stable state
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