CHIMEI INNOLUX V460H1-LH8 Specification

Global LCD Panel Exchange Center

TFT LCD Preliminary Specification

MODEL NO.: V460H1 - LH8

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

TV Product Marketing & Management Div

Approved By

Chao-Chun Chung

Reviewed By

QA Dept. Product Development Div.

Hsin-Nan Chen WT Lin

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Prepared By

LCD TV Marketing and Product Management Div.

Josh Chi Steven Tu

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CONTENTS

REVISION HISTORY

1. GENERAL DESCRIPTION

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

2.2.2 BACKLIGHT INVERTER UNIT

3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE

3.2 BACKLIGHT UNIT

3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS

3.2.2 INVERTER CHARACTERISTICS

3.2.3 INVERTER INTERFACE CHARACTERISTICS

4. BLOCK DIAGRAM

4.1 TFT LCD MODULE

5. INTERFACE PIN CONNECTION

5.1 TFT LCD MODULE

5.2 BACKLIGHT UNIT

5.3 INVERTER UNIT

5.4 BLOCK DIAGRAM OF INTERFACE

5.5 LVDS INTERFACE

5.6 COLOR DATA INPUT ASSIGNMENT

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

6.2 POWER ON/OFF SEQUENCE

7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

7.2 OPTICAL SPECIFICATIONS

8. DEFINITION OF LABELS

9. PACKAGING

9.1 PACKING SPECIFICATIONS

9.2 PACKING METHOD

10. PRECAUTIONS

10.1 ASSEMBLY AND HANDLING PRECAUTIONS

10.2 SAFETY PRECAUTIONS

10.3 SAFETY STANDARDS

11. MECHANICAL CHARACTERISTICS

-------------------------------------------------------

Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

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Version Date

Ver 1.0 Ver 1.1

Dec. 25,’09

Jan. 25,’09

Page

(New)

All

29, 31

Section Description

All 7 Preliminary Specification was first issued.

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Model No.: V460H1 - LH8

Preliminary

REVISION HISTORY

Update OPT data

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V460H1-LH8 is a 46” TFT Liquid Crystal Display module with 14-CCFL Backlight unit and 4ch-LVDS

interface. This module supports 1920 x 1080 HDTV format and can display true 1.073G colors (8bit+Hi-FRC

-bit/color). The inverter for backlight is built-in.

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1.2 FEATURES

- High brightness (450nits)

- High contrast ratio (6000:1)

- Fast response time (Gray to Gray average 4.5 ms)

- High color saturation (72% NTSC)

-Full HDTV (1920 x 1080 pixels) resolution, true HDTV format

DE (Data Enable) only mode

- LVDS (Low Voltage Differential Signaling) interface

- Optimized response time for 120 Hz frame rate

- Ultra wide viewing angle: Super MVA technology

1.3 APPLICATION

- Standard Living Room TVs.

- Public Display Application.

- Home Theater Application.

- MFM Application.

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note Active Area 1018.08(H) x 572.67(V) (46” diagonal) mm Bezel Opening Area 1024.4(H) x 579.2(V) mm Driver Element a-si TFT active matrix - Pixel Number 1920x R.G.B. x 1080 pixel Pixel Pitch(Sub Pixel) 0.17675(H) x 0.53025(V) mm Pixel Arrangement RGB vertical stripe - Display Colors 1.073G color Display Operation Mode Transmissive mode / Normally black - -

Surface Treatment

Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and

Anti-Glare coating (Haze 11%)

Hardness (3H)

- (2)

(1)

back outlines.

Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to

change this feature.

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal (H) - 1083 - mm

Module Size

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Module Depth does not include connectors.

Vertical (V) - 627 - mm

Depth (D) - 51.2 - mm

Weight - 13200 - g -

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Item Symbol

Storage Temperature TST -20 +60 ºC (1)

Operating Ambient Temperature TOP 0 50 ºC (1), (2)

Shock (Non-Operating) S

Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in your product design to prevent the surface temperature

of display area from being over 65 ºC. The range of operating temperature may degrade in case of

improper thermal management in your product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, and ± Z.

Љ

X, Y axis - 50 G (3), (5)

NOP

Z axis - 35 G (3), (5)

- 1.0 G (4), (5)

NOP

Min. Max.

Value

Unit Note

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that

the module would not be twisted or bent by the fixture. The module would not be twisted or bent by the

fixture.

Relative Humidity (%RH)

100

90

80

60

Operating Range

40

20

10

Storage Range

2.2 ELECTRICAL ABSOLUTE RATINGS Temperature (ºC)

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2.2.1 TFT LCD MODULE

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Item Symbol

Min. Max.

Power Supply Voltage VCC -0.3 13.5 V

Logic Input Voltage VIN -0.3 3.6 V

Value

Unit Note

(1)

2.2.2 BACKLIGHT INVERTER UNIT

Item Symbol

Lamp Voltage VW

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

should be restricted to the conditions described under Normal Operating Conditions.

Value

Min. Max.

Ё

3000 V

Unit Note

RMS

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3. ELECTRICAL CHARACTERISTICS

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

3.1 TFT LCD MODULE (

Parameter Symbol

Ta = 25 ± 2 ºC)

Power Supply Voltage VCC

Rush Current I

White Pattern

Power Supply Current

Horizontal Stripe

Black Pattern

Differential Input High Threshold Voltage

Differential Input Low

LVDS interface

Threshold Voltage

Common Input Voltage VCM

Differential input voltage |VID|

RUSH

V

LVT H

V

LVT L

Value

Unit Note

Min. Typ. Max.

10.8 12 13.2 V (1)

- - 4.4 A (2)

-

- 0.51 0.663 A

- 0.93 1.21 A

- 0.45 0.585 A

+100 - -

- - -100

1.0 1.2 1.4 V

200 - 600

mV

(3)

(4)

Terminating Resistor R

Input High Threshold CMOS interface

Voltage

Input Low Threshold

Voltage

Note (1) The module should be always operated within the above ranges.

V

T

IH

IL

- 100 - ohm

2.7 - 3.3 V

0 - 0.7 V

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Note (2) Measurement condition:

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Model No.: V460H1 - LH8

Preliminary

Vcc rising time is 470us

Vcc

0.9Vcc

0.1Vcc

GND

470us

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Note (3) The specified power supply current is under the conditions at Vcc = 12V, Ta = 25 ± 2 ºC, fv = 60 Hz,

whereas a power dissipation check pattern below is displayed.

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Model No.: V460H1 - LH8

Preliminary

a. White Pattern

Active Area

c. Horizontal Stripe Pattern

b. Black Pattern

Active Area

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Note (4) The LVDS input characteristics are as follows:

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3.2 BACKLIGHT UNIT

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Model No.: V460H1 - LH8

Preliminary

3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (

Parameter Symbol

Min. Typ. Max. Lamp Input Voltage VL - 1100 - V Lamp Current IL 10.5 11.0 11.5 mA

Lamp Turn On Voltage VS

- - 1820 V

- - 1650 V

Value

Ta = 25 ± 2 ºC)

Unit Note

-

RMS

(2), Ta = 0 ºC

RMS

(2), Ta = 25 ºC

RMS

(1)

Operating Frequency FL 30 - 80 KHz (3) Lamp Life Time LBL 50,000 - - Hrs (4)

3.2.2 INVERTER CHARACTERISTICS (

Parameter Symbol

Ta = 25 ± 2 ºC)

Val ue

Unit Note

Min. Typ. Max.

Total Power Consumption P

- 156 163

255

Power Supply Voltage VBL 22.8 24 25.2

Power Supply Current IBL - 6.5 6.8

Input Ripple Noise - - - 912

V (6)

V

Arms No Dimming

kHz

Oscillating Frequency FW 37 40 43 mA H.V (5)

Dimming frequency FB 150 160 170 Hz Dimming frequency

Minimum Duty Ratio D

- 20 - % Minimum Duty Ratio

MIN

Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring

master and slave board.

Note (2) The lamp starting voltage V

should be applied to the lamp for more than 1 second after startup.

S

Otherwise the lamp may not be turned on.

Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the

display input signals, and it may result in line flow on the display. In order to avoid interference, the

lamp frequency should be detached from the horizontal synchronous frequency and its harmonics

as far as possible.

Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and

the effective discharge length is longer than 80% of its original length (Effective discharge length is

defined as an area that has equal to or more than 70% brightness compared to the brightness at

the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25

±2 and I

к

Note (5) The power supply capacity should be higher than the total inverter power consumption P

= 10.5~ 11.5mArms.

L

. Since

BL

the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current

changed as PWM duty on and off. The transient response of power supply should be considered

for the changing loading when inverter dimming.

Note (6) The measurement condition of Max. value is based on 46" backlight unit under input voltage 24V,

average lamp current 11.3 mA and lighting 30 minutes later.

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1

A

2

A

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Model No.: V460H1 - LH8

Preliminary

HV (Blue +(-) ) HV (White +(-) )

Inverter

A A

HV (Blue -(+) )

1

HV (White -(+) )

2

HV (Blue +(-) )

1

HV (White +(-) )

2

LCD Module

HV (Blue -(+) )

1

A A

HV (White -(+) )

2

HV (Blue +(-) )

1

HV (White +(-) )

2

HV (Blue -(+) )

1

HV (White -(+) )

2

HV (Blue +(-) )

1

HV (White +(-) )

2

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3.2.3 INVERTER INTERFACE CHARACTERISTICS

Parameter Symbol

On/Off Control Voltage

Voltage

Status Signal

VBL Rising Time Tr1 VBL Falling Time Tf1 Control Signal Rising Time Tr Control Signal Falling Time Tf PWM Signal Rising Time T PWM Signal Falling Time T Input impedance RIN PWM Delay Time T

BLON Delay Time

BLON Off Time T

ON

OFF

MAX 2.85 3.0 3.15 V Maximum duty ratioInternal PWM Control

MIN

HI 2.0

LO

V

BLON

V

IPWM

V

EPWM

Status

PW MR

PW MF

PW M

Ton

T

on1

off

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Tes t

Condition

Ё

30 Ё

Ё

30 Ё

Ё Ё Ё

Ё

100 Ё ms

Ё

300 Ё

ЁЁЁЁ

Ё

300 Ё

Min. Typ. Max.

2.0 0

Ё

0

1

300

Val ue

Ё

0

Ё

Ё Ё

ЁЁЁЁ

Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Unit Note

5.0 V

0.8 V

Ё

5.0 V Duty onExternal PWM Control

0.8 V Duty off

0.8 V Abnormal

Ё

ms

Ё

ms 100 ms 100 ms

50 us 50 us

Ё

ms

Ё

ms

Ё

ms

VMinimum duty ratio

10%-90%V

MΩ

BL

Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to

change the internal/external PWM signal during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure. For a certain

reason, the inverter has a possibility to be damaged with wrong power sequence and control

signal timing.

Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:

Turn ON sequence: VBL

→

PWM signal → BLON

Turn OFF sequence: BLOFF → PWM signal → VBL

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Model No.: V460H1 - LH8

Preliminary

V

BL

V

BLON

EPWM

IPWM

9%/

Toff

Tf1

9

%/

Tr1

9

%/

9

%/

2.0V

0.8V

Ton

Ton1

0

Backlight on duration

Tr

Tf

Ext. Dimming Function

T

PWMR

2.0V

0

0.8V

T

PWM

T

PWMF

Floating

3.0V

0

Floating

Int. Dimming Function

V

W

External

PWM

Period

External

PWM Duty

Minimun Duty100%

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4.

BLOCK DIAGRAM OF INTERFACE

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Model No.: V460H1 - LH8

Preliminary

4.1 TFT LCD MODULE

CH1_0(+/-) CH1_1(+/-) CH1_2(+/-) CH1_3(+/-) CH1_4(+/-) CH1_CLK(+/-)

CH2_0(+/-) CH2_1(+/-) CH2_2(+/-) CH2_3(+/-) CH2_4(+/-) CH2_CLK(+/-)

CH3_0(+/-) CH3_1(+/-) CH3_2(+/-) CH3_3(+/-) CH3_4(+/-) CH3_CLK(+/-)

CH4_0(+/-) CH4_1(+/-) CH4_2(+/-) CH4_3(+/-) CH4_4(+/-)

SELLVDS

Vcc GND

P-TWO 187060-41221+P-TWO 187059-51221 or

SCAN DRIVER

TIMING

CONTROLLER

TFT LCD PANEL

(1920x3x1080)

INPUT CONNECTOR

DATA DRIVER

DC/DC CONVERTER

equivalent

VBL

GND

Status

E_PWM

I_PWM

BLON

INVERTER

CONNECTOR

CN1:

Cvilux

CI0114M1HR0-LA

or equivalent

!

CN2-CN8: CP042EP1MFB-LF (Cvilux)

BACKLIGHT

UNIT

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5 .INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module

CNF3

Connector Pin Assignment (187060-41221(P-TWO) or equivalent)

Pin Name Description Note

1 GND Ground 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 N.C. No Connection 6 N.C. No Connection 7 N.C. No Connection 8 N.C. No Connection

9 GND Ground 10 CH3_0N Third Pixel Negative LVDS differential data input. Channel 0 11 CH3_0P Third Pixel Positive LVDS differential data input. Channel 0 12 CH3_1N Third Pixel Negative LVDS differential data input. Channel 1 13 CH3_1P Third Pixel Positive LVDS differential data input. Channel 1 14 CH3_2N Third Pixel Negative LVDS differential data input. Channel 2 15 CH3_2P Third Pixel Positive LVDS differential data input. Channel 2 16 GND Ground 17 CH3_CLKN 18 CH3_CLKP 19 GND Ground 20 CH3_3N Third Pixel Negative LVDS differential data input. Channel 3 21 CH3_3P Third Pixel Positive LVDS differential data input. Channel 3 22 CH3_4N Third Pixel Negative LVDS differential data input. Channel 4 23 CH3_4P Third Pixel Positive LVDS differential data input. Channel 4 24 N.C. No Connection 25 N.C. No Connection 26 CH4_0N Fourth Pixel Negative LVDS differential data input. Channel 0 27 CH4_0P Fourth Pixel Positive LVDS differential data input. Channel 0 28 CH4_1N Fourth Pixel Negative LVDS differential data input. Channel 1 29 CH4_1P Fourth Pixel Positive LVDS differential data input. Channel 1 30 CH4_2N Fourth Pixel Negative LVDS differential data input. Channel 2 31 CH4_2P Fourth Pixel Positive LVDS differential data input. Channel 2 32 GND Ground 33 CH4_CLKN 34 CH4_CLKP 35 GND Ground 36 CH4_3N Fourth Pixel Negative LVDS differential data input. Channel 3 37 CH4_3P Fourth Pixel Positive LVDS differential data input. Channel 3 38 CH4_4N Fourth Pixel Negative LVDS differential data input. Channel 4 39 CH4_4P Fourth Pixel Positive LVDS differential data input. Channel 4 40 N.C. No Connection 41 N.C. No Connection

Third Pixel Negative LVDS differential clock input. Third Pixel Positive LVDS differential clock input.

Fourth Pixel Negative LVDS differential clock input. Fourth Pixel Positive LVDS differential clock input.

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(1)

(4)

(1)

(4)

(1)

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CNF2 Connector Pin Assignment (187059-51221 (P-TWO) or equivalent)

Pin Name Description Note

1 N.C. No Connection

2 N.C. No Connection

3 N.C. No Connection

4 N.C. No Connection

5 N.C. No Connection

6 N.C. No Connection

7 SELLVDS LVDS data format Selection (2)

8 N.C. No Connection

9 N.C. No Connection 10 N.C. No Connection 11 GND Ground 12 CH1_0N First Pixel Negative LVDS differential data input. Channel 0 13 CH1_0P First Pixel Positive LVDS differential data input. Channel 0 14 CH1_1N First Pixel Negative LVDS differential data input. Channel 1 15 CH1_1P First Pixel Positive LVDS differential data input. Channel 1 16 CH1_2N First Pixel Negative LVDS differential data input. Channel 2 17 CH1_2P First Pixel Positive LVDS differential data input. Channel 2 18 GND Ground 19 CH1_CLKN 20 CH1_CLKP 21 GND Ground 22 CH1_3N First Pixel Negative LVDS differential data input. Channel 3 23 CH1_3P First Pixel Positive LVDS differential data input. Channel 3 24 CH1_4N First Pixel Negative LVDS differential data input. Channel 4 25 CH1_4P First Pixel Positive LVDS differential data input. Channel 4 26 N.C. No Connection 27 N.C. No Connection 28 CH2_0N Second Pixel Negative LVDS differential data input. Channel 0 29 CH2_0P Second Pixel Positive LVDS differential data input. Channel 0 30 CH2_1N Second Pixel Negative LVDS differential data input. Channel 1 31 CH2_1P Second Pixel Positive LVDS differential data input. Channel 1 32 CH2_2N Second Pixel Negative LVDS differential data input. Channel 2 33 CH2_2P Second Pixel Positive LVDS differential data input. Channel 2 34 GND Ground 35 CH2_CLKN 36 CH2_CLKP Second Pixel Positive LVDS differential clock input. 37 GND Ground 38 CH2_3N Second Pixel Negative LVDS differential data input. Channel 3 39 CH2_3P Second Pixel Positive LVDS differential data input. Channel 3

40 CH2_4N Second Pixel Negative LVDS differential data input. Channel 4

41 CH2_4P Second Pixel Positive LVDS differential data input. Channel 4 42 N.C. No Connection 43 N.C. No Connection 44 GND Ground 45 GND Ground

First Pixel Negative LVDS differential clock input. First Pixel Positive LVDS differential clock input.

Second Pixel Negative LVDS differential clock input.

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(1)

(3)

(1)

(3)

(1)

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46 GND Ground 47 N.C. No Connection 48 Vin Power input (+12V) 49 Vin Power input (+12V) 50 Vin Power input (+12V) 51 Vin Power input (+12V)

Note (1) Please be reserved to open.

Note (2) Low or Open: VESA Format(default), connect to GND. High: JEIDA Format, connect to+3.3V.

Note (3) LVDS 4-Port Data Mapping

Port CH of LVDS Data Stream

1st Port First pixel 1, 5, 9, ..........., 1913, 1917

2nd Port Second pixel 2, 6, 10, ........., 1914, 1918

3rd Port Third pixel 3, 7, 11, ........., 1915, 1919

4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920

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)

5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.

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Model No.: V460H1 - LH8

Preliminary

CN2-CN8: CP042EP1MFB-LF (Cvilux)

Pin Name Description Wire Color

1 HV High Voltage Blue

2 HV High Voltage White

Note (1) The backlight interface housing for high voltage side is a model CP042EP1MFB-LF,

manufactured by Cvilux. The mating header on inverter part number is

CP042EP1MFB-LF (Cvilux)

1.HV (Blue

2.HV(White

1.HV (Blue

2.HV (White

1.HV (Blue

2.HV (White

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5.3 INVERTER UNIT

CN1: CI0114M1HR0-LA (Cvilux) or equivalent

№

Symbol Feature

1

2

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Model No.: V460H1 - LH8

Preliminary

3

4

5

6

7

8

9

10

11

12

13

14

Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.

VBL +24V

GND GND

STATUS

Normal (3.3V) Abnormal(GND)

E_PWM External PWM Control Signal

I_PWM Internal PWM Control Signal

BLON BL ON/OFF

Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.

Note (3) Pin 12 and Pin 13 can’t open in the same period.

CN2~CN8: CP042EP1MFB-LF (Cvilux)

№

Symbol Description

1

2

CCFL HOT CCFL high voltage

20

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5.4 BLOCK DIAGRAM OF INTERFACE

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Model No.: V460H1 - LH8

Preliminary

ARx0 +

ARx0 -

ARx1 +

ARx1 -

ARx2 +

ARx2 -

ARx3 +

ARx3 -

ARx4 +

ARx4 -

ACLK +

ACLK -

51Ω

100pF

PLL

RxOUT

AR0

Ω

AG0

Ω

AB0

DE

AR9

AG9

AB9

BRx0 +

BRx0 -

BRx1 +

BRx1 -

BRx2 +

BRx2 -

BRx3 +

BRx3 -

BRx4 +

BRx4 -

BCLK +

BCLK -

51Ω

100pF

PLL

BR0

BG0

BB0

Ω

DCLK

DCLK Timing Controller

LVDS Receiver (MASTER)

Ω

BR9

BG9

BB9

LVDS INPUT

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AR0~AR9: First pixel R data

AG0~AG9: First pixel G data

AB0~AB9: First pixel B data

BR0~BR9: Second pixel R data

BG0~BG9: Second pixel G data

BB0~BB9: Second pixel B data

DE: Data enable signal

DCLK: Data clock signal

The third and fourth pixel are followed the same rules.

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

CR0~CR9: Third pixel R data

CG0~CG9: Third pixel G data

CB0~CB9: Third pixel B data

DR0~DR9: Fourth pixel R data

DG0~DG9: Fourth pixel G data

DB0~DB9: Fourth pixel B data

Note (1) A ~ D channel are first, second, third and fourth pixel respectively.

Note (2) The system must have the transmitter to drive the module.

Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is

used differentially.

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5.5 LVDS INTERFACE

VESA Format : SELLVDS = L or Open

JEIDA Format : SELLVDS = H

VESA Format

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Current Cycle

AR 0P

AR 0N

AR 1P

AR 1N

AR 2P

AR 2N

AR 3P

AR 3N

AR 4P

AR 4N

JEIDA Format

AR 0P

AR 0N

AR 1P

AR 1N

AR0

AG1

AB2

AR6

AR4

AG5

AG0 AR5

AB1

DE VS HS AB5 AB4 AB3 AB2

REV AB7 AB6 AG7 AG6 AR7 AR6

REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV

AG4 AR7

AB5

AB0 AG5 AG4 AG3 AG2 AG1

AB4 AG7 AG6 AG5AG9 AG8

AR4 AR3 AR2 AR1 AR0

AR6 AR5 AR4AR9 AR8

AG0

AB1

DE

REV

AG4

AB5

AR 2P

AR 2N

AR 3P

AR 3N

AR 4P

AR 4N

AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)

AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)

AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)

DE : Data enable signal

DCLK : Data clock signal

RSV : Reserved

AB6

AR2

DE VS HS AB7 AB6AB9 AB8

REV AB3 AB2 AG3 AG2 AR3 AR2

REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV

23

DE

REV

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5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for

the color. The higher the binary input, the brighter the color. The table below provides the assignment of the

color versus data input.

Color

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

0

0 1 0 0 0 1 1 1

0 0 0

1 1 1

0 0 0

:

: 0 0 0

0 0 0

:

: 0 0 0

0

1

0

1

0

:

1

0

:

0

:

0

Basic Colors

Gray Scale Of Red

Gray Scale Of Green

Gray Scale Of Blue

Black Red Green Blue Cyan Magenta Yel lo w White

Red (0) / Dark Red (1) Red (2)

:

: Red (1021) Red (1022) Red (1023)

Green (0) / Dark Green (1) Green (2)

:

: Green (1021) Green (1022) Green (1023)

Blue (0) / Dark Blue (1) Blue (2)

:

: Blue (1021) Blue (1022) Blue (1023)

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Data Signal

Red Green Blue

0

1

0

1

0

1

0

1

0

:

1

0

:

0

:

0

1

:

1

0

1

0

:

0

:

0

1

0

1

0

:

1

0

1

0

:

0

1

0

1

0

1

0

:

0

1

0

:

0

:

1

0

:

0

1

0

1

0

:

0

:

1

0

:

: :

:

0

1

0

1

0

1

0

:

;

0

1

0

1

:

1

0

1

0

1

0

:

0

1

0

1

0

1

0

1

0

1

0

:

0

0 0

0

:

0

:

1

0

1

0

1

0

:

0

:

0

:

1

0

1

0

1

0

:

0

:

0

1

0

1

0

:

1

0

1

0

1

Note (1) 0: Low Level Voltage, 1: High Level Voltage

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6. INTERFACE TIMING

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram

Signal Item Symbol Min. Typ. Max. Unit Note

F

clkin

(=1/TC)

T

rcl

clkin_mod

F

LVDS

Receiver

Clock

Frequency

Input cycle to cycle jitter Spread spectrum modulation range Spread spectrum modulation

F

SSM

.

60 74.25 80 MHz

- - 200 ps (3)

F

-2% - F

clkin

- - 200 KHz

+2% MHz

clkin

(4)

frequency

LVDS

Receiver

Data

Vertical

Active

Setup Time

Hold Time

Frame Rate

To ta l

Tlvsu 600

Tlvhd 600

F

Tv 1115 1125 1135 Th

97 100 103 Hz

r5

117 120 123 Hz

r6

- -

ps

(5)

(6)

Tv=Tvd+T vb

Display

Te rm

Display

Tvd 1080 1080 1080 Th

Ё

Blank

Horizontal

Active

Display

Te rm

Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low

Note (2) Please make sure the range of pixel clock has follow the below equation:

Fr5 Tv Th Fclkin(min)

To ta l

Display

Blank

logic level. Otherwise, this module would operate abnormally.

F

clkin(max)

F

Њ

r

6

Tv Th

ѼѼ

ѼѼЊ

Tvb 35 45 55 Th

Th 540 550 575 Tc

Thd 480 480 480 Tc

Thb 60 70 95 Tc

Th=Thd+Thb

Ё

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

INPUT SIGNAL TIMING DIAGRAM

Tvd

Tv

Tvb

DE

T

h

DCLK

DE

Thd

DAT

Valid display data ( 480

Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI

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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.

LVDS RECEIVER INTERFACE TIMING DIAGRAM

Tc

RXCLK+/-

RXn+/-

Tlvsu

Tlvhd

1T

3T

5T

7T

9T

11T

13T

14

Note (6) : (ODSEL) = H/L or open for 100/120Hz frame rate. Please refer to 5.1 for detail information

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6.2 POWER ON/OFF SEQUENCE

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram

below.

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

10ms

50ms

ЉЉЉЉ

T4

0V

0.5

ЉЉЉЉ

T

1

ЉЉЉЉ

T

ЉЉЉЉ

2

T

3

0

500ms

ЉЉЉЉ

0.1V

CC

3

T1

T

2

T

0.1V

cc

T

4

LVDS Signals

0V

Power On

VA L I D

Power Off

0

ЉЉЉЉ

T

7

ЉЉЉЉ

T2

T

8

ЉЉЉЉ

T3

7

T

8

T

0

Option Signals

Backlight (Recommended)

500ms

(SELLVDS,…)

ЉЉЉЉ

T5

100ms

ЉЉЉЉ

T

6

50%

5

T

50%

6

T

NoteΚ

Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.

Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD

operation or the LCD turns off before the backlight turns off, the display may momentarily become

abnormal screen.

Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If

T2<0,that maybe cause electrical overstress failure.

Note (4) T4 should be measured after the module has been fully discharged between power off and on period.

Note (5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit Ambient Temperature Ta Ambient Humidity Ha Supply Voltage VCC 12V V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" Lamp Current IL Oscillating Frequency (Inverter) FW Vertical Frame Rate Fr 120 Hz

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

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25

50

11.0 40

±

± ±

2

10

0.5 3

Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

o

C

%RH

mA

KHz

measured under the test conditions described in 7.1 and stable environment shown in Note (6).

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR 4000 6000 - - Note (2)

Response Time

Gray to

gray

Center Luminance of White L

White Variation

δ

C

W

- 4.5 9 ms Note (3)

360 450 -

- - 1.3 - Note (7)

Cross Talk CT - - 4 % Note (5)

θ

=0°,

θ

CR

≥

=0°

Y

20

0.324

Typ.-

0.03

0.603

Typ.+

0.03

0.050

0.290

72 - % NTSC 80 88 80 88 80 88 -

Deg. Note (1)

80 88 -

Color Chromaticity

Viewing Angle

Red

Rx 0.633 -

Ry

Green

Blue

White

Gx 0.289 Gy Bx 0.147 -

By Wx 0.280 Wy

Color Gamut

Horizontal

Vertical

θ

x

Viewing angle at

normal direction

+

x

-

x

+

Y

-

Y

cd/

m

-

2

Note (4)

Note (6)

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T

Note (1) Definition of Viewing Angle (θx, θy):

Viewing angles are measured by Autronic Conoscope Cono-80

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Note (2) Definition of Contrast Ratio (CR):

θ

X-

= 90º

6 o’clock

θ

y-

= 90º

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L255 / L0

L255: Luminance of gray level 255

x-

y-

Normal

θ

x = θy = 0º

θy- θy+

θx−

θx+

y+

12 o’clock direction

θ

y+

= 90º

x+

θ

X+

= 90º

L 0: Luminance of gray level 0

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note

(7)

Note (3) Definition of Gray to Gray Switching Time :

Optical

Response

The driving signal means the signal of gray level 0, 63, 127, 191, and 255.

Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each other .

100%

90%

10%

0%

Gray to gray switching time

ime

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(

)

(

)

Note (4) Definition of Luminance of White (LC):

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Measure the luminance of gray level 255 at center point.

LC = L (5), where L (x) is corresponding to the luminance of the point X at the figure in Note (7).

Note (5) Definition of Cross Talk (CT):

CT = | Y

– YA | / YA × 100 (%)

B

Where:

= Luminance of measured location without gray level 255 pattern (cd/m2)

Y

A

Y

= Luminance of measured location with gray level 255 pattern (cd/m2)

B

(0, 0)

Active Area

Y

(D/8,W/2)

A, L

Gray128

Y

(D/2,7W /8)

A, D

Y

A, U

Y

A, R

D, W

(D/2,W /8)

(7D/8,W/2)

(D/4,W/4)

Y

(D/8,W/2)

B, L

Y

(D/2,7W /8)

B, D

0, 0

Active Area

Gray 0

Gray 255

Gray128

Y

B, U

Y

B, R

(3D/4,3W/4)

(D, W)

(D/2,W /8)

(7D/8,W/2)

Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature

change during measuring. In order to stabilize the luminance, the measurement should be

executed after lighting backlight for 1 hour in a windless room.

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Note (7) Definition of White Variation (δW):

Measure the luminance of gray level 255 at 5 points

δ

W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Vertical Line

W

W/4

W/2

3W /4

Horizontal Line

D

D/4 D/2 3D/4

12

5

34

Active Area

X

: Test Point

X=1 to 5

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8. DEFINITION OF LABELS

8.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

CHI MEI

OPTOELECTRONICS

V460H1 -LH8 Rev. XX

GEMN

X X X X X X X Y M D L N N N N

V460H1 - LH8 Rev. XX

CHI MEI

OPTOELECTRONICS

X X X X X X X Y M D L N N N N

(a) Model Name: V460H-LH8

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

(c) Serial ID: X X

(d) Production Location: XXXX, for example: TAIWAN or CHINA.

X X X X X Y M D L N N N N

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

Revision

CMO Internal Use

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Serial ID includes the information as below:

(a) Manufactured Date: Year: 2003=3, 2004=4….2010=0,2011=1,2012=2…

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1

(b) Revision Code: Cover all the change

(c) Serial No.: Manufacturing sequence of product

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st

to 31st, exclude I ,O, and U.

Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Product Line: 1 -> Line1, 2 -> Line 2, …etc.

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9. PACKAGING

9.1 PACKING SPECIFICATIONS

(1) 3 LCD TV modules / 1 Box

(2) Box dimensions : 1175(L)x 282(W)x 725(H)mm

(3) Weight : approximately 45Kg (3 modules per box)

9.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method

LCD TV Module

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

Anti-static Bag

PP Belt

Cushion(Bottom)

Carton Label

Figure.9-1 packing method

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Air Transportation &

Sea / Land Transportation (40ft Container)

(L1130*50*50mm)

Film

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

(L1150*W1190*H140mm)

(L1400*50*50mm)

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Model No.: V460H1 - LH8

Preliminary

Sea / Land Transportation (40ft HQ Container)

Figure.9-2 packing method

(L1130*50*50mm)

(L625*50*50mm)

Film

(L1130*50*50mm)

(L1400*50*50mm)

(L1150*W1190*H140mm)

Figure.9-2 packing method

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

10. PRECAUTIONS

10.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the module during assembly.

(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.

(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

(5) Do not plug in or pull out the I/F connector while the module is in operation.

(6) Do not disassemble the module.

(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.

(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD

modules in the specified storage conditions.

(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of CCFL will be higher than that of room

temperature.

10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling

with the inverter. Do not disassemble the module or insert anything into the backlight unit.

(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

10.3 SAFETY STANDARDS

The LCD module should be certified with safety regulations as follows:

Regulatory Item Standard

UL UL 60950-1: 2003

Information Technology equipment

Audio/Video Apparatus

If the module displays the same pattern for a long period of time, the phenomenon of image sticking may be

occurred.

cUL CAN/CSA C22.2 No.60950-1-03

CB IEC 60950-1:2001

UL UL 60065: 2003

cUL CAN/CSA C22.2 No.60065-03

CB

IEC 60065:2001

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11. MECHANICAL CHARACTERISTIC

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

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ڻႝηިҽԖϦљ

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Issued Date: Jan.25, 2010

Model No.: V460H1 - LH8

Preliminary

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