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Approved By Checked By Prepared By
Chao-Chun Chung Ken Wu HT Hung
Version 2.3 1 DateΚΚΚΚ19 Aug 2010
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PRODUCT SPECIFICATION
CONTENTS
REVISION HISTORY .....................................................................................................................................................4
1. GENERAL DESCRIPTION ........................................................................................................................................5
1.4 GENERAL SPECIFICATIONS ............................................................................................................................5
2. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT ....................................................................................................... 7
5.2 CONVERTER UNIT ..........................................................................................................................................19
5.3 BLOCK DIAGRAM OF INTERFACE.................................................................................................................20
7.1 TEST CONDITIONS .........................................................................................................................................28
9. DEFINITION OF LABELS........................................................................................................................................33
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V460H1-LE3 is a 46” TFT Liquid Crystal Display module with LED Backlight and 4ch-LVDS interface. This
module supports 1920 x 1080 Full HDTV format and can display true 1.07G colors (8bit+Hi-FRC -bit/color). The
converter module for backlight is built-in.
1.2 FEATURES
Ё High brightness (450 nits)
Ё High contrast ratio (6000:1)
Ё Fast response time (Gray to gray average 5.5 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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PRODUCT SPECIFICATION
Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for 120 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHS compliance
1.3 APPLICATION
Ё Standard Living Room TVs.
Ё Public Display Application.
Ё Home Theater Application.
Ё MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1018.08 (H) x 572.67 (V) (46” diagonal) mm
Bezel Opening Area 1024.48 (H) x 578.67 (V) mm
Driver Element a-si TFT active matrix -
Pixel Number 1920 x R.G.B. x 1080 pixel
Pixel Pitch (Sub Pixel) 0.1805 (H) x 0.5405 (V) mm
Pixel Arrangement RGB vertical stripe -
Display Colors 1.07G color
Display Operation Mode Transmissive mode / Normally Black -
Surface Treatment
Anti-Glare Coating (Haze 11%)
Hard Coating (3H)
(1)
- (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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PRODUCT SPECIFICATION
1.5 MECHANICAL SPECIFICATION
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal(H) 1075.5 1076.5 1077.5 mm
Vertical(V) 633.7 634.7 635.7 mm
Depth(D) 9.9 10.8 11.8 mm To Rear
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Depth(D)
Weight - 9500 - g
24.6 25.6 26.6
22.5 23.5 24.5
mm To converter
mm To converter
(1)
cover(Darfon)
cover(Ampower)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 050 ºC (1), (2)
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Max.
X,Y
Shock (Non-Operating) SNOP
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
axis
Z axis35 G (3), (5)
- 35 G (3), (5)
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(1)
2.3.2 BACKLIGHT CONVERTER UNIT
Value
Item Symbol
Min. Max.
Light Bar Voltage VW
Converter Input Voltage VBL 030V(1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum value s are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Contro.l Internal PWM Control and External PWM Control.
Ё
Ё
-0.3 7V(1), (3)
60V
Unit Note
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Rush Current I
- - 4 A (2)
RUSH
White Pattern - - 0.5 0.65 A
Power Supply Current
Horizontal Stripe - - 0.94 1.22 A
Black Pattern - - 0.42 0.54 A
LVDS
interface
CMOS
interface
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
V
V
LVT H
LVT L
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(Single-end)
Terminating Resistor R
|V
ID
T
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage V
IL
+100 - - mV
- - -100 mV
| 200 - 600 mV
- 100 - ohm
0 - 0.7 V
Note (1) The module should be always operated within the above ranges.
(3)
(4)
Note (2) Measurement condition:
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PRODUCT SPECIFICATION
(Low to H igh )
Control Signal
SW
+12 V
R1
1k
Vcc
Q1Si4485DY
Fuse
VR1
47k
R2
1k
Q2
2N7002
C1
0.01uF
(LCD Module Input)
C3
1uF
GND
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,
whereas a power dissipation check pattern below is displayed.
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PRODUCT SPECIFICATION
a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT UNIT
3.2.1 LED CHARACTERISTICS (Ta=25± 2 ºC)
Parameter Symbol
Forward Voltage V
LED Current I
3.2.2 CONVERTER CHARACTERISTICS
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Consumption PBL - 108 118.8 W IL =120mA
W
L
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PRODUCT SPECIFICATION
Value
Min. Typ. Max.
3.0 3.2 3.5
- 120
Value
Min. Typ. Max.
Unit Note
V I
mA
Unit Note
=120.0mA
L
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - 4.5 5.0 A Non Dimming
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN 5 10 - % (2)
Note (1) The measurement condition of Max. value is based on 46" backlight unit under input voltage 24V,
average LED current 120mA and lighting 30 minutes later.
Note (2) 5% minimum duty ratio is only valid for electrical operation.
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3.2.3 CONVERTER INTERFACE CHARACTERISTICS
PRODUCT SPECIFICATION
Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
MAX
VIPWM
MIN
HI
VEPWM
LO
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
0
0
0
30
30
Value
Ё
Ё
0
Ё
Ё
Ё
ЁЁ
ЁЁ
Te st
Condition
Ё
Min.Typ.Max.
2.0
Ё
Ё
2.853.0 3.15V maximum duty ratio
ЁЁ
Ё
2.0
Ё
Ё
3.0 3.3 3.6 V
Ё
Ё
Ё
ЁЁЁ
UnitNote
5.0 V
0.8 V
Ё
Vminimum duty ratio
5.0 V
0.8 V
0.8 V
ms
ms
100 ms
Duty on
Duty off
Normal
Abnormal
10%-90%V
BL
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
on
ЁЁЁ
ЁЁЁ
ЁЁЁ
Ё
Ё
Ё
1
100
300
ЁЁ
ЁЁ
ЁЁ
100 ms
50 us
50 us
MΩ
ms
ms
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
Ё
300
300
ЁЁ
ЁЁ
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Ш PWM signal Ш BLON
Turn OFF sequence: BLOFF
Ш PWM signal Ш VBL
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PRODUCT SPECIFICATION
V
V
V
BL
V
BLON
EPWM
IPWM
9
Toff
%/
Tf1
9
%/
Tr1
9
%/
9
%/
2.0V
0.8V
Ton
Ton1
0
0
Backlight on duration
Tr
Tf
Ext. Dimming Function
PWMR
T
2.0V
0
0.8V
T
PWM
PWMF
T
Floating
3.3V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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P-TWO 187060-41221+P-TWO 187059-51221 or equivalent
SCAN DRIVER
TIMING
CONTROLLER
INPUT CONNECTOR
DC/DC CONVERTER
CONVERTER CONNECTOR
CI0114M1HR0-LF
CN1:
(CvilLux)
or equivalent
BACKLIGHT
TFT LCD PANEL
(1920x3x1080)
DATA DRIVER
LED
UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF3 Connector Pin Assignment (187060-41221(P-TWO) or equivalent)
PinName Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 N.C. No Connection
8 N.C. No Connection
9 GND Ground
10CH3_0N Third Pixel Negative LVDS differential data input. Channel 0
11CH3_0P Third Pixel Positive LVDS differential data input. Channel 0
12CH3_1N Third Pixel Negative LVDS differential data input. Channel 1
13CH3_1P Third Pixel Positive LVDS differential data input. Channel 1
14CH3_2N Third Pixel Negative LVDS differential data input. Channel 2
15CH3_2P Third Pixel Positive LVDS differential data input. Channel 2
16GND Ground
17CH3_CLKN
18CH3_CLKP
19GND Ground
20CH3_3N Third Pixel Negative LVDS differential data input. Channel 3
21CH3_3P Third Pixel Positive LVDS differential data input. Channel 3
22CH3_4N Third Pixel Negative LVDS differential data input. Channel 4
23CH3_4P Third Pixel Positive LVDS differential data input. Channel 4
24N.C. No Connection
25N.C. No Connection
26CH4_0N Fourth Pixel Negative LVDS differential data input. Channel 0
27CH4_0P Fourth Pixel Positive LVDS differential data input. Channel 0
28CH4_1N Fourth Pixel Negative LVDS differential data input. Channel 1
29CH4_1P Fourth Pixel Positive LVDS differential data input. Channel 1
30CH4_2N Fourth Pixel Negative LVDS differential data input. Channel 2
31CH4_2P Fourth Pixel Positive LVDS differential data input. Channel 2
32GND Ground
33CH4_CLKN
34CH4_CLKP
35GND Ground
36CH4_3N Fourth Pixel Negative LVDS differential data input. Channel 3
37CH4_3P Fourth Pixel Positive LVDS differential data input. Channel 3
38CH4_4N Fourth Pixel Negative LVDS differential data input. Channel 4
39CH4_4P Fourth Pixel Positive LVDS differential data input. Channel 4
40N.C. No Connection
41N.C. No Connection
Third Pixel Negative LVDS differential clock input.
Third Pixel Positive LVDS differential clock input.
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CNF2 Connector Pin Assignment (187059-51221 (P-TWO) or equivalent )
PinName Description Note
1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (2)
8 N.C. No Connection
9 N.C. No Connection
10N.C. No Connection
11GND Ground
12CH1_0N First Pixel Negative LVDS differential data input. Channel 0
13CH1_0P First Pixel Positive LVDS differential data input. Channel 0
14CH1_1N First Pixel Negative LVDS differential data input. Channel 1
15CH1_1P First Pixel Positive LVDS differential data input. Channel 1
16CH1_2N First Pixel Negative LVDS differential data input. Channel 2
17CH1_2P First Pixel Positive LVDS differential data input. Channel 2
18GND Ground
19CH1_CLKN
20CH1_CLKP
21GND Ground
22CH1_3N First Pixel Negative LVDS differential data input. Channel 3
23CH1_3P First Pixel Positive LVDS differential data input. Channel 3
24CH1_4N First Pixel Negative LVDS differential data input. Channel 4
25CH1_4P First Pixel Positive LVDS differential data input. Channel 4
26N.C. No Connection
27N.C. No Connection
28CH2_0N Second Pixel Negative LVDS differential data input. Channel 0
29CH2_0P Second Pixel Positive LVDS differential data input. Channel 0
30CH2_1N Second Pixel Negative LVDS differential data input. Channel 1
31CH2_1P Second Pixel Positive LVDS differential data input. Channel 1
32CH2_2N Second Pixel Negative LVDS differential data input. Channel 2
33CH2_2P Second Pixel Positive LVDS differential data input. Channel 2
34GND Ground
35CH2_CLKN
36CH2_CLKP Second Pixel Positive LVDS differential clock input.
37GND Ground
38CH2_3N Second Pixel Negative LVDS differential data input. Channel 3
39CH2_3P Second Pixel Positive LVDS differential data input. Channel 3
40CH2_4N Second Pixel Negative LVDS differential data input. Channel 4
41CH2_4P Second Pixel Positive LVDS differential data input. Channel 4
42N.C. No Connection
43N.C. No Connection
44GND Ground
First Pixel Negative LVDS differential clock input.
First Pixel Positive LVDS differential clock input.
Second Pixel Negative LVDS differential clock input.
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PRODUCT SPECIFICATION
(1)
(1)
(3)
(3)
(1)
(3)
(3)
(1)
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45GND Ground
46GND Ground
47N.C. No Connection
48Vin Power input (+12V)
49Vin Power input (+12V)
50Vin Power input (+12V)
51Vin Power input (+12V)
Note (1) Please be reserved to open.
Note (2) Low or Open: JEIDA Format(default), connect to GND. High: VESA Format, connect to +3.3V.
Note (3) LVDS 4-Port Data Mapping
Port CH of LVDS Data Stream
1st Port First pixel 1, 5, 9, ..........., 1913, 1917
2nd Port Second pixel 2, 6, 10, ........., 1914, 1918
3rd Port Third pixel 3, 7, 11, ........., 1915, 1919
4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920
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PRODUCT SPECIFICATION
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5.2 CONVERTER UNIT
CN1: CI0114M1HR0-LF (CvilLux) or equivalent
Pin №Symbol Feature
1
2
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PRODUCT SPECIFICATION
3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL+24V
GND GND
Normal (3.3V)
Abnormal(GND)
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.