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TFT LCD Tentative Specification
MODEL NO.: V460H1 – LE2
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
Approved By
Reviewed By
Prepared By
TV Head Division
Chao-Chun Chung
QA Dept. Product Development Div.
Hsin-nan Chen WT Lin
LCD TV Marketing and Product Management Div.
CY Chang HT Hung
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
CONTENTS
REVISION HISTORY.......................................................................................................................................................4
1. GENERAL DESCRIPTION..........................................................................................................................................5
1.1 OVERVIEW .......................................................................................................................................................... 5
1.2 FEATURES........................................................................................................................................................... 5
1.3 APPLICATION ......................................................................................................................................................5
1.4 GENERAL SPECIFICATIONS .............................................................................................................................5
1.5 MECHANICAL SPECIFICATION .........................................................................................................................6
2. ABSOLUTE MAXIMUM RATINGS .............................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT........................................................................................................ 7
2.2 PACKAGE STORAGE.......................................................................................................................................... 8
2.3 ELECTRICAL ABSOLUTE RATINGS ..................................................................................................................8
2.3.1 TFT LCD MODULE ....................................................................................................................................8
2.3.2 BACKLIGHT CONVERTER UNIT..............................................................................................................8
3. ELECTRICAL CHARACTERISTICS...........................................................................................................................9
3.1 TFT LCD MODULE .............................................................................................................................................. 9
3.2 BACKLIGHT UNIT..............................................................................................................................................12
3.2.1 LED CHARACTERISTICS (Ta=25± 2 ºC)................................................................................................12
3.2.2 CONVERTER CHARACTERISTICS .......................................................................................................12
3.2.3 CONVERTER INTERFACE CHARACTERISTICS ..................................................................................13
4. BLOCK DIAGRAM OF INTERFACE ........................................................................................................................ 15
4.1 TFT LCD MODULE ............................................................................................................................................ 15
5. INPUT TERMINAL PIN ASSIGNMENT ....................................................................................................................16
5.1 TFT LCD Module Input.......................................................................................................................................16
5.2 BACKLIGHT UNIT..............................................................................................................................................19
5.3 CONVERTER UNIT ...........................................................................................................................................20
5.4 BLOCK DIAGRAM OF INTERFACE..................................................................................................................21
5.5 LVDS INTERFACE .............................................................................................................................................23
5.6 COLOR DATA INPUT ASSIGNMENT ................................................................................................................24
6. INTERFACE TIMING.................................................................................................................................................25
6.1 INPUT SIGNAL TIMING SPECIFICATIONS......................................................................................................25
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
6.2 POWER ON/OFF SEQUENCE..........................................................................................................................25
7. OPTICAL CHARACTERISTICS................................................................................................................................29
7.1 TEST CONDITIONS........................................................................................................................................... 29
7.2 OPTICAL SPECIFICATIONS .............................................................................................................................30
8. PRECAUTIONS......................................................................................................................................................... 34
8.1 ASSEMBLY AND HANDLING PRECAUTIONS ................................................................................................. 34
8.2 SAFETY PRECAUTIONS ..................................................................................................................................34
9. DEFINITION OF LABELS ......................................................................................................................................... 35
9.1 CMO MODULE LABEL ...................................................................................................................................... 35
10. PACKAGING ...........................................................................................................................................................36
11. MECHANICAL CHARACTERISTICS .....................................................................................................................38
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REVISION HISTORY
Version Date
Ver. 0.0 Dec. 10.09 All All The Tentative Specification was first issued.
Page
(New)
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
Section Description
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V460H1-LE2 is a 46” TFT Liquid Crystal Display module with LED LBacklight unit and 4ch-LVDS interface. This
module supports 1920 x 1080 Full HDTV format and can display true 1.07G colors (8bit+Hi-FRC -bit/color). The
inverter module for backlight is built-in.
1.2 FEATURES
Ё High brightness (450 nits)
Ё High contrast ratio (4000:1)
Ё Fast response time (Gray to gray average 4.5 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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Model No.: V460H1-LE2
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Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for 120 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHS compliance
1.3 APPLICATION
Ё Standard Living Room TVs.
Ё Public Display Application.
Ё Home Theater Application.
Ё MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1018.08 (H) x 572.67 (V) (46” diagonal) mm
Bezel Opening Area 1024.48 (H) x 578.67 (V) mm
Driver Element a-si TFT active matrix -
Pixel Number 1920 x R.G.B. x 1080 pixel
Pixel Pitch (Sub Pixel) 0.1805 (H) x 0.5405 (V) mm
Pixel Arrangement RGB vertical stripe -
Display Colors 1.07G color
Display Operation Mode Transmissive mode / Normally Black -
Surface Treatment
Anti-Glare Coating (Haze 11%)
Hard Coating (3H)
(1)
- (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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1.5 MECHANICAL SPECIFICATION
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal(H) - 1076.5 - mm
Vertical(V) - 634.7 - mm
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Depth(D) 10.8 mm To Rear
Depth(D)
Weight (10000) g
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25.1
Issue Date:Dec.10.2009
Model No.: V460H1-LE2
mm To converter
Tentative
(1)
cover
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
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Model No.: V460H1-LE2
Tentative
Value
Unit Note
Min. Max.
X,Y
Shock (Non-Operating) SNOP
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
axis
Z axis 35 G (3), (5)
- 50 G (3), (5)
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
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Model No.: V460H1-LE2
Tentative
Value
Unit Note
Min. Max.
(1)
2.3.2 BACKLIGHT CONVERTER UNIT
Value
Item Symbol
Min. Max.
Light Bar Voltage VW
Converter Input Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum value s are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Contro.l Internal PWM Control and External PWM Control.
Ё
Ё
-0.3 7 V (1), (3)
60 VRMS
Unit Note
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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Model No.: V460H1-LE2
Tentative
Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
Common Input Voltage VCM 1.0 1.2 1.4 V
- - 4.35 A (2)
RUSH
-
-
-
V
LVT H
- - -100 mV
V
LVT L
- 0.464 0.6 A
- 0.9 1.17 A
- 0.4 0.52 A
+100 - - mV
Differential input voltage |VID| 200 - 600 mV
- 100 - ohm
T
0 - 0.7 V
IL
CMOS
interface
Terminating Resistor R
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage V
Note (1) The module should be always operated within the above ranges.
(3)
(4)
Note (2) Measurement condition:
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
(Low to H ig h)
Control Signal
SW
+12V
Vcc
Q1 Si4485DY
Fus e
R1
1k
VR1
47k
C1
0.01uF
R2
Q2
2N7002
1k
(LCD Module Input)
C3
1uF
GND
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,
whereas a power dissipation check pattern below is displayed.
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Model No.: V460H1-LE2
Tentative
a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT UNIT
3.2.1 LED CHARACTERISTICS (Ta=25± 2 ºC)
Parameter Symbol
Forward Voltage V
LED Current I
3.2.2 CONVERTER CHARACTERISTICS
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Consumption PBL - TBD -- W IL =150mA
W
L
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Value
Min. Typ. Max.
3.25 3.7 4.05
- 150
Value
Min. Typ. Max.
Unit Note
V
RMS
mA
Unit Note
Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
I
RMS
=150.0mA
L
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - TBD - A Non Dimming
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN - 5 - %
Note (1) The measurement condition of Max. value is based on 46" backlight unit under input voltage 24V,
average LED current 60 mA and lighting 30 minutes later.
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3.2.3 CONVERTER INTERFACE CHARACTERISTICS
Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
MAX
VIPWM
MIN
HI
VEPWM
LO
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
0
0
0
30
30
Value
Ё
Ё
0
Ё
Ё
Ё
ЁЁ
ЁЁ
Te st
Condition
Ё
Min. Typ. Max.
2.0
Ё
Ё
2.85 3.0 3.15 V maximum duty ratio
ЁЁ
Ё
2.0
Ё
Ё
3.0 3.3 3.6 V
Ё
Ё
Ё
ЁЁЁ
Unit Note
5.0 V
0.8 V
Ё
V minimum duty ratio
5.0 V
0.8 V
0.8 V
ms
ms
100 ms
Duty on
Duty off
Normal
Abnormal
10%-90%V
BL
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
on
ЁЁЁ
ЁЁЁ
ЁЁЁ
Ё
Ё
Ё
1
100
300
ЁЁ
ЁЁ
ЁЁ
100 ms
50 us
50 us
MΩ
ms
ms
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
Ё
300
300
ЁЁ
ЁЁ
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Ш PWM signal Ш BLON
Turn OFF sequence: BLOFF
Ш PWM signal Ш VBL
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
V
V
V
BL
V
BLON
EPWM
IPWM
9
Toff
%/
Tf1
9
%/
Tr1
9
%/
9
%/
2.0V
0.8V
Ton
Ton1
0
0
Backlight on duration
Tr
Tf
Ext. Dimming Function
PWMR
T
2.0V
0
0.8V
T
PWM
PWMF
T
Floating
3.3V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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Model No.: V460H1-LE2
Tentative
CONVERTER CONNECTOR
CN1: CI0114M1HR0-LF
(CvilLux) or equivalent
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment (FI-RE41S-HF(JAE) or equivalent)
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 N.C. No Connection
8 N.C. No Connection
9 GND Ground
10 CH3_0N Third Pixel
11 CH3_0P Third Pixel
12 CH3_1N Third Pixel
13 CH3_1P Third Pixel
14 CH3_2N Third Pixel
15 CH3_2P Third Pixel
16 GND Ground
17 CH3_CLKN
18 CH3_CLKP
19 GND Ground
20 CH3_3N Third Pixel
21 CH3_3P Third Pixel
22 CH3_4N Third Pixel
23 CH3_4P Third Pixel
24 N.C. No Connection
25 N.C. No Connection
26 CH4_0N Fourth Pixel
27 CH4_0P Fourth Pixel
28 CH4_1N Fourth Pixel
29 CH4_1P Fourth Pixel
30 CH4_2N Fourth Pixel
31 CH4_2P Fourth Pixel
32 GND Ground
33 CH4_CLKN
34 CH4_CLKP
35 GND Ground
36 CH4_3N Fourth Pixel
37 CH4_3P Fourth Pixel
38 CH4_4N Fourth Pixel
39 CH4_4P Fourth Pixel
40 N.C. No Connection
41 N.C. No Connection
Third Pixel Negative LVDS differential clock input.
Third Pixel Positive LVDS differential clock input.
Fourth Pixel Negative LVDS differential clock input.
Fourth Pixel Positive LVDS differential clock input.
Negative LVDS differential data input. Channel 0
Positive LVDS differential data input. Channel 0
Negative LVDS differential data input. Channel 1
Positive LVDS differential data input. Channel 1
Negative LVDS differential data input. Channel 2
Positive LVDS differential data input. Channel 2
Negative LVDS differential data input. Channel 3
Positive LVDS differential data input. Channel 3
Negative LVDS differential data input. Channel 4
Positive LVDS differential data input. Channel 4
Negative LVDS differential data input. Channel 0
Positive LVDS differential data input. Channel 0
Negative LVDS differential data input. Channel 1
Positive LVDS differential data input. Channel 1
Negative LVDS differential data input. Channel 2
Positive LVDS differential data input. Channel 2
Negative LVDS differential data input. Channel 3
Positive LVDS differential data input. Channel 3
Negative LVDS differential data input. Channel 4
Positive LVDS differential data input. Channel 4
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(1)
(4)
(4)
(1)
(4)
(4)
(1)
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CNF2 Connector Pin Assignment (FI-RE51S-HF (JAE) or equivalent )
Pin Name Description Note
1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (2)
8 N.C. No Connection
9 N.C. No Connection
10 N.C. No Connection
11 GND Ground
12 CH1_0N First Pixel
13 CH1_0P First Pixel
14 CH1_1N First Pixel
15 CH1_1P First Pixel
16 CH1_2N First Pixel
17 CH1_2P First Pixel
18 GND Ground
19 CH1_CLKN
20 CH1_CLKP
21 GND Ground
22 CH1_3N First Pixel
23 CH1_3P First Pixel
24 CH1_4N First Pixel
25 CH1_4P First Pixel
26 N.C. No Connection
27 N.C. No Connection
28 CH2_0N Second Pixel
29 CH2_0P Second Pixel
30 CH2_1N Second Pixel
31 CH2_1P Second Pixel
32 CH2_2N Second Pixel
33 CH2_2P Second Pixel
34 GND Ground
35 CH2_CLKN
36 CH2_CLKP
37 GND Ground
38 CH2_3N Second Pixel
39 CH2_3P Second Pixel
40 CH2_4N Second Pixel
41 CH2_4P Second Pixel
42 N.C. No Connection
43 N.C. No Connection
44 GND Ground
First Pixel Negative LVDS differential clock input.
First Pixel Positive LVDS differential clock input.
Second Pixel Negative LVDS differential clock input.
Second Pixel Positive LVDS differential clock input.
Negative LVDS differential data input. Channel 0
Positive LVDS differential data input. Channel 0
Negative LVDS differential data input. Channel 1
Positive LVDS differential data input. Channel 1
Negative LVDS differential data input. Channel 2
Positive LVDS differential data input. Channel 2
Negative LVDS differential data input. Channel 3
Positive LVDS differential data input. Channel 3
Negative LVDS differential data input. Channel 4
Positive LVDS differential data input. Channel 4
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Negative LVDS differential data input. Channel 0
Positive LVDS differential data input. Channel 0
Negative LVDS differential data input. Channel 1
Positive LVDS differential data input. Channel 1
Negative LVDS differential data input. Channel 2
Positive LVDS differential data input. Channel 2
Negative LVDS differential data input. Channel 3
Positive LVDS differential data input. Channel 3
Negative LVDS differential data input. Channel 4
Positive LVDS differential data input. Channel 4
Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
(1)
(1)
(3)
(3)
(1)
(3)
(3)
(1)
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45 GND Ground
46 GND Ground
47 N.C. No Connection
48 Vin Power input (+12V)
49 Vin Power input (+12V)
50 Vin Power input (+12V)
51 Vin Power input (+12V)
Note (1) Please be reserved to open.
Note (2) Low or Open: VESA Format(default), connect to GND. High: JEIDA Format, connect to +3.3V.
Note (3) LVDS 4-Port Data Mapping
Port CH of LVDS Data Stream
1st Port First pixel 1, 5, 9, ..........., 1913, 1917
2nd Port Second pixel 2, 6, 10, ........., 1914, 1918
3rd Port Third pixel 3, 7, 11, ........., 1915, 1919
4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN2, 4 : 51281-1094 (Molex) or 7083K-F10N-00L(E&T)
Pin № Symbol Feature NOTE
1 N4
2 N3
3 N2
4 N1
5 NC
6 NC
7 NC
8 NC
9 VLED
10 VLED
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Negative of LED String
No Connection
Positive of LED String
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5.3 CONVERTER UNIT
CN1:
CI0114M1HR0-LF (CvilLux)
Pin № Symbol Feature
1
2
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Model No.: V460H1-LE2
Tentative
or equivalent
3
4
5
6
7
8
9
10
11 STAT US
12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN2, 4 : 51281-1094 (Molex) or 7083K-F10N-00L(E&T)
Pin № Symbol Feature NOTE
1 N4
2 N3
3 N2
4 N1
5 NC
6 NC
7 NC
8 NC
9 VLED
10 VLED
Negative of LED String
No Connection
Positive of LED String
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5.4 BLOCK DIAGRAM OF INTERFACE
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
ARx0 +
ARx0 -
ARx1 +
ARx1 -
ARx2 +
ARx2 -
ARx3 +
ARx3 -
ARx4 +
ARx4 -
ACLK +
ACLK -
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
100pF
100pF
100pF
100pF
100pF
100pF
RxOUT
AR0 Ω AR9
AG0 Ω AG9
AB0 Ω AB9
DE
PLL
BRx0 +
BRx0 -
BRx1 +
BRx1 -
BRx2 +
BRx2 -
BRx3 +
BRx3 -
BRx4 +
BRx4 -
BCLK +
BCLK -
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
100pF
100pF
100pF
100pF
100pF
100pF
PLL
BR0 Ω BR9
BG0 Ω BG9
BB0 Ω BB9
DCLK
DCLK
Timing
Controller
LVDS Receiver
(MASTER)
LVDS INPUT
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
The third and fourth pixel are followed the same rules.
CR0~CR9: Third pixel R data
CG0~CG9: Third pixel G data
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
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CB0~CB9: Third pixel B data
DR0~DR9: Fourth pixel R data
DG0~DG9: Fourth pixel G data
DB0~DB9: Fourth pixel B data
Note (1) A ~ D channel are first, second, third and fourth pixel respectively.
Note (2) The system must have the transmitter to drive the module.
Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line
when it is used differentially.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DE VS HS AB7 AB6AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Color
Black
Red
Green
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red (1023)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
Blue (1022)
Blue (1023)
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
1
0
0
0
1
1
1
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Data Signal
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
;
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
:
:
:
:
:
:
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
LVDS
Receiver
Clock
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
(=1/TC)
F
Spread spectrum
modulation frequency
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
F
clkin
- - 200 ps (3)
T
rcl
clkin_mod
F
- - 200 KHz
SSM
60 74.25 80 MHz
F
-2% - F
clkin
+2% MHz
clkin
(4)
LVDS
Receiver
Data
Setup Time Tlvsu 600 - - ps
(5)
Hold Time Tlvhd 600 - - ps
Fr5 97 100 103 Hz
Vertical
Active
Display
Te rm
Horizontal
Active
Display
Te rm
Frame Rate
F
117 120 123 Hz
r6
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Th 540 550 575 Tc
Display Thd 480 480 480 Tc
Blank Thb 60 70 95 Tc
(6)
Tv=Tvd+Tvb
Ё
Ё
Th=Thd+Thb
Ё
Ё
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (2ʼʳ ʳ ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˼˸˿ʳ˶˿˶˾ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼ˍʳ ʳ ʳ
˶˿˾˼ʻ˴ʼ
˙
ʳЊʳ˙
ˉʳѼʳ˧ʳѼʳ˧˻
ʳ
˙
ˈʳѼʳ˧ʳѼʳ˧˻ʳЊʳ˙
˶˿˾˼ʻ˼ʼ
ʳ
ʳ
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Model No.: V460H1-LE2
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INPUT SIGNAL TIMING DIAGRAM
Tv
DE
DCLK
DE
DATA
Th
Tc
Tvd
Thb
Tvb
Thd
Valid display data ( 480 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
3T
5T
7T
9T
11T
13T
14
Note (6) : (ODSEL) = H/L or open for 100/120Hz frame rate. Please refer to 5.1 for detail information
14
14
14
14
14
14
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram
below.
0V
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
Tentative
0.1V
cc
0.5ЉЉЉЉT1ЉЉЉЉ10ms
2
0ЉЉЉЉT
0ЉЉЉЉT
500ms ЉЉЉЉT
LVDS Signals
ЉЉЉЉ100ms
3
ЉЉЉЉ100ms
0ЉЉЉЉT7ЉЉЉЉT
0ЉЉЉЉT8ЉЉЉЉT
4
0V
2
3
Option Signals
(SELLVDS…)
Backlight (Recommended)
500msЉЉЉЉT
5
Power On
T
7
T
T
1
T
2
3
T
4
VALI D
Power Off
T
8
50%
T
5
50%
T
6
Power ON/OFF Sequence
Note.
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance. If T2<0,
that maybe cause electrical overstress failures.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Model No.: V460H1-LE2
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
LED Current IL
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
25±2
50±10
120±3.6
oC
%RH
mA
LCD Module
LCD
P
Field of View = 1º
mm
500
CS
-2000
Light Shield Room
(Ambient Luminance < 2 lux)
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR (6000) - - Note (2)
Response Time
Center Luminance of White L
White Variation
Cross Talk CT - - 4 % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Color Gamut
Viewing
Horizontal
Angle
Vertical
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Model No.: V460H1-LE2
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Gray to
gray
C
δW
=0°, θY =0°
Rx (0.646) Ry
Gx (0.335) -
θ
x
Viewing angle at
normal direction
Gy
Bx (0.152) -
By
Wx
Wy
θx+
θ
-
x
θY+
θ
Y
-
CR≥20
- 4.5 9 ms Note (3)
(450) - cd/m2Note (4)
- - 1.3 - Note (7)
Typ.-
0.03
(0.335)
(0.620)
(0.041)
0.285
0.293
Typ.+
0.03
-
-
-
-
-
(72) - % NTSC
80 88 80 88 80 88 -
Deg. Note (1)
80 88 -
Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80.
Normal
θ x = θ y = 0º
y-
θ
θX- = 90º
6 oϗclock
θy- = 90º
x-
θx−
y-
θ
y+
y+
θx+
12 oϗclock direction
θy+ = 90º
x+
θX+ = 90º
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Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
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Model No.: V460H1-LE2
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Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
Note (3) Definition of Gray-to-Gray Switching Time:
Optical Response
100 %
90 %
10 %
0 %
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
Gray to Gray
Switching Time
The driving signal means the signal of gray level 0, 255, 511, 767, and 1023.Gray to gray average
time means the average switching time of gray level 0, 255, 511, 767,1023 to each other.
Note (4) Definition of Luminance of White (LC):
Measure the luminance of gray level 1023 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
Time
Gray to Gray
Switching Time
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A
A
A
A
Note (5) Definition of Cross Talk (CT):
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Issue Date:Dec.10.2009
Model No.: V460H1-LE2
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CT = | Y
Where:
(a)
(0, 0)
Y
(D/8,W/2)
A, L
Y
(D/2,7W/8)
A, D
(b)
– YA | / Y
B
= Luminance of measured location without gray level 1023 pattern (cd/m2)
Y
A
= Luminance of measured location with gray level 1023 pattern (cd/m2)
Y
B
ctive Area
Gray 512
= Luminance of measured location without gray level 1023 pattern (cd/m2)
Y
A
= Luminance of measured location with gray level 1023 pattern (cd/m2)
Y
B
×
100 (%)
A
Y
A, U
Y
A, R
(D, W)
(D/2,W/8)
(7D/8,W/2)
(D/4,W/4)
Y
(D/8,W/2)
B, L
Y
(D/2,7W/8)
B, D
(0, 0)
ctive Area
Gray 0
Gray 1023
Gray 512
Y
B, U
Y
B, R
(3D/4,3W/4)
(D, W)
(D/2,W/8)
(7D/8,W/2)
ctive Area
Gray 0
(D/8,W/2)
Y
A, L
Y
(D/2,7W/8)
A, D
(0, 0)
Note (6) Definition of White Variation (
Measure the luminance of gray level 1023 at 5 points
δ
W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
δ
W):
Y
Y
A, R
(D, W)
(D/2,W/8)
A, U
(7D/8,W/2)
(D/8,W/2)
Y
B, L
(D/2,7W/8)
Y
B, D
(0, 0)
(D/4,W/4)
ctive Area
Gray 1023
Gray 0
Y
B, U
Y
(3D/4,3W/4)
(D, W)
(D/2,W/8)
(7D/8,W/2)
B, R
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Model No.: V460H1-LE2
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Horizontal Line
D
D
4
D
2
1 2
W
4
W
W
2
Vertical Line
3W
4
3 4
5
3D
4
X
Test point :
X = 1 ~ 5
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
к
recommended to store the module with temperature from 0 to 35
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
at normal humidity without
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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Model No.: V460H1-LE2
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CHI MEI
OPTOELECTRONICS
CHI MEI
OPTOELECTRONICS
Model Name: V460H1-LE2
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
V460H1 –LE2 Rev. XX
X X X X X X X Y M D L N N N N
V460H1 –LE2 Rev. XX
X X X X X X X Y M D L N N N N
Serial No.
Product Line
E207943
MADE IN TAIWAN
GEMN
RoHS
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
Serial ID includes the information as below:
Manufactured Date:
Year: 2001=1,2002=2,2003=3,2004=4…2010=0,2011=1,2012=2..
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
CMO Internal Use
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10. PACKAGING
10.1 PACKING SPECIFICATIONS
(1) 5 LCD TV modules / 1 Box
(2) Box dimensions : 1175(L)x282(W)x725(H)mm
(3) Weight : approximately 56 Kg ( 5 modules per box)
10.2 PACKING METHOD
Figures 10-1 and 10-2 are the packing method
LCD TV Module
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Cushion(Bottom)
Anti-static Bag
PP Belt
Carton Label
Figure.10-1 packing method
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(
)
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Air Transportation &
Sea / Land Transportation (40ft Container)
(L1130*50*50mm)
Film
(L1150*W1190*H140mm)
(L1400*50*50mm)
Gross: 465kg
Sea / Land Transportation (40ft HQ Container)
(L1130*50*50mm)
(L625*50*50mm)
Film
(L1400*50*50mm)
L1150*W1190*H140mm
Gross: 704kg
Figure.10-2 packing method
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11. MECHANICAL CHARACTERISTICS
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CHI MEI
࡛ભሽٝڶૻֆ
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࡛ભሽٝڶૻֆ
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