Please return 1 copy for your confirmation with your
signature and comments.
Approved By Checked By Prepared By
Chao-Chun Chung
Ken Wu
HT Hung
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PRODUCT SPECIFICATION
CONTENTS
1. GENERAL DESCRIPTION...................................................................................................................................................5
1.2 FEATURES ....................................................................................................................................................5
2. ABSOLUTE MAXIMUM RATINGS....................................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT....................................................................................................7
7.1 TEST CONDITIONS .....................................................................................................................................27
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9. DEFINITION OF LABELS..................................................................................................................................................34
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Version Date Page(New) Section Description
Ver. 2.0
Ver. 2.1
Ver. 2.2
Ver. 2.3
Jul. 27, 2011
Aug.04, 2011
Aug.30, 2011
Jan.17, 2012
All
18
6
9
13
35
37
12
12
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PRODUCT SPECIFICATION
REVISION HISTORY
All
5.3
1.5
3.1
3.2.2
10.2
11
3.2.1
3.2.2
The approval specification was first issued.
Modify 5.3 T-BALANCE BOARD UNIT Pin No.1,2,4,5
Add the tolerance of module weight
Modify 3.1 Power Supply Current, Black attern:0.32->0.38
Add Note (5) description.
Modify 10.2 illustration of module
Modify 11 MECHANICAL CHARACTERISTIC
LAMP SPECIFICATION
T-BALANCE BOARD INTERFACE CHARACTERISTICS
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V460H1-L12 is a 46” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display 16.7M colors (8-bit). The inverter module
for backlight isn’t built-in.
1.2 FEATURES
Ё High brightness (380 nits)
Ё High contrast ratio (4000:1)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
Ё LVDS (Low Voltage Differential Signaling) interface
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PRODUCT SPECIFICATION
Ё Optimized response time for 60 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHs compliance
1.3 APPLICATION
Ё Standard Living Room TVs
Ё Public Display Application
Ё Home Theater Application
Ё MFM Application
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1018.08(H) x 572.67(V) (46” diagonal) mm
Bezel Opening Area 1024.4(H) x 578.6(V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel-
Pixel Pitch(Sub Pixel) 0.17675(H) x 0.53025(V) mm -
Pixel Arrangement RGB vertical stripe - -
(1)
Display Colors 16.7M color-
Display Operation ModeTransmissive mode / Normally Black - -
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) Please refer sec 3.1 and 3.2 for more information of Power consumption
Note (3) The spec. of the surface treatment is temporarily for this phase. CMI reserves the rights to change this feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 1081.8 1083 1084.2 mm (1)
Vertical (V) 626 627 628 mm (1)
Module Size
Depth (D) -- mm (2)
Depth (D) 50 51 52 mm (3)
Weight 10780 11280 11780 g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
Note (3) Module Depth is between bezel to rear.
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 35 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(a) 90 %RH Max. (Ta
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
Љ 40 ºC).
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
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PRODUCT SPECIFICATION
store the module with temperature from 0 to 35
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
к at normal humidity without condensation.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Value
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT T-BALANCE BOARD UNIT
Item Symbol
Lamp Voltage VW
Min. Max.
Value
Min. Max.
Ё
3000 VRMS
Unit Note
(1)
Unit Note
Input Voltage VBL 0 170 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Ё
-0.3 7 V (1)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Rush Current I
RUSH
Power consumption P
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
LVDS
interface
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(single-end)
V
V
|V
Terminating Resistor R
CMIS
interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
T
Ё Ё
Ё Ё
Ё Ё
LVT H
LVTL
| 200
ID
T
0
IL
+100
Ё Ё
Ё
8.64 10.82 W (3)
0.42
0.72 0.82 A
0.38
Ё Ё
Ё Ё
Ё
Ё
100
Ё
Ё
Note (1) The module should be always operated within the above ranges.
3 A (2)
Ё
A
(4)
Ё
A
mV
-100 mV
(5)
600 mV
Ё
ohm
3.3 V
0.7 V
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PRODUCT SPECIFICATION
GND
Vcc rising time is 470us
0.9Vcc
0.1Vcc
470us
Vcc
Note (3) The Specified Power consumption is under Horizontal Stripe
Note (4) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
pattern.
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= 60 Hz,
v
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PRODUCT SPECIFICATION
c. Horizontal Pattern
a. White Pattern
Active Area
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows :
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION (Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
PRODUCT SPECIFICATION
Value
Unit Note
Lamp Input Voltage VW - 970 - V
Lamp Current IL 14 14.5 15 mA
- - 1670 V
I
RMS
RMS
(1) , Ta = 0 ºC
RMS
L
Lamp Turn On Voltage VS
- - 1390 V
(1) , Ta = 25 ºC
RMS
Operating Frequency FO 30 - 80 KHz (2)
Lamp Life Time LBL 50,000 - - Hrs (3)
2
-10%ʳ
10% (6)
2
2
+10%
(6)
Unsymmetrical ratio UR
Crest factor C.F.ʳ
3.2.2 T-BALANCE BOARD INTERFACE CHARACTERISTICS
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Operating Voltage VBL
Min. Typ. Max.
Ё
+90 Ё V
Unit Note
VBL=VBL+ to VBL-
RMS
Sine Wave
=14.5mA
Total Power Consumption
Total Input Current
Oscillating Frequency FW 38 40 42 KHz
Individual Lamp Current IL 14.0 14.5 15.0 mA (3)
Protection Circuit Supply
Voltage
Input Connector Open
Detection
Lamp Open Detection
PWM Dimming Frequency FB 150
PWM Dimming Duty Ratio D
Striking Frequency Fs 44
Striking Time Ts 1 1.5 2 Sec
High2 5 13.2 V Normal Operation
Low
High2
Low
P
BL
I
BL
Vcc 0 5 13.2 V
CNT
PT
20
MIN
Ё
148.5 154.8 W IL =14.5mA
Ё
Ё
0
1.65 1.72 A Non Dimming
Ё
Ё
Ё
160 170
Ё
Ё
0.8 V Input Connector Open
Ё
1.4 V Normal Operation
100 %
52 KHz
V Lamp Open
Hz
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Parameter Symbol
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Open One Lamp Operating
Voltage
Open All Lamp Operating
Voltage
Backlight Turn On Voltage VBS 1700
VBL 60
VBL 115
Ё
Ё
2300
90 V
160 V
V
RMS
RMS
RMS
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
master and slave board.
Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second after startup.
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference,
the lamp frequency should be detached from the horizontal synchronous frequency and its
harmonics as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value
and the effective discharge length is longer than 80% of its original length (Effective discharge
length is defined as an area that has equal to or more than 70% brightness compared to the
brightness at the center point of lamp.) as the time in which it continues to operate under the
condition at Ta = 25 ±2
к and I
= (14.0~ 15.0) mArms.
L
Note (5) The IPI/IPB should design proper protection circuit to shut down if abnormal signals occurred of
CNT/PT/FB
Note (6) Unsymmetrical ratio =
ЮI+p – I-pЮ/ Irms *100%
Crest factor = I+p (or I-p) / Irms
Please light on the lamp with symmetric waveform, both voltage & current.
I+p
I-p
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)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
(B-F,187059-51221 (P-TWO)) or equivalent
INPUT CONNECTOR
CONTROLLER
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PRODUCT SPECIFICATION
TIMING
SCAN DRIVER
TFT LCD PANEL
(1920x3x1080)
Data Driver (mini-LVDS
SELLVDS
VIN
GND
VBL+
VBL-
SGND
Vcc
CNT
PT
FB1
FB2
DC/DC CONVERTER
T-Balance Board
CN1:
CI0112M1HR0-LA(Cvilux)
or
S12B-PH-SM3-TB (JST)
Cvilux
CN2-CN13:
CPLB0VA100B-NH
BACKLIGHT
UNIT
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PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD INTERFACE
CNF1 Connector Part No.: B-F,187059-51221 (P-TWO) or equivalent.
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (3)(4)
8 N.C. No Connection (2)
9 N.C No Connection (2)
10 N.C. No Connection (2)
11 GND Ground
12 ERX0- Even pixel Negative LVDS differential data input. Channel 0
13 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
14 ERX1- Even pixel Negative LVDS differential data input. Channel 1
15 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
16 ERX2- Even pixel Negative LVDS differential data input. Channel 2
17 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 ECLK- Even pixel Negative LVDS differential clock input.
20 ECLK+ Even pixel Positive LVDS differential clock input.
21 GND Ground
22 ERX3- Even pixel Negative LVDS differential data input. Channel 3
23 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
24 N.C. No Connection
25 N.C. No Connection
26 GND Ground
27 GND Ground
28 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
29 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
30 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
31 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
32 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
33 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK- Odd pixel Negative LVDS differential clock input
36 OCLK+ Odd pixel Positive LVDS differential clock input
37 GND Ground
38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
39 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
40 N.C. No Connection
41 N.C. No Connection
42 GND Ground
43 GND Ground
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (2)
48 VCC Power input (+12V)
49 VCC Power input (+12V)
50 VCC Power input (+12V)
51 VCC Power input (+12V)
(2)
(5)
(5)
(5)
(2)
(5)
(5)
(5)
(2)
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Note (1) LVDS connector pin order defined as follows
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PRODUCT SPECIFICATION
Note (2) Reserved for internal use. Please leave it open.
Note (3)
SELLVDS Mode
L JEIDA
H(default) VESA
L: Connect to GND, H: Connect to Open or +3.3V
Note (4) LVDS signal pin connected to the LCM side has the following diagram. R1 in the system side should be
less than 1K Ohm. (R1 < 1K Ohm)
Note (5) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel
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Note (6) LVDS connector mating dimension range request is 0.93mm~1.0mm as follow
5.2 BLU UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
Pin Name Description Wire Color
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PRODUCT SPECIFICATION
1 HV High Voltage White
2 HV High Voltage Pink
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
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5.3 T-BALANCE BOARD UNIT
CN1: CI0112M1HR0-LA (CviLux) or S12B-PH-SM3-TB (JST)
Pin №Signal nameFeature
1 VBL+ +90 V Sine Wave
2 VBL+ +90 V Sine Wave
3 N.C No Connect
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PRODUCT SPECIFICATION
4 VBL-
5 VBL-
6 N.C No Connect
7 SGND Signal GND
8 VCC 5V
9 CNT +5V
10 PT +2V
11 FB1 Lamp current feedback 1
12 FB2 Lamp current feedback 2
-90 V Sine Wave
-90 V Sine Wave
CN2-CN13: CPLB0VA100B-NH (CviLux)
Pin № Signal nameFeature
1 CFL HOT CFL High voltage
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5.4 BLOCK DIAGRAM OF INTERFACE
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PRODUCT SPECIFICATION
ER0~ER7 Even pixel R data OR0~OR7 Odd pixel R data
EG0~EG7 Even pixel G data OG0~OG7 Odd pixel G data
EB0~EB7 Even pixel B data OB0~OB7 Odd pixel B data
DE Data enable signal
DCLK Data clock signal
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PRODUCT SPECIFICATION
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = H or Open
RXCLK
RXCLK
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PRODUCT SPECIFICATION
Current F\FOH
Current F\FOH
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
JEIDA Format : SELLVDS = L
RXCLK
RXCLK
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
Current F\FOH
Current F\FOH
G3G2G4
G3G2G4
G3G2G4
G3G2G4
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R7G2R6R5R4R3
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R7G2R6R5R4R3
B2G7B3
B2G7B3
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
G5G4G6
G5G4G6
G5G4G6
G5G4G6
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
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R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus