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Issue Date: Feb.02.2010
Model No.: V420H2-LN1
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CONTENTS
REVISION HISTORY ..................................................................................................................................................4
1. GENERAL DESCRIPTION......................................................................................................................................5
1.2 FEATURES ....................................................................................................................................................5
2. ABSOLUTE MAXIMUM RATINGS...........................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT....................................................................................................7
7.1 TEST CONDITIONS..................................................................................................................................... 26
9. DEFINITION OF LABELS......................................................................................................................................31
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 982.0 983.0 984.0 mm
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Module Size
Weight - 9500 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to Rear.
Vertical (V) 575.0 576.0 577.0 mm
Depth (D) 34.1 35.1 36.1 mm
(1), (2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
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Value
Unit Note
Min. Max.
(a) 90 %RH Max. (Ta
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
Љ
40 ºC).
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
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store the module with temperature from 0 to 35
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT INVERTER UNIT
Item Symbol
Lamp Voltage VW
к
at normal humidity without condensation.
Value
Unit Note
Min. Max.
Value
Unit Note
Min. Max.
Ё
3000 VRMS
(1)
Power Supply Voltage VBL 0 30 V (1)
Ё
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
-0.3 7 V (1), (3)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
LVDS
interface
CMOS
interface
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
Common Input Voltage V
Terminating Resistor R
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage V
Vertical Stripe
Black Pattern
- - 4.3 A (2)
RUSH
-
-
-
1.125 1.25 1.375 V
LVC
- 100 - ohm
T
0 - 0.7 V
IL
- 0.84 1.1 A
- 0.83 - A
- 0.48 - A
(3)
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
GND
Vcc rising time is 470us
0.9Vcc
0.1Vcc
470us
Vcc
= 60 Hz,
v
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a. White Pattern
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b. Black Pattern
Note (4) The LVDS input characteristics are as follows:
Active Area
Active Area
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
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Value
Unit Note
Lamp Input Voltage VL - 1090 -
Lamp Current IL 10.0 10.5 11.0
- - 1910
Lamp Turn On Voltage VS
- - 1560
Operating Frequency FL 35 - 70
Lamp Life Time LBL 50,000 - -
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
master and slave board.
Note (2) The lamp starting voltage V
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
should be applied to the lamp for more than 1 second after startup.
S
Lamp Input
Voltage
Lamp
Current
Lamp Turn
On Voltage
Operating
Frequency
Lamp Life
Time
VL
IL
VS
FL
LBL
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
±2
к
and IL =
˄˃ˁ˃˄˄ˁ˃
mArms.
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)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
SELLVDS
ODSEL
(FI-RE51S-HF (JAE)) or equivalent
INPUT CONNECTOR
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FRAME
BUFFER
TIMING
CONTROLLER
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SCAN DRIVER
TFT LCD PANEL
(1920x3x1080)
DATA DRIVER(RSDS
Vcc
GND
DC/DC CONVERTER
& REFERENCE
VOLTAGE
GENERATOR
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (3)(5)
N.C. No Connection
8
9 ODSEL
10 N.C. No Connection (2)
11 GND Ground
12 ERX0- Even pixel Negative LVDS differential data input. Channel 0
13 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
14 ERX1- Even pixel Negative LVDS differential data input. Channel 1
15 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
16 ERX2- Even pixel Negative LVDS differential data input. Channel 2
17 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 ECLK- Even pixel Negative LVDS differential clock input
20 ECLK+ Even pixel Positive LVDS differential clock input
21 GND Ground
22 ERX3- Even pixel Negative LVDS differential data input. Channel 3
23 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
24 N.C. No Connection
25 N.C. No Connection
26 GND Ground
27 GND Ground
28 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
29 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
30 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
31 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
32 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
33 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK- Odd pixel Negative LVDS differential clock input.
36 OCLK+ Odd pixel Positive LVDS differential clock input.
37 GND Ground
38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
39 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
40 N.C. No Connection
41 N.C. No Connection
42 GND Ground
43 GND Ground
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (2)
Overdrive Lookup Table Selection
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(2)
(2)
(4)(6)
(7)
(7)
(7)
(2)
(7)
(7)
(7)
(2)
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g
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
Note (1) LVDS connector pin orderdefined as follows
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Note (2) Reserved for internal use. Please leave it open.
Note (3)
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
Low = Open or connect to GND, High = Connect to +3.3V
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
Low = Open or connect to GND: VESA Format, High = Connect to +3.3V: JEIDA Format.
frame rate to optimize image quality.
ODSEL Note
L or open Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
R2R1
Selector (pin7)
Settin
TCON
System side
System side: R1 < 1K
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Note (6) ODSEL signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
TCON
TCON
R2
R1
R1
System side
System side
Note (7) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd
R2
R3
R3
SettingSelector (pin9)
SettingSelector (pin9)
LCM side
LCM side
pixel and the second pixel is even pixel.
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
Pin Name Description Wire Color
1 HV High Voltage White
2 HV High Voltage Pink
1 HV(White)
2 HV(Pink)
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1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
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p
p
OR0
5.3 BLOCK DIAGRAM OF INTERFACE
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ER0-ER7
-
-
OR0-OR7
-
-
Host
Graphics
Controller
ERx0+
-
ERx1+
ERx1-
ERx2+
-
ERx3+
ERx3-
ECLK+
-
ORx0+
-
ORx1+
ORx1-
51
Ө
100pF
51
Ө
51Ө
100
F
Ө
51
51
Ө
100pF
51
Ө
51
Ө
100pF
51
Ө
RxOUT
ER0-ER7
-
-
-OR7
-
-
51
Ө
100pF
51
Ө
Timing
51
Ө
100pF
51
Ө
51Ө
100
F
Controller
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
ORx2+
ORx3+
ORx3-
OCLK+
51
Ө
51
51
51
51
51
100pF
Ө
Ө
100pF
Ө
Ө
100pF
Ө
-
-
LVDS Receiver
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ER0~ER7: Even pixel R data
EG0~EG7: Even pixel G data
EB0~EB7: Even pixel B data
OR0~OR7: Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7: Odd pixel B data
DE: Data enable signal
DCLK: Data clock signal
Notes (1) The system must have the transmitter to drive the module.
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Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
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5.5 LVDS INTERFACE
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VESA LVDS forma
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
Κʻ˦˘˟˟˩˗˦ʳ˼ː˟ʳʳ˸ʼ
Current F\FOH
Current F\FOH
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
G3G2G4
G3G2G4
G3G2G4
G3G2G4
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
ERX3
ERX3
JEDIA LVDS forma
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
Κʻ˦˘˟˟˩˗˦ʳ˼ː˛ʼ
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
Current F\FOH
Current F\FOH
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
G5G4G6
G5G4G6
G5G4G6
G5G4G6
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R2
R2
G3
G3
ERX2
ERX2
ERX3
ERX3
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B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
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R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
5.5 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus