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Global LCD Panel Exchange Center
TFT LCD Tentative Specification
MODEL NO.: V420H2 – LE5
www.panelook.com
Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentative
Customer:
Approved by:
Note:
Approved By
TV Head Division
Chao-Chun Chung
QA Dept. Product Development Div.
Reviewed By
Hsin-nan Chen WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
CY Chang Peggi Chiu
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentative
- CONTENTS -
REVISION HISTORY
1. GENERAL DESCRIPTION
1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2PACKAGE STORAGE
2.3ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
2.3.2 BACKLIGHT UNIT
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
3.2 BACKLIGHT CONVERTER UNIT
3.2.1
3.2.2 CONVERTER CHARACTERISTICS
LED LIGHT BARCHARACTERISTICS
3.2.3 CONVERTER INTERFACE CHARACTERISTICS
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
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3
4
5
7
13
5. INTERFACE PIN CONNECTION
5.1 TFT LCD MODULE
5.2 BACKLIGHT UNIT
5.3 CONVERTER UNIT
5.4 BLOCK DIAGRAM OF INTERFACE
5.5 LVDS INTERFACE
5.6 COLOR DATA INPUT ASSIGNMENT
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
9. PACKAGING
9.1 PACKING SPECIFICATIONS
9.2 PACKING METHOD
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
10.2 SAFETY PRECAUTIONS
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14
25
29
33
34
36
11. MECHANICAL CHARACTERISTICS
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
REVISION HISTORY
Version Date
Ver 0.0 Jan 27,10’ All All
Page
(New)
Section Description
Tentative Specification was first issued.
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V420H2- LE5 is 42” TFT Liquid Crystal Display module with LED Backlight and 4 ch-LVDS interface. This
module supports 1920 x 1080 Full HDTV format and can display 1.07G colors ( 8-bit +FRC). The converter
module for backlight is built-in.
1.2 FEATURES
- High brightness (450 nits)
- Ultra-high contrast ratio (6000:1)
- Faster response time (gray to gray average 4.5 ms)
- High color saturation NTSC (72%)
- Ultra wide viewing angle : 176(H)/176(V) (CR≥ 20) with Super MVA technology
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- DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
1.3 APPLICATION
- TFT LCD TVs
- Multi-Media Display
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 930.24 (H) x 523.26 (V) (42" diagonal) mm
Bezel Opening Area 937.24 (H) x 530.26 (V) mm
Driver Element a-si TFT active matrix -
Pixel Number 1920 x R.G.B. x 1080 pixel
Pixel Pitch (Sub Pixel) 0.1615 (H) x 0.4845 (V) mm
Pixel Arrangement RGB vertical stripe -
Display Colors 1.07G color
Display Operation Mode Transmissive mode / Normally Black -
Surface Treatment
Anti-Glare Coating (Haze 11%)
Hard Coating (3H)
-
(1)
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal(H) - 973.24 - mm (1)
Vertical(V) - 566.26 - mm (1)
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Depth(D) - 10.8 - mm
Depth(D)
Weight 7950
24.6 25.6 26.6
4
mm To converter
cover
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 +50 ºC (1), (2)
Shock (Non-Operating) S
Vibration (Non-Operating) V
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 ºC).Љ
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Value
Min. Max.
- 35 G (3), (5)
NOP
- 1.0 G (4), (5)
NOP
Unit Note
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of improper
thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so
that the module would not be twisted or bent by the fixture.
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10
Storage Range
Temperature (ºC)
5
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80 60 -20 40 0 20 -40
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time. It is highly recommended to
store the module with temperature from 0 to 35 at normal humidity without condensation.к
(b)The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage Vcc -0.3 13.5 V
Input Signal Voltage VIN -0.3 3.6 V
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Value
Min. Max.
Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Unit Note
2.3.2 BACKLIGHT UNIT
Item Symbol
Light Bar Voltage VW Ta = 25 к - - 60 V
Converter Input Voltage VBL - 0 - 30 V
Control Signal Level - - -0.3 - 7 V
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Functional operation
should be restricted to the conditions described under normal operating conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
Te st
Condition
Min. Type Max. Unit Note
RMS
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3. ELECTRICAL CHARACTERISTICS
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
3.1 TFT LCD MODULE
Parameter Symbol
Power Supply Voltage V
Rush Current I
White Pattern
Power
Horizontal
Supply
Stripe
Current
Black Pattern
Differential
Input High
Threshold
V
Voltage
Differential
LVDS
interface
Input Low
Threshold
Voltage
Common Input
V
Voltage
Differential
input voltage
Terminating
Resistor
Ta = 25 ± 2 ºC
Value
Unit Note
Min. Typ. Max.
CC
RUSH
-
-
-
+100 - - mV
LVT H
LVT L
V
CM
| 200 - 600 mV
|V
ID
R
T
10.8 12 13.2 V (1)
- - 4.38 A (2)
- 1.27 1.65 A
- 1.32 1.72 A
- 0.58 - A
- - -100 mV
1.0 1.2 1.4 V
- 100 - ohm
(3)
(4)
Input High
2.7 - 3.3 V
0 - 0.7 V
CMOS
interface
Threshold
Voltage
Input Low
Threshold
V
IH
V
IL
Voltage
Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
Note (3) The specified power supply current is under the conditions at Vcc =12V, Ta = 25 ± 2 ºC, fv = 120 Hz,
whereas a power dissipation check pattern below is displayed.
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
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a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT CONVERTER UNIT
3.2.1 LED LIGHT BARCHARACTERISTICS(Ta = 25 ± 2 ºC)
Parameter Symbol
Light Bar Voltage V
LED Forward Voltage V
LED Current I
3.2.2 CONVERTER CHARACTERISTICS(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Consumption PBL - TBD TBD W
Converter Input Voltage V
Converter Input Current I
Dimming Frequency FB 150 160 170 Hz
W
f
L
BL
BL
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Value
Min. Typ. Max.
- 43.4 -
2.8 3.3
75.2 80 84.8
Value
Min. Typ. Max.
22.8 24 25.2
-
TBD
-
Unit Note
I
V
RMS
V
I
RMS
=80 mA
L
=80 mA
L
mA
Unit Note
V
DC
A
Tentativ e
Minimum Duty Ratio D
- 5 - %
MIN
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3.2.3 CONVERTER INTERFACE CHARACTERISTICS
External dimming: 150Hz~170Hz, duty ratio: 5%~100%
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Model No.: V420H2 – LE5
Tentativ e
Parameter Symbol
ON
On/Off Control Voltage
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
Status Signal
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
MAX
MIN
LO
LO
VBLON
VIPWM
HI
VEPWM
HI
Status
0
0
0
30
30
Value
Ё
Ё
Ё
0
Ё
Ё
Ё
ЁЁ
ЁЁ
Te st
Condition
Ё
Ё
Ё
ЁЁ
Ё
Ё
Ё
Ё
Ё
Ё
ЁЁЁ
Min. Typ. Max.
2.0
3.15
2.0
3.0 3.3 3.6 V Normal
Unit Note
5.0 V
0.8 V
3.45
Ё
5.0 V Duty on
0.8 V Duty off
0.8 V Abnormal
100 ms
maximum duty ratio
V
minimum duty ratio
V
ms
10%-90%V
ms
BL
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
BLON Delay Time
BLON Off Time Toff
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the converter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL → PWM signal → BLON
on
T
on1
ЁЁЁ
ЁЁЁ
ЁЁЁ
Ё
Ё
Ё
Ё
Ё
1
100
300
300
300
ЁЁ
ЁЁ
ЁЁ
ЁЁ
ЁЁ
100 ms
50 us
50 us
MΩ
ms
ms
ms
ms
Turn OFF sequence: BLOFF → PWM signal → VBL
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
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V
V
V
BL
V
BLON
EPWM
IPWM
9
Toff
%/
Tf1
9
%/
Tr1
9
%/
9
%/
2.0V
0.8V
Ton
Ton1
0
0
Backlight on duration
Tr
Tf
Ext. Dimming Function
PWMR
T
2.0V
0
0.8V
T
PWM
T
PWMF
Floating
3.3V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
12
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4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
CNF2: FI-RE41S-HF,JAE
Taiwan or equivalent
CH3_0(+/-)
CH3_1(+/-)
CH3_2(+/-)
CH3_3(+/-)
CH3_4(+/-)
CH3_CLK(+/-)
INPUT CONNECTOR
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Model No.: V420H2 – LE5
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SCAN DRIVER
CH4_0(+/-)
CH4_1(+/-)
CH4_2(+/-)
CH4_3(+/-)
CH4_4(+/-)
+
CH1_0(+/-)
CH1_1(+/-)
CH1_2(+/-)
CH1_3(+/-)
CH1_4(+/-)
CH1_CLK(+/-)
CH2_0(+/-)
CH2_1(+/-)
CH2_2(+/-)
CH2_3(+/-)
CH2_4(+/-)
CH2_CLK(+/-)
SELLVDS
Vcc
GND
-
CNF1: FI-RE51S-HF,JAE Taiwan
INPUT CONNECTOR
or equivalent
TIMING
CONTROLLE
DC/DC
TFT LCD PANEL
(1920x3x1080)
DATA DRIVER
VB
GND
CONVERTER
CN2-CN7:SM02 (13.0)-BDAS-3-TB(LF)(JST) or equivalent
CONNECTOR
Status
A_DIM
I_PWM
B
LON
CN1:S14B-PH-SM4-
TB(D)(LF) or
equivalent
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BACKLIGHT
UNIT
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5. INTERFACE PIN CONNECTION
5.1 TFT LCD MODULE
CNF1 Connector Pin Assignment (FI-RE51S-HF(JAE) or equivalent)
Pin Name Description Note
1 GND Ground
2 N.C. No Connection (1)
3 N.C. No Connection (1)
4 N.C. No Connection (1)
5 N.C. No Connection (1)
6 N.C. No Connection (1)
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7 SELLVDS LVDS Data Format Selection (2)
8 N.C. No Connection (1)
9 N.C. No Connection (1)
10 N.C. No Connection (1)
11 GND Ground
12 CH1[0]- First pixel Negative LVDS differential data input. Pair 0
13 CH1[0]+ First pixel Positive LVDS differential data input. Pair 0
14 CH1[1]- First pixel Negative LVDS differential data input. Pair 1
15 CH1[1]+ First pixel Positive LVDS differential data input. Pair 1
16 CH1[2]- First pixel Negative LVDS differential data input. Pair l 2
17 CH1[2]+ First pixel Positive LVDS differential data input. Pair 2
18 GND Ground
19 CH1CLK- First pixel Negative LVDS differential clock input.
20 CH1CLK+ First pixel Positive LVDS differential clock input.
21 GND Ground
22 CH1[3]- First pixel Negative LVDS differential data input. Pair 3
23 CH1[3]+ First pixel Positive LVDS differential data input. Pair 3
24 CH1[4]- First pixel Negative LVDS differential data input. Pair 4
25 CH1[4]+ First pixel Positive LVDS differential data input. Pair 4
26 N.C. No Connection (1)
27 N.C. No Connection (1)
28 CH2[0]- Second pixel Negative LVDS differential data input. Pair 0
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29 CH2[0]+ Second pixel Positive LVDS differential data input. Pair 0
30 CH2[1]- Second pixel Negative LVDS differential data input. Pair 1
31 CH2[1]+ Second pixel Positive LVDS differential data input. Pair 1
32 CH2[2]- Second pixel Negative LVDS differential data input. Pair 2
33 CH2[2]+ Second pixel Positive LVDS differential data input. Pair 2
34 GND Ground
35 CH2CLK- Second pixel Negative LVDS differential clock input.
36 CH2CLK+ Second pixel Positive LVDS differential clock input.
37 GND Ground
38 CH2[3]- Second pixel Negative LVDS differential data input. Pair 3
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39 CH2[3]+ Second pixel Positive LVDS differential data input. Pair 3
40 CH2[4]- Second pixel Negative LVDS differential data input. Pair 4
41 CH2[4]+ Second pixel Positive LVDS differential data input. Pair 4
42 N.C. No Connection (1)
43 N.C. No Connection (1)
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (1)
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
CNF2 Connector Pin Assignment (FI-RE41S-HF(JAE) or equivalent)
Pin Name Description Note
1 GND Ground
2 N.C. No Connection (1)
3 N.C. No Connection (1)
4 N.C. No Connection (1)
5 N.C. No Connection (1)
6 N.C. No Connection (1)
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7 N.C. No Connection (1)
8 N.C. No Connection (1)
9 GND Ground
10 CH3[0]- Third pixel Negative LVDS differential data input. Pair 0
11 CH3[0]+ Third pixel Positive LVDS differential data input. Pair 0
12 CH3[1]- Third pixel Negative LVDS differential data input. Pair 1
13 CH3[1]+ Third pixel Positive LVDS differential data input. Pair 1
14 CH3[2]- Third pixel Negative LVDS differential data input. Pair 2
15 CH3[2]+ Third pixel Positive LVDS differential data input. Pair 2
16 GND Ground
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17 CH3CLK- Third pixel Negative LVDS differential clock input.
18 CH3CLK+ Third pixel Positive LVDS differential clock input.
19 GND Ground
20 CH3[3]- Third pixel Negative LVDS differential data input. Pair 3
21 CH3[3]+ Third pixel Positive LVDS differential data input. Pair 3
22 CH3[4]- Third pixel Negative LVDS differential data input. Pair 4
23 CH3[4]+ Third pixel Positive LVDS differential data input. Pair 4
24 N.C. No Connection (1)
25 N.C. No Connection (1)
26 CH4[0]- Fourth pixel Negative LVDS differential data input. Pair 0
27 CH4[0]+ Fourth pixel Positive LVDS differential data input. Pair 0
28 CH4[1]- Fourth pixel Negative LVDS differential data input. Pair 1
29 CH4[1]+ Fourth pixel Positive LVDS differential data input. Pair 1
30 CH4[2]- Fourth pixel Negative LVDS differential data input. Pair 2
31 CH4[2]+ Fourth pixel Positive LVDS differential data input. Pair 2
32 GND Ground
33 CH4CLK- Fourth pixel Negative LVDS differential clock input.
34 CH4CLK+ Fourth pixel Positive LVDS differential clock input.
35 GND Ground
36 CH4[3]- Fourth pixel Negative LVDS differential data input. Pair 3
37 CH4[3]+ Fourth pixel Positive LVDS differential data input. Pair 3
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38 CH4[4]- Fourth pixel Negative LVDS differential data input. Pair 4
39 CH4[4]+ Fourth pixel Positive LVDS differential data input. Pair 4
40 N.C. No Connection (1)
41 N.C. No Connection (1)
Note (1) Reserved for internal use. Please leave it open.
Note (2) High=connect to +3.3V : JEIDA Format Ι Low= connect to GND or Open : VESA Format.
Note (3) Interface optional pin has internal scheme as following diagram. Customer should keep the interface
voltage level requirement as below.
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Model No.: V420H2 – LE5
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System Board
Panel
1K ohm
Interface Voltage
Level
VH > 3.0V
Note (4) LVDS 4-port Data Mapping
Port Channel of LVDS Data Stream
1st Port First Pixel 1, 5, 9, ……1913, 1917
2nd Port Second Pixel 2, 6, 10, ….1914, 1918
IC
>20K ohm
3rd Port Third Pixel 3, 7, 11, ….1915, 1919
4th Port Fourth Pixel 4, 8, 12, ….1916, 1920
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and leader wire is shown in the table below.
CN2-CN5 (Housing): 51281-1094 (Molex)
Pin No. Symbol Description
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Model No.: V420H2 – LE5
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1 VLED
2 VLED
3 NC
4 NC
5 N1
6 N2
7 N3
8 N4
9 N5
10 N6
Note (1) The backlight interface housing for high voltage side is a model
equivalent
. The mating header on converter part number is
Positive of LED String
No Connection
Negative of LED String
51281-0994
51281-0994
, manufactured by
Molex or
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5.3 CONVERTER UNIT
CN1(Header): S14B-PH-SM3-TB (JST) or equivalent
Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM control signal
13 I_PWM Internal PWM control signal
14 BLON Backlight on/off control
Notice:
VBL +24V Power input
GND Ground
Normal (3.3V)
Abnormal (0V)
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Model No.: V420H2 – LE5
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#PIN 12:PWM Dimming Control (Use Pin 12) : Pin 13 must open.
#PIN 13:Analog Dimming Control (Use Pin 13) : 0V~3.3V and Pin 12 must open.
#PIN 13(I_PWM) and Pin 12(E_PWM) can not open in same period.
CN2 - CN5 : 51281-1094 (Molex)
Pin № Symbol Feature
1
2 VLED53 VLED44 VLED35 VLED26 VLED17 NC
8 NC
9 VLED+
10 VLED+
VLED6-
Negative of LED String
No Connection
Positive of LED String
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5.4 BLOCK DIAGRAM OF INTERFACE
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
The third and fourth pixel are followed the same rules.
CR0~CR9: Third pixel R data
CG0~CG9: Third pixel G data
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
CB0~CB9: Third pixel B data
DR0~DR9: Fourth pixel R data
DG0~DG9: Fourth pixel G data
DB0~DB9: Fourth pixel B data
Note (1) A ~ D channel are first, second, third and fourth pixel respectively.
Note (2) The system must have the transmitter to drive the module.
Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8 AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5 AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4 AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSV : Reserved
AB6
AR2
DE VS HS AB7 AB6 AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0 AR0 REV
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Data Signal
Basic
Colors
Gray
Scale
Of
Red
Color
Black
Red
Green
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red Green Blue
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
;
:
:
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Red (1023)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
:
:
:
:
:
:
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Blue (1022)
Blue (1023)
Note (1) 0: Low Level Voltage, 1: High Level Voltage
00000000000000000000000000000000000000001111111111111111110
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency
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F
clkin
(=1/TC)
60 74.25 80 MHz
Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
LVDS
Receiver
Clock
LVDS
Receiver
Data
Vertical
Active
Display
Te rm
Horizontal
Active
Display
Te rm
Input cycle to
cycle jitter
T
rcl
ЁЁ
200 ps (3)
Spread spectrum
modulation range
clkin_mod
F
F
-2%
clkin
Ё
F
+2% MHz
clkin
(4)
Spread spectrum
F
modulation frequency
SSM
Setup Time Tlvsu 600
200 KHz
ЁЁ
ps
(5)
Hold Time Tlvhd 600
ЁЁ
ps
Fr5 TBD 100 TBD Hz
Frame Rate
F
TBD 120 TBD Hz
r6
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Th 540 550 575 Tc
Display Thd 480 480 480 Tc
Blank Thb 60 70 95 Tc
(6)
Tv=Tvd+Tvb
Ё
Ё
Th=Thd+Thb
Ё
Ё
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (2ʼʳ ʳ ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˼˸˿ʳ˶˿˶˾ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼ˍʳ ʳ ʳ
˙
˶˿˾˼ʻ˴ʼ
˙
ˈʳ Ѽʳ ˧ʳ Ѽʳ ˧˻ʳ Њʳ ˙
ʳЊʳ˙
ˉʳѼʳ˧ʳѼʳ˧˻
˶˿˾˼ʻ˼ʼ
ʳ
ʳ
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
INPUT SIGNAL TIMING DIAGRAM
Tv
Tvd
Tvb
DE
Th
DCLK
Thd
DE
DAT
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
Valid display data ( 480 clocks)
Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
14
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
3T
14
5T
14
7T
14
9T
14
11T
14
13T
14
Note (6) : (ODSEL) = H/L or open for 100/120Hz frame rate. Please refer to 5.1 for detail information
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
0V
0.5Љ ЉЉЉT1ЉЉЉЉ10ms
2
0Љ ЉЉЉT
0Љ ЉЉЉT
500ms Љ ЉЉЉT
LVDS Signals
ЉЉЉЉ 50ms
3
ЉЉЉЉ50ms
4
0V
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0.1V
CC
T
1
T
2
Power On
VA L I D
T
3
Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
0.1V
cc
T
4
Power Off
0Љ ЉЉЉT7ЉЉЉЉT
0Љ ЉЉЉT8ЉЉЉЉT
2
3
T
7
T
8
Option Signals
(SELLVDS,…)
Backlight (Recommended)
500msЉ ЉЉЉT
100ms
ЉЉЉЉ
5
T6
50%
T
5
Power ON/OFF Sequence
Note (1) The supply voltage of the external system fo
r the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
50%
T
6
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0,that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
LED Current IL 80 mA
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
25± 2
50± 10
oC
%RH
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7.2 OPTICAL SPECIFICATIONS
ʳ The relative measurement methods of optical characteristics are shown in 7.2. The following items should be ʳʳ
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR TBD (6000) - - Note (2)
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Response Time
Center Luminance of White LC (360) 450 - cd/m2Note (4)
White Variation
Cross Talk CT - - (4) % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Color Gamut C.G
Gray to
gray
δ W
Rx (0.644) -
θ x=0° , θ y =0°
Ry (0.335) -
Gx (0.329) -
Gy (0.624) -
Bx (0.152) -
By (0.044) -
Wx (0.280) -
Wy
Viewing angle
at normal direction
- (4.5) (9.0) ms Note (3)
- - (1.3) - Note (6)
TBD
(0.290)
-- (72) - % NTSC
TBD
-
-
θ x+
Horizontal
θ x-
Viewing Angle
θ Y+
Vertical
θ Y-
Note (1) Definition of Viewing Angle (θx, θy):
ʳ Viewing angles are measured by Autronic Conoscope Cono-80.
CR≥ 20
30
80 88 -
80 88 -
Deg. Note (1)
80 88 -
80 88 -
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
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Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
Note (3) Definition of Gray-to-Gray Switching Time:
pixels white all with Luminance Surface
pixels black all with Luminance Surface
The driving signal means the signal of gray level 0,127,255,383,511,639,767,895 and 1023.
Gray to gray average time means the average switching time of gray level 0,127,255,383,511,
639,767,895 and 1023 to each other.
Note (4) Definition of Luminance of White (L
ʳ
Measure the luminance of gray level 1023 at center point and 5 points
):
C
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
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Note (5) Definition of Cross Talk (CT):
ʳ
CT = | YB – YA | / YA × 100 (%)
ʳ
Where:
ʳ
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
ctive Area
Gray 512
(D/8,W/2)
Y
A, L
Y
(D/2,7W/8)
A, D
(0, 0)
Note (6) Definition of White Variation (
ʳ
Measure the luminance of gray level 1023 at 5 points
δ
W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
δ
W):
Y
A, U
Y
A, R
(D,W)
(D/2,W/8)
(7D/8,W/2)
(D/4,W/4)
Y
(D/8,W/2)
B, L
Y
(D/2,7W/8)
B, D
(0, 0)
ctive Area
Gray 0
Gray 0
Gray 128
Y
(D/2,W/8)
B, U
Y
(7D/8,W/2)
B, R
(3D/4,3W/4)
(D,W)
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8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
CHI MEI
OPTOELECTRONICS
V420H2 –LE5 Rev. XX
X X X X X X X Y M D L N N N N
(a) Model Name: V420H2-LE5
(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
(c) Serial ID: X X
X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
E 2 07943
MADE IN TAIWAN
GEMN
Serial ID includes the information as below:
(a) Manufactured Date: Year: 2001=1, 2002=2, 2003=3, 2004=4….2010=0, 2011=1, 2012=2....
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1
(b) Revision Code: Cover all the change
(c) Serial No.: Manufacturing sequence of product
(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.
Revision
CMO Internal Use
st
to 31st, exclude I ,O, and U.
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9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 5 LCD TV modules / 1 Box
(2) Box dimensions : 1085(L)x296(W)x653(H)mm
(3) Weight : Approx. TBD Kg(5 modules per carton)
9.2 PACKING METHOD
Figures 9-1 and 9-2 are the packing method
LCD TV Module
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Issued Date: Jan.27, 2010
Model No.: V420H2 – LE5
Tentativ e
Anti-Static Bag
Cushion(Bottom)
Carton
Cushion(Top)
PP Belt
Carton Label
Figure.9-1 packing method
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Sea / Land Transportation
(40ft Container)
Air Transportation
Figure.9-2 packing method
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10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD
modules in the specified storage conditions.
(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of LED light bar will be higher than that of room
temperature.
10.2 SAFETY PRECAUTIONS
(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling
with the converter. Do not disassemble the module or insert anything into the backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case
of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(3) After the module’s end of life, it is not harmful in case of normal operation and storage.
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11. MECHANICAL CHARACTERISTICS
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CHI MEI
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