25 ERX0- Even pixel Negative LVDS differential data input. Channel 0
26 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
27 ERX1- Even pixel Negative LVDS differential data input. Channel 1
28 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
29 ERX2- Even pixel Negative LVDS differential data input. Channel 2
30 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
31 GND Ground
32 ECLK- Even pixel Negative LVDS differential clock input.
33 ECLK+ Even pixel Positive LVDS differential clock input.
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34 GND Ground
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
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35 ERX3- Even pixel Negative LVDS differential data input. Channel 3
36 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
37 N.C. No Connection
38 N.C. No Connection
39 GND Ground
40 SCL EEPROM Serial Clock
41 N.C. No Connection
42 N.C. No Connection
43 WP EEPROM Write Protection
44 SDA EEPROM Serial Data
45 LVDS_SEL High(3.3V) or open for VESA, Low (GND) for JEIDA (4)
46 N.C. No Connection
47 N.C. No Connection
48 N.C. No Connection
49 N.C. No Connection
50 N.C. No Connection
(1)
(3)
(3)
(3)
51 N.C. No Connection
Note (1) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel
Note (2) LVDS connector pin order defined as follows
Note (3) Reserved for internal use. Please leave it open.
Note (4) Low: JEIDA LVDS Format (Connect to GND), High or open: VESA Format. (Connect to +3.3V)
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
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g
y
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
Vcc
Selector (pin45
stem side
System side
R1 < 1K
R1
)
R2
Settin
R3
TCON
LCM sideS
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5.2 LVDS INTERFACE
JEDIA FormatΚSELLVDS=L
RXCLK
RXCLK
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
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ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
VESA FormatΚSELLVDS=H or Open
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
Current F\FOH
Current F\FOH
G5G4G6
G5G4G6
G5G4G6
G5G4G6
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
G3G2G4
G3G2G4
G3G2G4
G3G2G4
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
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R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE: Data enable signal
DCLK: Data clock signal
Notes (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
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5.3 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of color
versus data input.
Color
R7 R6 R5 R4 R3 R2 R1 R0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Blue
Cyan
Magenta
Yel lo w
White
Red(0) / Dark
Red(1)
Red(2)
:
:
Red(253)
Red(254)
Red(255)
Green(0) / Dark
Green(1)
Green(2)
:
:
Green(253)
Green(254)
Green(255)
Blue(0) / Dark
Blue(1)
Blue(2)
:
:
Blue(253)
Blue(254)
Blue(255)
Note (1) 0: Low Level Voltage, 1: High Level Voltage
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
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Model No.: V400H1 - P02
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Data Signal
Red Green Blue
G7G6G5G
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G3 G2 G1 G0
4
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
1
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
B
B6 B5 B4 B3 B2
7
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
B1B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item SymbolMin. Typ. Max. Unit Note
Frequency
LVDS
Receiver
Clock
LVDS
Receiver
Data
Ver t ical
Active
Display
Term
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
Setup Time Tlvsu 600 - - ps
Hold Time Tlvhd 600 - - ps
Frame Rate
Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
F
clkin
(=1/TC)
- - 200 ps
T
rcl
clkin_mod
F
F
- - 200 KHz
SSM
Fr5 57 60 63 Hz
F
47 50 53 Hz
r6
60 74.25 80 MHz
F
-2%- F
clkin
+2%MHz
clkin
Approval
(3)
(4)
(5)
(6)
Ё
Ё
Horizontal
Active
Total Th 1050 1100 1150 Tc Th=Thd+Thb
Display Thd 960 960 960 Tc
Ё
Display
Term
Blank Thb
90 140 190
Tc
Ё
Note (1) Please make sure the range of pixel clock has follow the below equationΚ
Fclkin(max) Њ Fr6 Ѽ Tv Ѽ Th
Fr5 Ѽ Tv Ѽ Th Њ Fclkin(min)
Note (2) This module is operated in DE only mode and please follow the input signal timing diagram belowΚ
ʳ
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DE
T
h
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INPUT SIGNAL TIMING DIAGRAM
T
v
T
vd
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
T
vb
DCLK
T
hd
DE
DAT
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
Valid display data (960 clocks)
Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
3T
5T
7T
9T
11T
13T
14
Note (6) (ODSEL) = H/L or open for 50/60Hz frame rate. Please refer to 5.1 for detail information
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
0V
0.5ЉЉЉЉT1ЉЉЉЉ10ms
0ЉЉЉЉT
0ЉЉЉЉT
500ms ЉЉЉЉT
2
ЉЉЉЉ50ms
3
ЉЉЉЉ50ms
4
0.1V
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CC
T
1
T
2
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
0.1V
cc
T
3
T
4
LVDS Signals
0ЉЉЉЉT7ЉЉЉЉT2
0ЉЉЉЉT8ЉЉЉЉT3
0V
Signal selector
(SELLVDS…)
Backlight (Recommended)
500msЉЉЉЉT
100ms
ЉЉЉЉ
5
T6
Power On
T
7
T
5
Power ON/OFF Sequence
VA L I D
50%
50%
Power Off
T
8
T
6
NoteΚ
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Vertical Frame Rate Fr 60 Hz
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (7).
Item SymbolCondition Min. Typ. Max.UnitNote
Contrast Ratio CR 46006500
Response Time
Center Transmittance T%
White Variation
Red
Gray to
gray
δW
Rcx
Rcy
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CC
θ
=0°, θY =0°
x
With CMO Module
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
o
-
C
%RH
- (2), (4)
(2)
(2), (7)
-
-
25±2
50±10
12 V
-
6.5 12 ms (5)
- 4.6 - %
- - 1.3 -
0.647
0.327
Color
Chromaticity
Green
Blue
Gcx
Gcy
Bcx
Bcy
Wcx
θ
=0°, θY =0°
x
CS-1000T
Standard light source “C”
Typ -
0.03
0.296
0.600
0.144
0.083
0.335
Typ +
0.03
-
(1), (6)
-
-
-
White
-
Deg.(2), (3)
Viewing Angle
Horizontal
Ver t ical
Wcy
θx+
-
θ
x
θY+
-
θ
Y
CR≥20
With CMO Module
0.379
80 88
80
80
80
88
88
88
-
-
-
-
Note (1) Light source is the standard light source “C” which is defined by CIE and driving voltages are based on
suitable gamma voltages. The calculating method is as followingǺ
1. Measure Module’s and BLU’s spectrums. W, R, G, B are with signal input. BLU (for V400H1-L08) is
supplied by CMO.
2. Calculate cell’s spectrum.
3. Calculate cell’s chromaticity by using the spectrum of standard light source “C”
Note (2) Light source is the BLU which is supplied by CMO and driving voltages are based on suitable gamma
voltages.
Note (3) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80
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T
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
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Normal
θx = θy = 0º
θy-θy+
θX- = 90º
x-
θx−
6 o’clock
θ
y-
= 90º
y-
Note (4) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L1023: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (1), where CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (7).
Note (5) Definition of Gray to Gray Switching Time:
θx+
12 o’clock direction
y+
θ
y+
= 90º
x+
θX+ = 90º
100%
90%
Optical
Response
10%
0%
Gray to Gray
Switching Time
Gray to Gray
Switching Time
ime
The driving signal means the signal of gray level 0, 63, 127, 191, 255.
Gray to gray average time means the average switching time of gray level 0, 63, 127, 191, 255 to each
other.
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Note (6) Measurement Setup:
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be
executed after lighting backlight for 1 hour in a windless room.
LCD Module
LCD Panel
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Model No.: V400H1 - P02
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CS-2000
Field of View = 1º
500 mm
Note (7) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
D/4D/23D/4
W/4
W/2
W
Vertical Line
3W/4
Light Shield Room
(Ambient Luminance < 2lux)
Horizontal Line
D
12
: Test Point
5
34
X
X=1 to 5
Active Area
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8. DEFINITION OF LABELS
8.1 OPEN CELL LABEL
The barcode nameplate is pasted on each open cell as illustration for CMO internal control.
8.2 CARTON LABEL
The barcode nameplate is pasted on each box as illustration, and its definitions are as following explanation
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Model No.: V400H1 - P02
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V400H1-P02
XXXXXXXXXXXXXX
(a) Model Name: V400H1– P02
P.O. NO.
Parts ID.
Carton ID. Quantities 12
XXXXXXXXXXXXXX
Made in Taiwan
(b) Carton ID: CMO internal control
(c) Quantities: 12
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9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 12pcs LCD TV Panels / 1 Box
(2) Box dimensions: 1108 (L) X 738 (W) X 252 (H)
(3) Weight: approximately 36 Kg
9.2 PACKING METHOD
Figures 9-1 and 9-2 are the packing method
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Figure.9-1 packing method
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Global LCD Panel Exchange Center
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Issued Date: Nov. 19, 2009
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Figure. 9-2 Packing method
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10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the product during assembly.
(2) To assemble backlight or install module into user’s system can be only in clean working areas. The dust
and oil may cause electrical short or worsen the polarizer.
(3) It’s not permitted to have pressure or impulse on the module because the LCD panel will be damaged.
(4) Always follow the correct power sequence when the product is connecting and operating. This can
prevent damage to the CMOS LSI chips during latch-up.
(5) Do not pull the I/F connector in or out while the module is operating.
(6) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(7) It is dangerous that moisture come into or contacted the product, because moisture may damage the
product when it is operating.
(8) High temperature or humidity may reduce the performance of module. Please store this product within
the specified storage conditions.
(9) When ambient temperature is lower than 10ºC may reduce the display quality. For example, the
response time will become slowly.
10.2 SAFETY PRECAUTIONS
(1) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case
of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(2) After the product’s end of life, it is not harmful in case of normal operation and storage.
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11. MECHANICAL CHARACTERISTICS
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
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ڻႝηިҽԖϦљ
CHI MEI
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
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Global LCD Panel Exchange Center
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
ڻႝηިҽԖϦљ
CHI MEI
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One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
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