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V315H4-LE3
Specification
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CHIMEI INNOLUX V315H4-LE3 Specification

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MODEL NO.: V315H4
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PRODUCT SPECIFICATION
□ Tentative Specification □Preliminary Specification
■ Approval Specification
SUFFIX: LE3
Customer:
APPROVED BY SIGNATURE
Name / Title
Note
Approved By Checked By Prepared By
Chao-Chun Chung Ken Wu Carlos Lee
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PRODUCT SPECIFICATION
CONTENTS
1. GENERAL DESCRIPTION ......................................................................................................................................................... 5
1.1 OVERVIEW ..........................................................................................................................................................5
1.2 FEATURES ..........................................................................................................................................................5
1.3 APPLICATION...................................................................................................................................................... 5
1.4 GENERAL SPECIFICATIONS .............................................................................................................................5
1.5 MECHANICAL SPECIFICATIONS....................................................................................................................... 5
2. ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................... 6
2.1 ABSOLUTE RATINGS OF ENVIRONMENT ........................................................................................................ 6
2.2 PACKAGE STORAGE.......................................................................................................................................... 7
2.3 ELECTRICAL ABSOLUTE RATINGS .................................................................................................................. 7
3. ELECTRICAL CHARACTERISTICS ......................................................................................................................................... 8
3.1 TFT LCD MODULE ..............................................................................................................................................8
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION......................................................................................... 11
4. BLOCK DIAGRAM OF INTERFACE ...................................................................................................................................... 12
4.1 TFT LCD MODULE ............................................................................................................................................12
5. INPUT TERMINAL PIN ASSIGNMENT ................................................................................................................................ 13
5.1 TFT LCD Module Input....................................................................................................................................... 13
5.2 BACKLIGHT UNIT.............................................................................................................................................. 15
5.3 BLOCK DIAGRAM OF INTERFACE.................................................................................................................. 16
5.4 LVDS INTERFACE ............................................................................................................................................. 18
5.5 COLOR DATA INPUT ASSIGNMENT ................................................................................................................ 19
6. INTERFACE TIMING................................................................................................................................................................ 20
6.1 INPUT SIGNAL TIMING SPECIFICATIONS...................................................................................................... 20
6.2 POWER ON/OFF SEQUENCE..........................................................................................................................23
7. OPTICAL CHARACTERISTICS............................................................................................................................................... 24
7.1 TEST CONDITIONS...........................................................................................................................................24
7.2 OPTICAL SPECIFICATIONS .............................................................................................................................25
8. PRECAUTIONS .......................................................................................................................................................................... 29
8.1 ASSEMBLY AND HANDLING PRECAUTIONS .................................................................................................29
8.2 SAFETY PRECAUTIONS ..................................................................................................................................29
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PRODUCT SPECIFICATION
8.3 STORAGE PRECAUTIONS............................................................................................................................... 29
9. DEFINITION OF LABELS......................................................................................................................................................... 30
9.1 CMI MODULE LABEL ........................................................................................................................................30
10. MECHANICAL CHARACTERISTIC .................................................................................................................................... 31
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Version Date Page(New) Section Description Ver. 0. 0 Ver. 1. 0 Ver. 2. 0 Ver. 2. 1
Dec. 08, 2010
Dec.28, 2010 Jan. 14, 2011 Apr. 26, 2011
All All All 15
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PRODUCT SPECIFICATION
REVISION HISTORY
All All All
5.2
The tentative specification was first issued. The preliminary specification was first issued. The Approval Specification was first issued. Modify PIN ASSIGNMENT
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V315H4-LE3 is a TFT Liquid Crystal Display module with LED Backlight unit and 2ch-LVDS interface. The display
diagonal is 31.5”. This module supports 1920 x 1080 Full HDTV format and can display 16.7M colors (8-bit). The
converter module for backlight isn’t built-in.
1.2 FEATURES
Ё High contrast ratio (4000:1)
Ё Fast response time (8.5ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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PRODUCT SPECIFICATION
Ё LVDS (Low Voltage Differential Signaling) interface
Ё Viewing Angle : 176(H)/176(V) (CR>20) MVA Technology
Ё RoHs compliance
1.3 APPLICATION
Ё TFT LCD TVs
Ё Multi-Media Displays
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 697.92(H) x 392.58 (V) mm (1)
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x W. R.G.B. x 1080 pixel -
Pixel Pitch(Sub Pixel) 0.18175 (H) x 0.18175 (V) mm -
Pixel Arrangement wRGB square - -
Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally Black - -
Surface Treatment Anti-Glare coating (Haze 14%) / Hard Coating (3H) - (2)
Note (1) Please refer to the attached drawings for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMI reserves the rights to change this feature.
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 740.4 741.4 742.4 mm Module size
Module Size
Weight - 3710 - g -
Vertical (V) 435.0 435.8 436.6 mm Depth (D) 8.9 9.4 9.9 mm To rear
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
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PRODUCT SPECIFICATION
Value
Min. Max.
Unit Note
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage Vcc -0.3 13.5 V Input Signal Voltage VIN -0.3 3.6 V
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PRODUCT SPECIFICATION
Value
Min. Max.
Unit Note
(1)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power consumption
Horizontal Stripe
Black Pattern
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High Threshold Voltage
Differential Input Low
Threshold Voltage LVDS interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(single-end)
Terminating Resistor R
RUSH
ЁЁ
Ё
P
T
Ё
Ё
ЁЁ
ЁЁ
ЁЁ
V
V
|V
LVT H
LVT L
ID
T
+100
ЁЁ
| 200
Ё
3.7 A (2)
6.72 8.16 W
7.92 9.84 W
4.8 5.76 W
0.56 0.68 A
0.66 0.82 A
0.4 0.48 A
ЁЁ
mV
-100 mV
Ё
100
600 mV
Ё
ohm
(3)
(4)
(5)
CMIS interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
0
IL
Ё
Ё
3.3 V
0.7 V
Note (1) The module should be always operated within the above ranges.
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Note (2) Measurement ConditionsΚ
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PRODUCT SPECIFICATION
GND
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
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PRODUCT SPECIFICATION
Note (3) The Specified Power consumption is under a,b,c pattern.
Note (4) The Specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
= 60 Hz,
v
Note (5) The LVDS input characteristics are as follows :
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
PRODUCT SPECIFICATION
3.2.1 LED LIGHT BAR CHARACTERISTICS (
Ta = 25 ± 2 ºC)
The backlight unit contains 2 pcs light bar.
Parameter Symbol
Total Current (6 String) If
One String Current I
LED Forward Voltage V
One String Voltage V
One String Voltage Variation
ϦV
Life time -
Min. Typ. Max.
- 720 763.2
L
f
W
- - 2
W
- 120 127.2
3.0 3.25 3.5
51 - 59.5
30,000 - -
Value
Unit Note
mA
mA
I
V
DC
I
V
DC
V
Hrs (1)
Note (1) The lifetime is defined as the time which luminance of the LED decays to 50% compared to the
initial value, Operating condition: Continuous operating at Ta = 25±2 , Iк
=120mA.
L
=120mA
L
=120mA
L
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)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ER 0+/­ER 1+/­ER 2+/­ER 3+/­ER CLK+/-
OR 0+/­OR 1+/­OR 2+/­OR 3+/­OR CLK+/-
(FI-RE51S-HF (JAE)) or equivalent
INPUT CONNECTOR
FRAME
BUFFER
MEMC
SELLVDS
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PRODUCT SPECIFICATION
SCAN DRIVER
TFT LCD PANEL
(1920x2x1080 x2)
TIMING
CONTROLLER
Data Driver (mini-LVDS
VIN GND
DC/DC CONVERTER
& REFERENCE VOLTAGE
GENERATOR
CN2:51281-1094 (Molex) or equivalent
LED
BACKLIGHT
UNIT
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PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Part No.: JAE Taiwan FI-RE51S-HF or equivalent.
Pin Name Description Note
1 GND Ground 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 N.C. No Connection 6 N.C. No Connection 7 SELLVDS LVDS data format Selection (3) (4) 8 N.C. No Connection
9 N.C. No Connection 10 N.C. No Connection 11 GND Ground 12 ERX0- Even pixel Negative LVDS differential data input. Channel 0 13 ERX0+ Even pixel Positive LVDS differential data input. Channel 0 14 ERX1- Even pixel Negative LVDS differential data input. Channel 1 15 ERX1+ Even pixel Positive LVDS differential data input. Channel 1 16 ERX2- Even pixel Negative LVDS differential data input. Channel 2 17 ERX2+ Even pixel Positive LVDS differential data input. Channel 2 18 GND Ground 19 ECLK- Even pixel Negative LVDS differential clock input. 20 ECLK+ Even pixel Positive LVDS differential clock input. 21 GND Ground 22 ERX3- Even pixel Negative LVDS differential data input. Channel 3 23 ERX3+ Even pixel Positive LVDS differential data input. Channel 3 24 N.C. No Connection 25 N.C. No Connection 26 GND Ground 27 GND Ground 28 ORX0- Odd pixel Negative LVDS differential data input. Channel 0 29 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0 30 ORX1- Odd pixel Negative LVDS differential data input. Channel 1 31 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1 32 ORX2- Odd pixel Negative LVDS differential data input. Channel 2 33 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2 34 GND Ground 35 OCLK- Odd pixel Negative LVDS differential clock input. 36 OCLK+ Odd pixel Positive LVDS differential clock input. 37 GND Ground 38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3 39 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3 40 N.C. No Connection 41 N.C. No Connection 42 GND Ground 43 GND Ground 44 GND Ground 45 GND Ground
(2)
(2)
(5)
(5)
(5)
(2)
(5)
(5)
(5)
(2)
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46 GND Ground 47 N.C. No Connection (2) 48 VCC +12V power supply 49 VCC +12V power supply 50 VCC +12V power supply 51 VCC +12V power supply
Note (1) LVDS connector pin order defined as follows
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PRODUCT SPECIFICATION
Note (2) Reserved for internal use. Please leave it open.
Note (3) Low = Open or connect to GND: VESA Format, High = Connect to +3.3V: JEIDA Format.
Note (4) LVDS signal pin connected to the LCM side has the following diagram. R1 in the system side should be
less than 1K Ohm. (Ra < 1K Ohm)
Note (5) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel.
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN: 51281-0994 (Molex)
Pin № Symbol Feature
1 VLED+ Positive of LED String 2 NC 3 NC 4 N1 5 N2 6 N3 7 NC 8 NC 9 VLED+ Positive of LED String
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PRODUCT SPECIFICATION
NC
Negative of LED String
NC
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G0-EG
0
0
0
p
ORx0
O
p
OB0
CLK
OB0
5.3 BLOCK DIAGRAM OF INTERFACE
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PRODUCT SPECIFICATION
CNF1
ER0-ER7
E
EB
OR0-OR7
Host
Graphics
x
Controller
TxIN
-EB7
-
-OB7
D
ERx0+
ERx
ERx1+
7
ERx1-
ERx2+
ERx2-
ERx3+
7
ERx3-
100Ө
-
100pF
100Ө
100Ө
100
100Ө
100Ө
100pF
100Ө 100Ө
100pF
100Ө
F
RxOUT
ER0-ER7
E
EB
DE
OR0-OR7
-E
-EB7
-
7
7
-OB7
ECLK+
PLL
100Ө
-
100pF
100Ө
PLL
D
L
Timing
ORx0+
-
ORx1+
ORx1-
ORx2+
Rx2-
ORx3+
ORx3-
100Ө
100pF
100Ө
100Ө
100
100Ө
100Ө
100pF
100Ө 100Ө
100pF
100Ө
F
Controller
OCLK+
PLL
LVDS Transmitter
100Ө
-
100pF
100Ө
LVDS Receiver
PLL
THC63LVDM83A
(LVDF83A)
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PRODUCT SPECIFICATION
ER0~ER7: Even pixel R data
EG0~EG7: Even pixel G data
EB0~EB7: Even pixel B data
OR0~OR7: Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7: Odd pixel B data
DE: Data enable signal
DCLK: Data clock signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel.
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5.4 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=L or open)
RXCLK
RXCLK
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PRODUCT SPECIFICATION
Current F\FOH
Current F\FOH
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
JEDIA LVDS formatΚ(SELLVDS pin=H)
RXCLK
RXCLK
ORX0
ORX0
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
Current F\FOH
Current F\FOH
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
G3 G2G4
G3 G2G4
G3 G2G4
G3 G2G4
R2
R2
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
B2 G7B3
B2 G7B3
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
G5 G4G6
G5 G4G6
G5 G4G6
G5 G4G6
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
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PRODUCT SPECIFICATION
5.5 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color. The
higher the binary input, the brighter the color. The table below provides the assignment of the color versus data input.
Data Signal
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black Red
Green Basic Colors
Gray Scale Of Red
Gray Scale Of Green
Gray Scale Of Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Ye ll ow
White
Red (0) / Dark
Red (1)
Red (2)
:
: Red (253) Red (254) Red (255) Green (0) / Dark Green (1) Green (2)
:
: Green (253) Green (254) Green (255) Blue (0) / Dark Blue (1) Blue (2)
:
: Blue (253) Blue (254) Blue (255)
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0
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0
0
0
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0
0
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0
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0
0
1
1
1
1
1
1
0
0
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1
0 0 0 1 1 1 0 1 0 0 0
:
: 0 0 0 0 0 0
:
: 0 0 0 0 1 0
:
: 1 0 1
Version 2.1 19 DateΚΚΚΚ26 Apr 2011
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
LVDS
Receiver
Clock
Frequency
Input cycle to cycle jitter Spread spectrum modulation range
Spread spectrum modulation frequency
(=1/TC)
clkin_mod
F
F
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PRODUCT SPECIFICATION
F
clkin
T
rcl
SSM
60 74.25 80 MHz
ЁЁ
F
-2%
clkin
Ё
Ё
200 ps (3)
F
+2% MHz
clkin
(4)
200 KHz
LVDS
Setup Time Tlvsu 600
ЁЁ
Receiver
Data
Hold Time Tlvhd 600
ЁЁ
Fr5 47 50 53 Hz
Frame Rate
57 60 63 Hz
F
Ver t ical
Active
Display
Term
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
r6
Blank Tvb 35 45 55 Th
Horizontal
Active
Display
Term
Total Th 1050 1100 1150 Tc
Display Thd 960 960 960 Tc
Blank Thb 90 140 190 Tc
Note (1) Please make sure the range of frame rate has follow the below equationΚ
Fclkin(max) Fr6 Tv ThЊѼѼ
Fr5 Tv Th Fclkin(min)ѼѼЊ
ps
(5)
ps
Tv=Tvd+Tvb
Th=Thd+Thb
Version 2.1 20 DateΚΚΚΚ26 Apr 2011
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
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