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TFT LCD Tentative Specification
MODEL NO.:V315H3-P01
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
Customer:
Approved by:
Note:
TV Product Marketing & Management Div
Approved By
Chao-Chun Chung
QRA Dept. Product Development Div.
Reviewed By
Hsin-Nan Chen WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
Josh Chi Chris Chu
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
- CONTENTS -
REVISION HISTORY ------------------------------------------------------- 3
1. GENERAL DESCRIPTION
1.1 OVERVIEW
1.2 CHARACTERISTICS
1.3 MECHANICAL SPECIFICATIONS
------------------------------------------------------- 4
2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE V315B1-L01)
2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 7
3.1 TFT LCD OPEN CELL
4. BLOCK DIAGRAM ------------------------------------------------------- 10
4.1 TFT LCD OPEN CELL
5. INPUT TERMINAL PIN ASSIGNMENT ------------------------------------------------------- 11
5.1 TFT LCD MODULE
5.2 LVDS INTERFACE
5.3 COLOR DATA INPUT ASSIGNMENT
6. INTERFACE TIMING ------------------------------------------------------- 15
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 19
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. PRECAUTIONS ------------------------------------------------------- 23
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
8.2 SAFETY PRECAUTIONS
9. MECHANICAL DRAWING ------------------------------------------------------- 24
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
REVISION HISTORY
Version Date
Ver 0.0 22, Feb, 10’ All All Tentative Specification was first issued.
Page
(New)
Section Description
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V315H3-P01 is a 31.5” TFT Liquid Crystal Display module. This module supports 1920* 1080 HDTV format and
can display 16.7M colors (8 bit/color).
1.2 CHARACTERISTICS
CHARACTERISTICS ITEMS SPECIFICATIONS
Screen Diagonal [in] 31.51
Pixels [lines] 1920*1080
Active Area [mm] 698.4 (H) x 392.85 (V) (31.51” diagonal)
Sub -Pixel Pitch [mm] 0.12125 (H) x 0.36375 (V)
Pixel Arrangement RGB vertical stripe
Weight [g] TBD
Physical Size [mm] 716.1(W) x 410(H) x 1.79(D) Typ.
Display Mode Transmissive mode / Normally black
Contrast Ratio 6000:1 Typ.
(Typical value measured at CMO’s module)
Glass thickness (Array/CF) [mm] 0.7 / 0.7
Viewing Angle (CR>20) +88/-88(H),+88/-88(V) Typ.
(Typical value measured at CMO’s module)
Color Chromaticity R=(0.639, 0.327)
G=(0.288, 0.603)
B=(0.148, 0.048)
W=(0.280, 0.290)
(Typical value measured at CMO’s module)
Cell Transparency [и]
Polarizer (CF side) Glare coating,Hard coating (3H) 709.7(H) x 405(w)..
4.7%Typ.
(Typical value measured at CMO’s module)
Tentative
Polarizer (TFT side) Super Wide View, 709.7(H) x 405(w)..
1.3 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Weight - TBD - g -
I/F connector mounting
position
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
(2) Connector mounting position
The mounting inclination of the connector makes
the screen center within ±0.5mm as the horizontal.
+/- 0.5mm
(2)
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE V315B1-L01)
Item Symbol
Storage Temperature TST -20 +60 ºC (1), (3)
Operating Ambient Temperature T
Altitude Operating A OP 0 5000 M (3)
Altitude Storage A ST 0 12000 M (3)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 ºC).Љ
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation..
OP
Min. Max.
Value
0 50 ºC (1), (2), (3)
Unit Note
Tentative
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10
Storage Range
Temperature (ºC)
8060-20 400 20 -40
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in your product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of improper
thermal management in your product design.
Note (3) The rating of environment is base on LCD module. Leave LCD cell alone, this environment condition can’t
be guaranteed. Except LCD cell, the customer has to consider the ability of other parts of LCD module
and LCD module process.
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2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
Storage Condition : With shipping package.
Storage temperature range : 25±5 к
Storage humidity range : 50±10%RH
Shelf life : a month
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
Item Symbol
Power Supply Voltage VAA -0.3 +17.0 V
Power Supply Voltage VGH -0.3 +30.0 V
Power Supply Voltage VGL -10.0 -0.3 V
Logic Input Voltage VIN -0.3 4.0 V
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation should
be restricted to the conditions described under Normal Operating Conditions.
Value
Min Max
Unit
Note
(1)
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Model No.: V315H3-P01
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Unit Note
Tentative
Rush Current I
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage |VID| 200
Terminating Resistor R
CMOS
interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
RUSH
ЁЁ
ЁЁ
ЁЁ
V
LVT H
V
LVT L
T
0
IL
ЁЁ
0.98
0.98 1.2 A
0.51
+100
ЁЁ
ЁЁ
Ё
Ё
100
Ё
Ё
Note (1) The module should be always operated within the above ranges.
3.5 A (2)
Ё
A
(3)
Ё
A
mV
-100 mV
(4)
600 mV
Ё
ohm
3.3 V
0.7 V
Note (2) Measurement condition:
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Model No.: V315H3-P01
Tentative
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60 Hz, whereas a
power dissipation check pattern below is displayed.
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a. White Pattern
Active Area
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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4. BLOCK DIAGRAM
4.1 TFT LCD OPEN CELL
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
TFT LCD PANEL
(1920x3x1080)
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
X(L) BoardX(R) Board
C Board
INPUT CONNECTOR
(FI-RE51S-HF) or equivalent
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
SELLVDS
VCC
GND
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin assignment
Pin Name Description Note
1 VCC +12V power supply
2 VCC +12V power supply
3 VCC +12V power supply
4 VCC +12V power supply
5 VCC +12V power supply
6 GND Ground
7 GND Ground
8 GND Ground
9 GND Ground
10 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
11 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
12 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
13 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
14 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
15 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2
16 GND Ground
17 OCLK- Odd pixel Negative LVDS differential clock input
18 OCLK+ Odd pixel Positive LVDS differential clock input.
19 GND Ground
20 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
21 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
22 N.C. No Connection
23 N.C. No Connection
24 GND Ground
25 ERX0- Even pixel Negative LVDS differential data input. Channel 0
26 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
27 ERX1- Even pixel Negative LVDS differential data input. Channel 1
28 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
29 ERX2- Even pixel Negative LVDS differential data input. Channel 2
30 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
31 GND Ground
32 ECLK- Even pixel Negative LVDS differential clock input.
33 ECLK+ Even pixel Positive LVDS differential clock input.
34 GND Ground
35 ERX3- Even pixel Negative LVDS differential data input. Channel 3
36 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
37 N.C. No Connection
38 N.C. No Connection
39 GND Ground
40 SCL EEPROM Serial Clock
41 N.C. No Connection
42 N.C. No Connection
43 WP EEPROM Write Protection
44 SDA EEPROM Serial Data
45 LVDS_SEL High(3.3V) or open for VESA, Low (GND) for JEIDA (4)
46 N.C. No Connection
47 N.C. No Connection
48 N.C. No Connection
49 N.C. No Connection
50 N.C. No Connection
51 N.C. No Connection
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
(1)
(1)
(1)
(3)
(1)
(1)
(1)
(3)
(3)
(3)
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g
V
Note (1) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel
Note (2) LVDS connector pin order defined as follows
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
Note (3) Reserved for internal use. Please leave it open.
Note (4) Low: JEIDA LVDS Format (Connect to GND), High or open: VESA Format. (Connect to +3.3V)
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
cc
TCON
R1
Selector (pin45)
CN2(XR) Connector Pin Assignment
R2
R3
Settin
System side
LCM side
System side
R1 < 1K
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5.2 LVDS INTERFACE
JEDIA FormatΚSELLVDS=L
RXCLK
RXCLK
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
VESA FormatΚSELLVDS=H or Open
RXCLK
RXCLK
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
Current F\FOH
Current F\FOH
G5 G4G6
G5 G4G6
G5 G4G6
G5 G4G6
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE: Data enable signal
DCLK: Data clock signal
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
G3 G2G4
G3 G2G4
G3 G2G4
G3 G2G4
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
Notes (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
5.3 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of color versus data
input.
Data Signal
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red(0) / Dark
Red(1)
Red(2)
:
:
Red(253)
Red(254)
Red(255)
Green(0) / Dark
Green(1)
Green(2)
:
:
Green(253)
Green(254)
Green(255)
Blue(0) / Dark
Blue(1)
Blue(2)
:
:
Blue(253)
Blue(254)
Blue(255)
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
:
:
0
0
0
0
0
0
0
0
0
1
1
0
:
:
0
1
1
0
1
1
0
0
0
0
0
0
:
:
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
Tentative
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
1
1
0
:
:
:
:
0
1
1
0
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
F
clkin
(=1/TC)
T
- - 200 ps
rcl
clkin_mod
F
- - 200 KHz
F
SSM
LVDS
Receiver
Clock
LVDS
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
Setup Time Tlvsu 600 - - ps
Receiver
Data
Vertical
Active
Display
Te rm
Hold Time Tlvhd 600 - - ps
F
Frame Rate
r5
F
r6
Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Horizontal
Active
Total Th
Display Thd
Display
Te rm
Blank Thb
Note (1) Please make sure the range of pixel clock has follow the below equationΚ
60 74.25 80 MHz
F
-2% - F
clkin
+2% MHz
clkin
57 60 63
47 50 53
1050 1100 1150
960 960 960
90 140 190
Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
(3)
(4)
(5)
Hz
Hz
Tc Th=Thd+Thb
Tc
Tc
(6)
Ё
Ё
Ё
Ё
Fclkin(max) FЊ r6 Tv ThѼѼ
Fr5 Tv Th FѼѼЊclkin(min)
Note (2) This module is operated in DE only mode and please follow the input signal timing diagram belowΚ
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INPUT SIGNAL TIMING DIAGRAM
Tv
DE
DCLK
DE
DAT
Th
Tvd
Tvb
Thd
Valid display data ( 960 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
3T
5T
7T
9T
11T
13T
14
Note (6) (ODSEL) = H/L or open for 50/60Hz frame rate. Please refer to 5.1 for detail information
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14
14
17
14
14
14
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram below.
Tentative
0V
0.5ЉЉЉЉT1ЉЉЉЉ10ms
0ЉЉЉЉT
0ЉЉЉЉT
500ms ЉЉЉЉT
LVDS Signals
2Љ
Љ50ms
ЉЉ
3Љ
Љ50ms
ЉЉ
4
0ЉЉЉЉT7ЉЉЉЉT2
0ЉЉЉЉT8ЉЉЉЉT3
0V
Signal selector
(SELLVDS…)
Backlight (Recommended)
500msЉЉЉЉT
100msЉЉЉЉT6
5
0.1VCC
Power On
T7
0.1Vcc
T3T1
T2
T4
VA L I D
Power Off
T8
50%
50%
T5
6
T
Power ON/OFF Sequence
NoteΚ
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD operation
or the LCD turns off before the backlight turns off, the display may momentarily become abnormal screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5)Interface signal shall not be kept at high impedance when the power is on.
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage V
CC
25±2
50±10
5.0 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Inverter Current I
Inverter Driving Frequency F
L
L
5.2±0.5 mA
58±3 KHz
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown as below. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (5).
Item Symbol Condition Min. Typ. Max. Unit Note
Red
Green
Color
Chromaticity
Blue
White
Center Transmittance T% - 4.7 % (1), (7)
Contrast Ratio CR
Response Time
White Variation
Crosstalk CT
Horizontal
Viewing Angle
Vertical
Rx
Ry (0.327)
Gx
Gy (0.603)
Bx
By (0.046)
=0°, θY =0°
θ
x
Viewing angle at
normal direction
With CMO module
Typ.-0.03
Wx
Wy
=0°, θY =0°
θ
x
Gray to
gray
average
δW
With CMO Module
=0°, θY =0°
θ
x
With CMO
Module@60Hz
θ
=0°, θY =0°
x
4200 6000 - (1), (3)
-
With CMO Module
θx+
θ
x
θY+
θ
Y
-
CR≥20
With CMO Module
-
80 88 80
80
80
(0.639)
(0.288)
(0.148)
Typ+0.03
(0.28)
(0.29)
6.5 12
88 88 88 -
o
C
%RH
-
-
-
-
-
-
-
-
ms (4)
1.3 - (1), (6)
4 % (1), (8)
Deg.
Tentative
(1),(5)
Note (1) Light source is CMO’s V315H1-L01 BLU and driving voltages are based on suitable gamma voltages.
Note (2) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by EZ-Contrast 160R (Eldim)
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Normal
θx = θy = 0º
θy- θy+
θX- = 90º
6 o’clock
θ
y-
= 90º
x-
y-
Note (3) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L255 / L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5) ,where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
θx−
θx+
y+
12 o’clock direction
θ
y+
= 90º
x+
θX+ = 90º
Note (4) Definition of Gray-to-Gray Switching Time:
100%
90%
Optical
Response
10%
0%
Gray to gray
Switching time
The driving signal means the signal of Gray 0, 31, 63, 95, 127, 159, 191, 223, 255.
Gray to gray average time means the average switching time of Gray 0, 31, 63, 95, 127, 159, 191, 223,
255. to each other.
Note (5) Measurement Setup:
The LCD module should be stabilized at given temperature for 60 minutes to avoid abrupt temperature
Gray to gray
Switching time
Time
change during measuring. In order to stabilize the luminance, the measurement should be executed after
lighting Backlight for 60 minutes in a windless room.
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LCD Module
LCD Panel
Field of View = 1º
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Issued Date: Feb. 22, 2010
Model No.: V315H3-P01
Tentative
CS-2000
500 mm
Note (6) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
where L (X) is corresponding to the luminance of the point X at the figure below.
W/4
Light Shield Room
Ambient Luminance < 2 lux)
Horizontal Line
D
D/4 D/2 3D/4
1 2
: Test Point
W
W/2
5
X
X=1 to 5
Vertical Line
3W/4
Note (7) Definition of Transmittance(T%):
Module with suitable gamma voltage signal input.
Luminance of LCD module
Transmittance =
Luminance of backlight
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A
(
)
A
(
)
(
)
Note (8) Definition of Cross Talk (CT):
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Model No.: V315H3-P01
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Y
(D/8,W/2)
A, L
Y
(D/2,7W/8)
A, D
CT = | Y
Where:
(0, 0)
– YA | / YA× 100 (%)
B
= Luminance of measured location without gray level 0 pattern (cd/m2)
Y
A
Y
= Luminance of measured location with gray level 0 pattern (cd/m2)
B
ctive Area
Gray 128
Y
Y
A, R
D, W
A, U
(D/2,W/8)
(7D/8,W/2)
(D/4,W/4)
Y
(D/8,W/2)
B, L
Y
(D/2,7W/8)
B, D
0, 0
ctive Area
Gray 0
Gray 0
Gray 128
Y
(D/2,W/8)
B, U
Y
(7D/8,W/2)
B, R
(3D/4,3W/4)
D, W
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the product during assembly.
(2) To assemble backlight or install module into user’s system can be only in clean working areas. The dust and
oil may cause electrical short or worsen the polarizer.
(3) It’s not permitted to have pressure or impulse on the module because the LCD panel will be damaged.
(4) Always follow the correct power sequence when the product is connecting and operating. This can prevent
damage to the CMOS LSI chips during latch-up.
(5) Do not pull the I/F connector in or out while the module is operating.
(6) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
(7) It is dangerous that moisture come into or contacted the product, because moisture may damage the product
when it is operating.
(8) High temperature or humidity may reduce the performance of module. Please store this product within the
specified storage conditions.
(9) When ambient temperature is lower than 10ºC may reduce the display quality. For example, the response
time will become slowly.
8.2 SAFETY PRECAUTIONS
(1) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(2) After the product’s end of life, it is not harmful in case of normal operation and storage.
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