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PRODUCT SPECIFICATION
CONTENTS
1. GENERAL DESCRIPTION......................................................................................................................................5
1.2 FEATURES ....................................................................................................................................................5
2. ABSOLUTE MAXIMUM RATINGS ...........................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT....................................................................................................7
7.1 TEST CONDITIONS .....................................................................................................................................27
9. DEFINITION OF LABELS......................................................................................................................................34
11. INTERNATIONAL STANDARD ............................................................................................................................37
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) Please refer sec 3.1 and 3.2 for more information of Power consumption
Note (3) The spec. of the surface treatment is temporarily for this phase. CMI reserves the rights to change this feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 734.4 735.4 736.4 mm (1)
Vertical (V) 432 433 434 mm (1)
Module Size
Depth (D) 9.8 10.8 11.8 mm (2)
Depth (D) 30.7 31.7 32.7 mm (3)
Weight - 4300 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
Note (3) Module Depth is between bezel to converter cover.
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PRODUCT SPECIFICATION
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(a) 90 %RH Max. (Ta
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
Љ
40 ºC).
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
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PRODUCT SPECIFICATION
store the module with temperature from 0 to 35
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
к
at normal humidity without condensation.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Value
Item Symbol
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
Unit Note
(1)
2.3.2 BACKLIGHT CONVERTER UNIT
Value
Item Symbol
Light bar Voltage VW
Min. Max.
Ё
60 V
Unit Note
DC
Power Supply Voltage VBL 0 30 V (1)
Ё
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and External PWM Control.
-0.3 7 V (1), (3)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Rush Current I
White Pattern
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Ё
RUSH
Ё
Ё
Ё
3.0 A (2)
4.2 4.6 W
Power consumption
Power Supply Current
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(single-end)
Terminating Resistor R
CMIS
interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
Horizontal Stripe
Black Pattern
White Pattern
Horizontal Stripe
Black Pattern
Ё
Ё
Ё
Ё
Ё
V
LVT H
V
LVTL
| 180
|V
ID
T
0
IL
Ё
Ё
Ё
Ё
Ё
+100
Ё
Ё
6.1 7.4 W
4.2 4.6 W
0.35 0.38 A
0.51 0.62 A
0.35 0.38 A
Ё
Ё
Ё
100
Ё
Ё
Note (1) The module should be always operated within the above ranges.
(3)
(4)
Ё
mV
-100 mV
(5)
600 mV
Ё
ohm
3.3 V
0.7 V
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PRODUCT SPECIFICATION
GND
Vcc rising time is 470us
0.9Vcc
0.1Vcc
470us
Vcc
Note (3) The Specified Power consumption is under XXX pattern.
Note (4) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
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= 60 Hz,
v
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PRODUCT SPECIFICATION
c. Horizontal Pattern
a. White Pattern
Active Area
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows :
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3.2 BACKLIGHT CONVERTER UNIT
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PRODUCT SPECIFICATION
3.2.1 LED LIGHT BAR CHARACTERISTICS (
The backlight unit contains 2pcs light bar.
Parameter Symbol
Total Current (8 String) If
One String Current IL
LED Forward Voltage Vf
One String Voltage VW
Ϧ
One String Voltage Variation
Life time -
Note (1) The lifetime is defined as the time which luminance of the LED decays to 50% compared to the
initial value, Operating condition: Continuous operating at Ta = 25±2 , I
VW
3.2.2 CONVERTER CHARACTERISTICS (
Parameter Symbol
Power Consumption PBL - 41 46 W (1),(2) IL = 120 mA
Converter Input VoltageVBL
Converter Input CurrentIBL
Input Inrush Current - - - 2.69 Apeak
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio D
Note (1) The power supply capacity should be higher than the total converter power consumption PBL. Since
5 10 - % (4)
MIN
Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
- 960 1017.6
- 120 127.2
2.7 3.2 3.6
33.6 - 43.2
- - 2
30,000 - -
к
=120mA.
L
Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
22.8 24 25.2
-
1.7 1.92 A Non Dimming
Unit Note
VDC
Unit Note
mA
mA
VDC I
VDC I
V
Hrs (1)
=24V, (IL=typ.)
V
BL
=120mA
L
=120mA
L
(3)
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when converter dimming.
Note (2) The measurement condition of Max. value is based on 31.5" backlight unit under input voltage 24V,
average LED current 127.2 mA and lighting 1 hour later.
Note (3) The duration of rush current is about 30ms.
Note (4) 5% minimum duty ratio is only valid for electrical operation.
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3.2.3 CONVERTER INTERFACE CHARACTERISTICS
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PRODUCT SPECIFICATION
Parameter Symbol
ON
On/Off Control Voltage
OFF
External PWM Control
Voltage
Error Signal ERR
VBL Rising Time Tr1
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
HI
LO
VBLON
VEPWM
Te st
Condition
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Value
Min.Typ.Max.
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
5.25V
0.8 V
5.25V Duty on
0.8 V Duty off
Ё
Ё
100 ms
100 ms
50 us
50 us
2.0
0
2.0
0
Ё
30
Ё
Ё
Ё
Ё
Unit Note
(6)
Abnormal: Open
Ё
ms 10%-90%V
collector
Normal: GND
(4)
(5)
BL
Ё
Ё
Ё
Ё
Ё
Input Impedance Rin
PWM Delay Time TPWM
Ton
BLON Delay Time
T
on1
BLON Off Time Toff
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the
converter has a possibility to be damaged with wrong power sequence and control signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL → PWM signal → BLON
Turn OFF sequence: BLOFF → PWM signal → VBL
Note (4) When converter protective function is triggered, ERR will output open collector status.
Note (5)
Note (6)
The EPWM interface that inserts a pull up resistor to 5V in Max Duty (100%), please refers to Fig.2.
The BLON interface that inserts a pull up resistor to 5V, please refers to Fig.2.
1
1
300
300
300
Ё
Ё
Ё
Ё
Ё
Ё
MΩ
Ё
ms
Ё
ms
Ё
ms
Ё
ms
Fig.1
. For a certain reason, the
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PRODUCT SPECIFICATION
V
V
BL
V
BLON
EPWM
Tr1
%/
9
9
%/
2.0V
0.8V
Ton
Ton1
0
0
Toff
Backlight on duration
Tr
Tf
Ext. Dimming Function
PWMR
T
2.0V
0
0.8V
T
PWM
T
PWMF
Floating
V
W
EPWM
External
PWM
Period
5V +/- 5%
10k
>1M
ӨӨӨӨ
ӨӨӨӨ
10k
ӨӨӨӨ
Dimming
Circuit
External
PWM Duty
Fig. 1
Fig. 2
BLON
100%
5V +/- 5%
10k
>1M
ӨӨӨӨ
ӨӨӨӨ
10k
ӨӨӨӨ
ENA
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q
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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PRODUCT SPECIFICATION
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
SELLVDS
GND
Vcc
VBL
GND
ERR
E_PWM
BLON
(B-F,107C51-0000RA-G4) (Starconn)
INPUT CONNECTOR
or e
ual
Converter
CONNECTOR
CN1:
CI0114M1HR0-LF
(CvilLux) or
equivalent
FRAME BUFFER
TIMING
CONTROLLER
DC/DC CONVERTER &
REFERENCE VOLTAGE
GENERATOR
SCAN DRIVER IC
DATA DRIVER Mini-LVDS
CN2-CN3:51281-1094 (Molex) or equivalent
BACKLIGHT
UNIT
TFT LCD PANEL
(1920x3x1080)
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
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PRODUCT SPECIFICATION
CNF1 Connector Part No.: JAE Taiwan (
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (3)(4)
8 N.C. No Connection (2)
9 N.C No Connection
10 N.C. No Connection (2)
11 GND Ground
12 ERX0- Even pixel Negative LVDS differential data input. Channel 0
13 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
14 ERX1- Even pixel Negative LVDS differential data input. Channel 1
15 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
16 ERX2- Even pixel Negative LVDS differential data input. Channel 2
17 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 ECLK- Even pixel Negative LVDS differential clock input.
20 ECLK+ Even pixel Positive LVDS differential clock input.
21 GND Ground
22 ERX3- Even pixel Negative LVDS differential data input. Channel 3
23 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
24 N.C. No Connection
25 N.C. No Connection
26 GND Ground
27 GND Ground
28 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
29 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
30 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
31 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
32 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
33 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK- Odd pixel Negative LVDS differential clock input
36 OCLK+ Odd pixel Positive LVDS differential clock input
37 GND Ground
38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
39 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
40 N.C. No Connection
41 N.C. No Connection
42 GND Ground
43 GND Ground
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (2)
48 VCC Power input (+12V)
49 VCC Power input (+12V)
50 VCC Power input (+12V)
51 VCC Power input (+12V)
ሽ
) FI-RE51S-HF or equivalent.
(2)
(5)
(5)
(5)
(2)
(5)
(5)
(5)
(2)
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Note (1) LVDS connector pin order defined as follows
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PRODUCT SPECIFICATION
Note (2) Reserved for internal use. Please leave it open.
Note (3)
SELLVDS Mode
L(default)
H JEIDA
L: Connect to GND, H: Connect to +3.3V
Note (4) LVDS signal pin connected to the LCM side has the following diagram. R1 in the system side should be
less than 1K Ohm. (R1 < 1K Ohm)
VESA
TCON
TCON
R2
R2
R3
R3
Setting
Setting
Selector (pin7)
R1
R1
System side
Note (5) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel
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LCM side
LCM sideSystem side
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN:
51281-1094 (Molex)
Pin № Symbol Feature
1
2
3
4
5
6
7 N1
8 N2
9 N3
10 N4
5.3 CONVERTER UNIT
CN1(Header):
CI0114M1HR0-LF (CvilLux)
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PRODUCT SPECIFICATION
VLED+ Positive of LED String
NC NC
Negative of LED String
Notice
Pin №Symbol Feature
1
2
3
4
5
6
7
8
9
10
11 ERR
12 BLON BL ON/OFF
13 NC NC
14 E_PWM
VBL +24V
GND GND
Normal (GND)
Abnormal (Open
collector)
External PWM
Control
1. If Pin14 is open, E_PWM is 100% duty.
2. If Pin12 is open, BLU is turned on.
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CN2~3:
51281-1094 (Molex)
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PRODUCT SPECIFICATION
Pin № Symbol Feature
1
2
3
4
5
6
7 N1
8 N2
9 N3
10 N4
VLED+ Positive of LED String
NC NC
Negative of LED String
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G0-EG
0
G0-EG
0
0
p
ORx0
O
OG0
OB0
OG0
OB0
5.4 BLOCK DIAGRAM OF INTERFACE
TxIN
ER0-ER7
E
EB
7
-EB7
OR0-OR7
-OG7
-OB7
PLL
Host
Graphics
Controller
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PRODUCT SPECIFICATION
CNF1
ERx0+
ERx
-
ERx1+
ERx1-
ERx2+
ERx2ERx3+
ERx3-
ECLK+
ORx0+
ORx1+
ORx1-
ORx2+
Rx2-
ORx3+
ORx3-
-
-
100
Ө
100pF
100
Ө
100Ө
100
F
100
Ө
100
Ө
100pF
100
Ө
100
Ө
100pF
100
Ө
100
Ө
100pF
100
Ө
100
Ө
100pF
100
Ө
100Ө
100pF
Ө
100
100
Ө
100pF
100
Ө
100
Ө
100pF
100
Ө
PLL
RxOUT
ER0-ER7
E
EB
DE
OR0-OR7
DCLK
Timing
Controller
7
-EB7
-OG7
-OB7
PLL
OCLK+
100
Ө
100
100pF
Ө
-
PLL
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
LVDS Re ceiver
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PRODUCT SPECIFICATION
ER0~ER7 Even pixel R data OR0~OR7 Odd pixel R data
EG0~EG7 Even pixel G data OG0~OG7 Odd pixel G data
EB0~EB7 Even pixel B data OB0~OB7 Odd pixel B data
DE Data enable signal
DCLK Data clock signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=L or open)
RXCLK
RXCLK
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PRODUCT SPECIFICATION
Current F\FOH
Current F\FOH
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
JEDIA LVDS format
RXCLK
RXCLK
ORX0
ORX0
Κ
(SELLVDS pin=H)
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
Current F\FOH
Current F\FOH
R7G2R6R5R4R3
R7G2R6R5R4R3
G3G2G4
G3G2G4
G3G2G4
G3G2G4
R2
R2
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
B2G7B3
B2G7B3
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
G5G4G6
G5G4G6
G5G4G6
G5G4G6
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
Version 1.0 22 Date
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Dec. 20, 2010
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PRODUCT SPECIFICATION
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus