Please return 1 copy for your confirmation with your
signature and comments.
Approved By Checked By Prepared By
Chao-Chun Chung Vincent ChouWayne Lin
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PRODUCT SPECIFICATION
CONTENTS
1. GENERAL DESCRIPTION ......................................................................................................................................................... 5
1.2 FEATURES ..........................................................................................................................................................5
1.4 GENERAL SPECIFICATIONS .............................................................................................................................5
7.1 TEST CONDITIONS........................................................................................................................................... 27
9. DEFINITION OF LABELS......................................................................................................................................................... 32
Note (1) Please refer to the attached drawings in chapter 11 for more information about the front and back outlines.
Note (2) Please refer sec 3.1 and 3.2 for more information of Power consumption
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 759 760 761 mm (1)
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PRODUCT SPECIFICATION
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
Note (3) Module Depth is between bezel to Inverter cover.
Vertical (V) 449 450 451 mm (1)
Depth (D) 40.3 41.3 42.3 mm (2)
Depth (D) 46.9 47.9 48.9 mm (3)
Weight - 5150 - g -
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(1)
2.3.2 BACKLIGHT INVERTER UNIT
Value
Item Symbol
Min. Max.
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
Ё
Ё
-0.3 7 V (1), (3)
3000 VRMS
Unit Note
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(single-end)
Terminating Resistor R
CMIS
interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
RUSH
ЁЁ
ЁЁ
ЁЁ
V
LVTH
V
LVTL
|V
| 200
ID
T
0
IL
ЁЁ
0.38
0.58 0.62 A
0.3
+100
ЁЁ
ЁЁ
Ё
Ё
100
Ё
Ё
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
2.8 A (2)
Ё
A
(3)
Ё
A
mV
-100 mV
(4)
600 mV
Ё
ohm
3.3 V
0.7 V
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GND
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60 Hz,
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PRODUCT SPECIFICATION
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
whereas a power dissipation check pattern below is displayed.
a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
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Note (4) The LVDS input characteristics are as follows :
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PRODUCT SPECIFICATION
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Unit Note
Min. Typ. Max.
Lamp Input Voltage VW - 1560 - V
Lamp Current IL 11.8 12.3 12.8 mA
- - 2710 V
Lamp Turn On Voltage V
S
- - 2260 V
I
RMS
RMS
(1) , Ta = 0 ºC
RMS
(1) , Ta = 25 ºC
RMS
L
Operating Frequency FO 30 - 80 KHz (2)
Lamp Life Time LBL 50,000 - - Hrs (3)
3.2.2 ELECTRICAL SPECIFICATION
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Unit Note
Min. Typ. Max.
=12.3mA
Total Power Consumption P
255
- 74 78 W (5), (6), IL =12.3mA
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - 3.08 3.25 A Non Dimming
Inrush current I
R
- - 4.8 A
VBL=24V,(IL=typ)
peak
(7)
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Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 55 58 61 kHz (3)
Dimming Frequency FB 150 160 170 Hz
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PRODUCT SPECIFICATION
Minimum Duty Ratio D
Note (1) Lamp current is measured by utilizing AC current probe.
Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second after startup.
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference,
the lamp frequency should be detached from the horizontal synchronous frequency and its
harmonics as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value
and the effective discharge length is longer than 80% of its original length (Effective discharge
length is defined as an area that has equal to or more than 70% brightness compared to the
brightness at the center point of lamp.) as the time in which it continues to operate under the
condition at Ta = 25 ±2к and I
Note (5) The power supply capacity should be higher than the total inverter power consumption P
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
10 20 - % (8)
MIN
= 11.8~12.8mArms.
L
. Since
BL
for the changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 31.5" backlight unit under input voltage 24V,
average lamp current 12.6 mA and lighting 30 minutes later.
Note (7) The duration of Input Inrush Current is about VBL Rising Time 30ms.
Note (8) 10% minimum duty ratio is only valid for electrical operation.
HV (Pink)
HV (White)
HV (Pink)
HV (White)
LCD Module
HV (Pink)
HV (White)
HV (Pink)
HV (White)
1
A
2
A
1
A
2
A
Inverter
1
A
2
A
1
A
2
A
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y
r
A
3.2.3 INVERTER INTERFACE CHARACTERISTICS
Parameter Symbol
On/Off Control Voltage
Voltage
Voltage
Error Signal ERR
Error Turn on Delay Time T
Error Turn off Delay Time T
VBL Rising Time Tr1 Ё 30 ЁЁ ms
VBL Falling Time Tf1 Ё 30 ЁЁ ms
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time T
PWM Signal Falling Time T
Input impedance R
PWM Turn on Delay Time T
PWM Turn off Delay Time T
BLON Turn on Delay Time T
BLON Turn off Time T
BLON Delay Time T
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
ON
OFF
MAX2.853.0 3.15V Maximum duty ratioInternal PWM Control
MIN
HI 2.4
LO
V
BLON
V
IPWM
V
EPWM
ER-R
ER-F
PWMR
PWMF
IN
PWMON
PWMOFF
on
off
on1
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PRODUCT SPECIFICATION
2.4
0
Ё
0
Open Collecto
0
1
Value
Ё
Ё
0
Ё
Ё
Ё
5.0 V
0.8 V
Ё
5.0 V Duty on External PWM Control
0.8VDut
0.8VNormal
100 ms
100 ms
50 us
50 us
ЁЁ
UnitNote
V Minimum duty ratio
off
bnormal
10%-90%V
M˖
Tes t
Condition
Min.Typ.Max.
Ё
Ё
Ё
Ё
Ё
ЁЁЁ 200 ms
ЁЁЁ 200 ms
ЁЁЁ
ЁЁЁ
ЁЁЁ
ЁЁЁ
Ё
Ё 500 Ё ms
Ё 1 Ё ms
Ё 200 ЁЁ ms
Ё 200 ЁЁ ms
Ё 300 ЁЁ ms
BL
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
Ш
PWM signal Ш BLON
Ш
PWM signal Ш VBL
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T
Err
Open Collector
0
ER-R
0.8V
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PRODUCT SPECIFICATION
T
ER-F
V
V
V
BL
V
BLON
EPWM
IPWM
Tf
OFF
Tf1
T
Ton1
PWMOFF
T
PWMF
Floating
Tr1
0.9V
Ton
0
2.4V
0
0
0.8V
2.4V
0.8V
3V
Backlight on duration
Tr
Ext. Dimming Function
T
PWMR
PWMON
T
0.1V
BL
BL
T
Int. Dimming
0
Floating
Function
V
W
External
PWM
Period
External
PWM Duty
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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PRODUCT SPECIFICATION
SCAN DRIVER IC
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
SELLVDS
ODSEL
Vcc
GND
VBL
GND
ERR
BLON
I_PWM
FI-RE51S-HF (JAE) or Equivalent
INPUT CONNECTOR
INVERTER
CONNECTOR
CN1: Cvilux
CI0114M1HRL-NH or
Equivalent
TFT LCD PANEL
(1920x3x1080)
TIMING
CONTROLLER
DATA DRIVER IC
DC/DC CONVERTER &
REFERENCE VOLTAGE
BACKLIGHT
UNIT
E_PWM
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment
Pin Name Description Note
1
VCC +12V power supply
2
VCC +12V power supply
3
VCC +12V power supply
4
VCC +12V power supply
5
VCC +12V power supply
6
N.C. No Connection
7
GND Ground
8
GND Ground
9
GND Ground
10
ORX0-
11
ORX0+
12
ORX1-
13
ORX1+
14
ORX2-
15
ORX2+
16
GND Ground
17
OCLK-
18
OCLK+
19
GND Ground
20
ORX3-
21
ORX3+
22
N.C. No Connection
23
N.C. No Connection
24
GND Ground
25
ERX0-
26
ERX0+
27
ERX1-
28
ERX1+
29
ERX2-
30
ERX2+
31
GND Ground
32
ECLK-
33
ECLK+
34
GND Ground
35
ERX3-
36
ERX3+
37
N.C. No Connection
38
N.C. No Connection
39
GND Ground
40
SCL
41
SDA
42
N.C. No Connection
43
WP
Odd pixel Negative LVDS differential data input. Channel 0
Odd pixel Positive LVDS differential data input. Channel 0
Odd pixel Negative LVDS differential data input. Channel 1
Odd pixel Positive LVDS differential data input. Channel 1
Odd pixel Negative LVDS differential data input. Channel 2
Odd pixel Positive LVDS differential data input. Channel 2
Odd pixel Negative LVDS differential data input. Channel 3
Odd pixel Positive LVDS differential data input. Channel 3
Even pixel Negative LVDS differential data input. Channel 0
Even pixel Positive LVDS differential data input. Channel 0
Even pixel Negative LVDS differential data input. Channel 1
Even pixel Positive LVDS differential data input. Channel 1
Even pixel Negative LVDS differential data input. Channel 2
Even pixel Positive LVDS differential data input. Channel 2
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
Even pixel Negative LVDS differential data input. Channel 3
Even pixel Positive LVDS differential data input. Channel 3
EEPROM Serial Clock (for auto Vcom)
EEPROM Serial Data (for auto Vcom)
EEPROM Write Protection (for auto Vcom)
(0V~0.7VШDisable, 2.7V~3.3VШEnable)
44 PANEL_SEL
45
SELLVDS
No Connection
LVDS data format selection (2.7V~3.3VШVESA, 0V~0.7VШ
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PRODUCT SPECIFICATION
(2)
(7)
(7)
(7)
(2)
(7)
(7)
(7)
(2)
(2)
(2)
(3)(5)
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JEIDA).
46
OD_SEL
47
N.C. No Connection
48
N.C. No Connection
49
N.C. No Connection
50
TCON_RDY
51
N.C. No Connection
Note (1) LVDS connector pin order defined as follows
Overdriving lookup table selection
T-CON ready signal
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PRODUCT SPECIFICATION
(4)(6)
(2)
(2)
Note (2) Reserved for internal use. Please leave it open.
Note (3) Low = Connect to GND: JEIDA Format, High = Connect to +3.3V: VESA Format.
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
Low = Open or connect to GND, High = Connect to +3.3V
ODSEL Note
L or open Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 60 Hz frame rate.
Note (5) LVDS signal pin connected to the LCM side has the following diagram. R1 in the system side should be
less than 1K Ohm. (R1 < 1K Ohm)
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Note (6) ODSEL signal pin connected to the LCM side has the following diagram. R1 in the system side should
be less than 1K Ohm. (R1 < 1K Ohm)
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PRODUCT SPECIFICATION
Note (7) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel
5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN: E01B-KCF, manufactured by JST or Equivalent
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5.3 INVERTER UNIT
CN1: CI0114M1HRL-NH (CviLux)
Pin № Symbol Feature
1
2
3
4
5
6
7
8
9
10
11 ERR
12 BLON BL ON/OFF
13 I_PWM Internal PWM Control
14 E_PWM External PWM Control
GND GND
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PRODUCT SPECIFICATION
VBL +24V
Normal (GND)
Abnormal(Open collector)
Note (1) PIN 13:Intermal PWM Control (Use Pin 13): Pin 14 must open.
Note (2) PIN 14:External PWM Control (Use Pin 14): Pin 13 must open.
Note (3) Pin 13(I_PWM) and Pin 14(E_PWM) can’t open in same period.
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5.4 BLOCK DIAGRAM OF INTERFACE
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PRODUCT SPECIFICATION
ER0~ER7: Even pixel R data
EG0~EG7: Even pixel G data
EB0~EB7: Even pixel B data
OR0~OR7: Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7: Odd pixel B data
DE: Data enable signal
DCLK: Data clock signal
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PRODUCT SPECIFICATION
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel.
5.5 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=H)
Current F\FOH
Current F\FOH
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
JEDIA LVDS formatΚ(SELLVDS pin=L)
RXCLK
RXCLK
ORX0
ORX0
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
Current F\FOH
Current F\FOH
R7G2R6R5R4R3
R7G2R6R5R4R3
G3G2G4
G3G2G4
G3G2G4
G3G2G4
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R2
R2
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
B2G7B3
B2G7B3
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
G5G4G6
G5G4G6
G5G4G6
G5G4G6
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
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R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color