Please return 1 copy for your confirmation with your
signature and comments.
Approved By Checked By Prepared By
Chao-Chun Chung Vincent Chou
Perry Lin
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RODUCT SPECIFICATION
CONTENTS
1. GENERAL DESCRIPTION .................................................................................................................................................. 5
1.2 FEATURES .....................................................................................................................................................5
2. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................... 7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT...................................................................................................7
5.3 INVERTER UNIT ..........................................................................................................................................19
5.4 BLOCK DIAGRAM OF INTERFACE.............................................................................................................20
7.1 TEST CONDITIONS......................................................................................................................................27
9. DEFINITION OF LABELS.................................................................................................................................................. 33
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Version Date Page(New) Section Description
Ver. 2.0 July. 26, 2010 All All The approval specification was first issued.!
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RODUCT SPECIFICATION
REVISION HISTORY
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V315H1-L04 is a TFT Liquid Crystal Display module with 4U type CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 HDTV format and can display 16.7M colors (8-bit/color). The inverter module
for backlight is built-in.
1.2 FEATURES
Ё High brightness (450 nits)
Ё High contrast ratio (4000:1)
Ё Fast response time (Gray to gray average 6.5 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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Ё LVDS (Low Voltage Differential Signaling) interface
Ё Ultra wide viewing angle : Super MVA technology
Ё Low color shift function
1.3 APPLICATION
Ё Standard Living Room TVs
Ё Optimized Brightness, Multi-Media Displays
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 698.4(H) x 392.85(V) mm
Bezel Opening Area 705.4(H) x 399.8 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
Pixel Pitch(Sub Pixel) 0.12125 (H) x 0.36375 (V) mm -
Pixel Arrangement RGB vertical stripe - -
(1)
Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMI reserves the rights to change this feature.
Anti-Glare coating (Haze 11%), Hard Coating
(3H)
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
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RODUCT SPECIFICATION
Horizontal (H)
Vertical (V) 449.0 450.0 451.0 mm
Module Size
Weight - 5280 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth does not include connectors.
Depth (D) 31.5 32.5 33.5 mm To rear
Depth (D) 42.6 43.6 44.6 mm To ctrl cover
Depth (D) 46.9 47.9 48.9 mm To inverter cover
759.0 760.0 761.0 mm Module Size
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
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RODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so
that the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended
to store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
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RODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(1)
2.3.2 BACKLIGHT INVERTER UNIT
Value
Item Symbol
Min. Max.
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) The control signals include On/Off Control and External PWM Control.
Ё
Ё
-0.3 7 V (1), (3)
3000 VRMS
Unit Note
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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RODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(single-end)
Terminating Resistor R
CMIS
interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
RUSH
Ё Ё
Ё Ё
Ё Ё
V
LVTH
V
LVTL
|
|V
ID
T
0
IL
+100
ЁЁ
0.69
0.84 0.91 A
0.39
ЁЁ
200
Ё
100
Ё Ё
Ё
Ё
Ё
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
2.1 A (2)
Ё
A
(3)
Ё
A
mV
-100 mV
(4)
600 mV
Ё
ohm
3.3 V
0.7 V
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RODUCT SPECIFICATION
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
GND
Vcc rising time is 470us
0.9Vcc
0.1Vcc
470us
Vcc
= 60 Hz,
v
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RODUCT SPECIFICATION
c. Horizontal Pattern
a. White Pattern
Active Area
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows :
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
RODUCT SPECIFICATION
Value
Unit Note
Lamp Input Voltage VL - 1470 - V
Lamp Current IL 11.8 12.3 12.8 mA
- - 2570 V
Lamp Turn On Voltage VS
- - 2290 V
Operating Frequency FL 30 - 80 KHz
Lamp Life Time LBL 50,000 - - Hrs
3.2.2 ELECTRICAL SPECIFICATION
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
Power Consumption PBL - 74 78 W (5),(6) IL = 12.3 mA
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - 3.08 3.25 A Non Dimming
Unit
IL = 12.3mA
RMS
RMS
Ta = 0 ºC
RMS
Ta = 25 ºC
RMS
Note
Input Inrush Current
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 60 63 66 kHz (3)
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio D
Note (1) Lamp current is measured by utilizing AC current probe and its value is average.
Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second after startup.
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and the
effective discharge length is longer than 80% of its original length (Effective discharge length is defined
as an area that has equal to or more than 70% brightness compared to the brightness at the center point
- - - 4.79 Apeak
10 20 - %
MIN
VBL=24V,(IL=typ) (7)
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Value
ON
Ё
3.3
Ё
5.3 V
Voltage
OFF
0 Ё
0.8 V
HI 3.0
Ё
5.3 V Duty on
Voltage
LO
0 Ё 0.8 V Duty off
0 Ё 0.8 V Normal
4.5 Ё 5.5 V Abnormal
2 1
1 2
A
A A
of lamp.) as the time in which it continues to operate under the condition at Ta = 25 ±2 and IL = 11.8~ к
12.8mArms.
Note (5) The power supply capacity should be higher than the total inverter power consumption PBL. Since the
pulse width modulation (PWM) mode was applied for backlight dimming, the driving current changed
as PWM duty on and off. The transient response of power supply should be considered for the
changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 31.5" backlight unit under input voltage 24V,
average lamp current 12.6 mA and lighting 30 minutes later.
Note (7) The duration of Input Inrush Current is about VBL Rising Time 30ms.
Note (8) 10% minimum duty ratio is only valid for electrical operation.
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RODUCT SPECIFICATION
1
3.2.3 INVERTER INTERFACE CHARACTERISTICS
Parameter Symbol
On/Off Control
External PWM Control
LCD
Module
VBLON
VEPWM
A
A
A
A
A
Test
Condition
Ё
Ё
2
1
2
Min. Typ. Max.
Inverter
Unit Note
DET_5V DET_5V
Input impedance RIN Ё 1 Ё Ё MӨ
VBL Rising Time T1 Ё 20 Ё Ё ms 10%-90%VBL
VDIM Turn On Time T2
VBLON Turn On Time T3
VBLON Turn Off Time T4
VDIM Turn Off Time T5
Ё
Ё
Ё
Ё
Ё
500
250
0
1
Ё Ё
Ё Ё ms
Ё Ё ms
Ё Ё ms
ms
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Note (1) The Dimming signal should be valid before backlight turns on by BLON signal.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
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RODUCT SPECIFICATION
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
→
PWM signal → BLON
→
PWM signal → VBL
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SCAN DRIVER IC
INPUT CONNECTOR
or equal
GND
FRAME BUFFER
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+
SELLVDS
ODSEL
(JAE, FI-RE51S-HF)
Vcc
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RODUCT SPECIFICATION
TIMING
CONTROLLER
DC/DC CONVERTER &
REFERENCE VOLTAGE
TFT LCD PANEL
(1920x3x1080)
DATA DRIVER Mini-LVDS
DET_5V
VBL
GND
BLON
NC
E_PWM
CN1
INVERTER CONNECTOR
CN1: 20022WR14 (Yeon-Ho )
BACKLIGHT
UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (3)(5)
8 N.C. No Connection (2)
9 ODSEL Overdrive Lookup Table Selection (4)(6)
10 N.C. No Connection (2)
11 GND Ground
12 ERX0- Even pixel Negative LVDS differential data input. Channel 0
13 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
14 ERX1- Even pixel Negative LVDS differential data input. Channel 1
15 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
16 ERX2- Even pixel Negative LVDS differential data input. Channel 2
17 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 ECLK- Even pixel Negative LVDS differential clock input.
20 ECLK+ Even pixel Positive LVDS differential clock input.
21 GND Ground
22 ERX3- Even pixel Negative LVDS differential data input. Channel 3
23 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
24 N.C. No Connection
25 N.C. No Connection
26 GND Ground
27 GND Ground
28 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
29 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
30 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
31 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
32 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
33 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK- Odd pixel Negative LVDS differential clock input
36 OCLK+ Odd pixel Positive LVDS differential clock input
37 GND Ground
38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
39 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
40 N.C. No Connection
41 N.C. No Connection
42 GND Ground
43 GND Ground
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (2)
48 VCC Power input (+12V)
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RODUCT SPECIFICATION
(2)
(7)
(7)
(7)
(2)
(7)
(7)
(7)
(2)
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H Lookup table was optimized for 50 Hz frame rate.
R1
R1
49 VCC Power input (+12V)
50 VCC Power input (+12V)
51 VCC Power input (+12V)
Note (1) LVDS connector pin order defined as follows
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RODUCT SPECIFICATION
Note (2) Reserved for internal use. Please leave it open.
Note (3) Low = Open or connect to GND: VESA Format, High = Connect to +3.3V: JEIDA Format.
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
Low = Open or connect to GND, High = Connect to +3.3V
ODSEL Note
L or open Lookup table was optimized for 60 Hz frame rate.
Note (5) LVDS signal pin connected to the LCM side has the following diagram. R1 in the system side should be
less than 1K Ohm. (R1 < 1K Ohm)
TCON
TCON
R2
R2
Selector (pin7)
Setting
Setting
R3
R3
System side
System side
Note (6) ODSEL signal pin connected to the LCM side has the following diagram. R1 in the system side should
be less than 1K Ohm. (R1 < 1K Ohm)
LCM side
LCM side
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Selector (pin9)
Selector (pin9)
System side
System side
Note (7) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel
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RODUCT SPECIFICATION
R2R1
R2R1
R3
R3
Setting
Setting
TCON
TCON
LCM side
LCM side
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN: E01B-KCF, manufactured by JST or Equivalent
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RODUCT SPECIFICATION
5.3 INVERTER UNIT
CN1(Header): 20022WR14 (Yeon-Ho )
Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
11 DET_5V Check Lamp Ignition.
12 BLU_ON BL ON/OFF
13 N.C. No connect.
14 E_PWM External PWM Control
VBL +24V Power input
GND Ground
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ER0
-
ER7
ER0
-
ER7
Controller
ERx0+
ERx1+
ECLK+
RxOUT
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100pF
ERx3
-
ORx0+
ORx1+
OCLK+
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100Ө
100pF
ORx3
-
OR0
-OR7 OR0
-
OR7
5.4 BLOCK DIAGRAM OF INTERFACE
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RODUCT SPECIFICATION
TxIN
Host
Graphics
Controller
CNF1
ERx1-
ERx2+
ERx3+
100pF
100Ө
100pF
100pF
100pF
Timing
100pF
100Ө
ORx1-
ORx2+
100pF
ORx3+
100pF
100pF
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
LVDS Receiver
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ER0~ER7: Even pixel R data
EG0~EG7: Even pixel G data
EB0~EB7: Even pixel B data
OR0~OR7: Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7: Odd pixel B data
DE: Data enable signal
DCLK: Data clock signal
1
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
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RODUCT SPECIFICATION
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA LVDS formatΚ(SELLVDS pin=L or open)
RXCLK
RXCLK
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RODUCT SPECIFICATION
Current F\FOH
Current F\FOH
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
JEDIA LVDS formatΚ(SELLVDS pin=H)
RXCLK
RXCLK
ORX0
ORX0
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
R5G0R4R3R2R1
R5G0R4R3R2R1
B0G5B1
B0G5B1
Current F\FOH
Current F\FOH
R7G2R6R5R4R3
R7G2R6R5R4R3
G3G2G4
G3G2G4
G3G2G4
G3G2G4
R2
R2
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
R0
R0
G1
G1
B2B4B3B5VSHSDE
B2B4B3B5VSHSDE
R6G6R7G7B7B6RSVD
R6G6R7G7B7B6RSVD
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
B2G7B3
B2G7B3
R7G2R6R5R4R3
R7G2R6R5R4R3
B2G7B3
B2G7B3
G5G4G6
G5G4G6
G5G4G6
G5G4G6
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R2
R2
G3
G3
B4B6B5B7VSHSDE
B4B6B5B7VSHSDE
R0G0R1G1B1B0RSVD
R0G0R1G1B1B0RSVD
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
Version 2.0 22 DateΚΚ26 July 2010
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1 0 0
1 1
1 0 0
1 1
1 0 0
1 1
1 0 0
1 1
1 0 0
1 1
1 0 0
1 1
1 0 0
1 1
1 0 0
1 1
0 1 0
0 1
0 1 0
0 1
0 1 0
0 1
0 1 0
0 1
0 1 0
0 1
0 1 0
0 1
0 1 0
0 1
0 1 0
0 1
0 0 1
1 0
0 0 1
1 0
0 0 1
1 0
0 0 1
1 0
0 0 1
1 0
0 0 1
1 0
0 0 1
1 0
0 0 1
1 0
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
0 1
1
1 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
1 1
0 :
1 1
0 :
1 1
0 :
1 1
0 :
1 1
0 :
1 1
1 :
0 1
0 :
1 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 :
0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
0 0 0
0 0 :
1 1 1
0 0 :
1 1 1
0 0 :
1 1 1
0 0 :
1 1 1
0 0 :
1 1 1
0 0 :
1 1 1
0 1 :
0 1 1
1 0 :
1 0 1
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of