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REVISION HISTORY
Version Date Page Description
0.0 Sep.10, 2010 All Spec Ver.0.0 was first issued.
1.0 Feb.14, 2011 All Spec Ver.1.0 was first issued.
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PRODUCT SPECIFICATION
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
N173HHF-E21 is a 17.3” TFT Liquid Crystal Display module with LED Backlight unit and 40 pins
display port interface. This module supports 1920 x 1080 FHD mode and can display 262,144
colors. The optimum viewing angle is at 6 o’clock direction.
1.2 GENERAL SPECIFICATI0NS
Item Specification Unit Note
Screen Size 17.3” diagonal
Driver Element a-si TFT active matrix - Pixel Number 1920 x R.G.B. x 1080 pixel Pixel Pitch 0.1989 (H) x 0.1989 (V) mm Pixel Arrangement RGB vertical stripe - Display Colors 262,144 color Transmissive Mode Normally white - Surface Treatment Hard coating (3H), Anti-Glare - Luminance, White 400 Cd/m2
Power Consumption Total 11.2W (Max.) @ cell 2.2W (Max.), BL 9W (Max.) (1)
Note (1) The specified power consumption (with converter efficiency) is under the conditions at VCCS =
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Vertical (V) 232.3 232.8 233.3 mm
Thickness (T) - 5.7 6.0 mm
Horizontal 385.88 386.18 386.48 mm
Vertical 218.55 218.85 219.15 mm
Horizontal - 381.888 - mm
Vertical - 214.812 - mm
Weight - 578 600 g
2.1 CONNECTOR TYPE
Pin1Pin40
(1)
Please refer Appendix Outline Drawing for detail design.
Connector Part No.: Starconn 111A40-0000RA-G3, Tyco# 5-2069716-3, or equivalent
User’s connector Part No: Starconn 111B40-0000RA-G3, Tyco#5-2069715-3, or equivalent
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3. ABSOLUTE MAXIMUM RATINGS
3.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 +50 ºC (1), (2)
Note (1) (a) 90 %RH Max. (Ta <= 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel surface should be 0 ºC min. and 60 ºC max.
Relative Humidity (%RH)
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PRODUCT SPECIFICATION
Value
Min. Max.
Unit Note
100
90
80
60
Operating
40
20
10
Storage Range
Temperature (ºC)
3.2 ELECTRICAL ABSOLUTE RATINGS
3.2.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCCS -0.3 +6.0 V
Logic Input Voltage VIN -0.3 VCCS+0.3 V
Converter Input Voltage
Converter Control Signal Voltage
Converter Control Signal Voltage
LED_VCCS
LED_PWM,
LED_EN
Value
Min. Max.
-0.3 25 V (1)
-0.3 6 V (1)
-0.3 6 V (1)
Unit Note
8060-20 40 0 20 -40
(1)
Note (1) Stresses beyond those listed in above “ELECTRICAL ABSOLUTE RATINGS” may cause
permanent damage to the device. Normal operation should be restricted to the conditions
described in “ELECTRICAL CHARACTERISTICS”.
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4. ELECTRICAL SPECIFICATIONS
4.1 FUNCTION BLOCK DIAGRAM
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PRODUCT SPECIFICATION
Display port
Signals
VCCS
GND
Converter
Input Signals
INPUT CONNECTOR
DP INPUT /
TIMING CONTROLLER
EDID
EEPROM
DC/DC CONVERTER &
REFERENCE VOLTAGE
GENERATOR
LED
CONVERTER
SCAN DRIVER IC
TFT LCD PANEL
DATA DRIVER IC
BACKLIGHT UNIT
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4.2. INTERFACE CONNECTIONS
PIN ASSIGNMENT
Pin Symbol Description Remark
1 NC No Connection (Reserved)
2 H_GND High Speed Ground
3 ML3- Complement Signal-Lane 3
4 ML3+ True Signal-Main Lane 3
5 H_GND High Speed Ground
6 ML2- Complement Signal-Lane 2
7 ML2+ True Signal-Main Lane 2
8 H_GND High Speed Ground
9 ML1- Complement Signal-Lane 1
10 ML1+ True Signal-Main Lane 1
11 H_GND High Speed Ground
12 ML0- Complement Signal-Lane 0
13 ML0+ True Signal-Main Lane 0
14 H_GND High Speed Ground
15 AUX+ True Signal-Auxiliary Channel
16 AUX- Complement Signal-Auxiliary Channel
17 H_GND High Speed Ground
18 VCCS Power Supply +5 V (typical)
19 VCCS Power Supply +5 V (typical)
20 VCCS Power Supply +5 V (typical)
21 VCCS Power Supply +5 V (typical)
22 BIST Built-In Self Test (active high)
23 GND Ground
24 GND Ground
25 GND Ground
26 GND Ground
27 HPD Hot Plug Detect
28 BL_GND BL Ground
29 BL_GND BL Ground
30 BL_GND BL Ground
31 BL_GND BL Ground
32 LED_EN BL_Enable Signal of LED Converter
33 LED_PWM PWM Dimming Control Signal of LED Converter
34 NC No Connection (CMO Reserved)
35 NC No Connection (CMO Reserved)
36 LED_VCCS BL Power
37 LED_VCCS BL Power
38 LED_VCCS BL Power
39 LED_VCCS BL Power
40 NC No Connection (Reserved)
Note (1) The first pixel is odd as shown in the following figure.
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PRODUCT SPECIFICATION
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PRODUCT SPECIFICATION
1,1
(odd)
2,1
3,1
1,2
(even)
2,2
1,3
(odd)
1,4
(even)
1,Xmax
Pitch
Pitch
Ymax,1
Ymax,
Xmax
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4.3 ELECTRICAL CHARACTERISTICS
4.3.1 LCD ELETRONICS SPECIFICATION
Parameter Symbol
Power Supply Voltage VCCS 4.5 5.0 5.5 V (1)-
Ripple Voltage VRP - 50 - mV (1)-
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Inrush Current I
- - 1.5 A (1),(2)
RUSH
Mosaic - 387 437 mA (3)a
Power Supply Current
Black
lcc
- 441 491 mA (3)b
Note (1) The ambient temperature is Ta = 25 ± 2 ºC.
Note (2) I
: the maximum current when VCCS is rising
RUSH
I
: the maximum current of the first 100ms after power-on
IS
Measurement Conditions: Shown as the following figure. Test pattern: black..
(High to Low)
(Control Signal)
SW
+12V
+3.3V
R1
47K
R2
1K
47K
VR1
C1
1uF
Q1 2SK1475
C2
0.01uF
Q2
2SK1470
FUSE
C3
1uF
VCCS
(LCD Module Input)
VCCS rising time is 0.5ms
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Note (3) The specified power supply current is under the conditions at VCCS = 5 V, Ta = 25 ± 2 ºC, DC
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PRODUCT SPECIFICATION
Current and f
a. Mosaic Pattern
= 60 Hz, whereas a power dissipation check pattern below is displayed.
v
Active Area
b. Black Pattern
Active Area
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4.3.2 LED CONVERTER SPECIFICATION
Parameter Symbol
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Converter Input power supply voltage
Converter Inrush Current
LED_Vccs
ILED
RUSH
7.5 12.0 21.0 V
- - 1.5 A (1)
Backlight On 2.3 - 5.0 V
EN Control Level
Backlight Off 0 - 0.5 V
PWM High Level 2.3 - 5.0 V
PWM Control Level
PWM Low Level 0 - 0.5 V
10 - 100 %
PWM Control Duty Ratio
5 - 100 % (2)
PWM Control Permissive Ripple
Voltage
PWM Control Frequency f
VPWM_pp
190 - 2K Hz (3)
PWM
- - 100 mV
LED Power Current LED_VCCS =Typ. ILED 534 635 753 mA (4)
Note (1) ILED
ILED
: the maximum current when LED_VCCS is rising,
RUSH
: the maximum current of the first 100ms after power-on,
IS
Measurement Conditions: Shown as the following figure. LED_VCCS = Typ, Ta = 25 ± 2 ºC, f
= 200 Hz, Duty=100%.
PWM
(High to Low)
(Control Signal)
SW=24V
LED_VCCS(Typ)
LED_VCCS(Typ)
C1
1uF
VR1
R1
47K
R2
1K
47K
Q1 IRL3303
0.01uF
FUSE
Q2
IRL3303
C2
C3
1uF
(LED Converter Input)
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PRODUCT SPECIFICATION
VLED rising time is 0.5ms
0.5ms
90%
ILED
10%
Rush
100ms
ILED
IS
LED_VCC
LED_PWM
LED_EN
ILED
Note (2) If the PWM control duty ratio is less than 10%, there is some possibility that acoustic noise or
backlight flash can be found. And it is also difficult to control the brightness linearity.
Note (3) If PWM control frequency is applied in the range less than 1KHz, the “waterfall” phenomenon on
0V
0V
0V
the screen may be found. To avoid the issue, it’s a suggestion that PWM control frequency should
follow the criterion as below.
PWM control frequency f
dfN)33.0( f
should be in the range
PWM
PWM
fNd)66.0(
N : Integer )3(tN
f
: Frame rate
Note (4) The specified LED power supply current is under the conditions at “LED_VCCS = Typ.”, Ta = 25
± 2 ºC, f
= 200 Hz, Duty=100%.
PWM
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4.3.3 BACKLIGHT UNIT
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PRODUCT SPECIFICATION
Parameter Symbol
LED Light Bar Power
Supply Voltage
LED Light Bar Power
Supply Current
Power Consumption PL 5.38 6.47 7.22 W (3)
LED Life Time LBL 15000 - - Hrs (4)
Note (1) LED current is measured by utilizing a high frequency current meter as shown below :
Light Bar Feedback
Channels
L 30.8 35.2 37.4 V
V
L 174.8 184 193.2 mA
I
Min. Typ. Max.
VL,I
L
Ta = 25 ± 2 ºC
Value
LED
Light Bar
Unit Note
(1)(2)(Duty100%)
Note (2) For better LED light bar driving quality, it is recommended to utilize the adaptive boost converter
with current balancing function to drive LED light-bar.
Note (3) P
Note (4) The lifetime of LED is defined as the time when it continues to operate under the conditions at Ta =
25 ±2
= IL ×VL (Without LED converter transfer efficiency)
L
o
C and IL = 23 mA(Per EA) until the brightness becomes 50% of its original value.Љ
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|
|
|
|
4.4 DISPLAY PORT INPUT SIGNAL TIMING SPECIFICATIONS
4.4.1 ELECTRICAL SPECIFICATIONS
Parameter Symbol Min. Typ. Max. Unit Notes
MainLink Input Signal Peak-to
-peak Voltage
AUX Differential Input Voltage |VID|
Differential Signal Common Mode
Voltage
AUX AC Coupling Capacitor C
Lane Intra-pair Skew VRX-SKEW-INTRA_PAIR
Note (1) Display port interface related AC coupled signals are following VESA Display Port Standard
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PRODUCT SPECIFICATION
120 - - mV
|VDIFF
P-P|(MainLink)
40 - - mV
160 - 680 mV
(AUX)
VCM 0 2 V
75 200 nF
AUX
- - 100
ps
- - 300
High bit
Reduced
bit rate
High bit
Reduced
bit rate
rate
rate
V1.1a
Single Ended
Differential
V
V
V
0V
0V
D+
CM
D-
VID
VDIFF
P-P
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4.5 DISPLAY TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item SymbolMin. Typ. Max. Unit Note
DCLK Frequency 1/Tc TBD 138.5TBD MHz -
Vertical Total Time TV TBD 1110TBD TH -
Vertical Active Display Period TVD 108010801080 TH -
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PRODUCT SPECIFICATION
DE
Note (1) Display timing signal should be contained and transferred by Display Port Main Link stream
data packing described in VESA Display Port Standard V1.1a
Vertical Active Blanking Period TVB TV-TVD30 TV-TVD TH -
Horizontal Total Time TH TBD 2080TBD Tc -
Horizontal Active Display Period THD 192019201920 Tc -
Horizontal Active Blanking Period THB
TH-THD
160
TH-THD
Tc -
DISPLAY SIGNAL TIMING DIAGRAM
T
v
TVD
DE
TH
DCLK
TC
DE
DATA
HD
T
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4.6 POWER ON/OFF SEQUENCE
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PRODUCT SPECIFICATION
-Power Supply
for LCD, VCCS
-eDP Display
-HPD from Sink
-AUX Channel
-Main Link Data
0V
0V
Power On
90%
10%
t1
10%
Restart
10%
t12
Power Off
t11
90%
t2
Black Video
t3
AUX Channel Operational
t4
Link
Training
Idle
Video from Source
Valid Video Data
t10
Black Video
Idle or off
- Power Supply for
LED Converter,
LED_VCCS
- LED Converter
Dimming Signal,
LED_PWM
- LED Converter
Enable Signal,
LED_EN
0V
0V
0V
t5t6t7t8t9
90%
10%
t
A
t
C
t
E
90%
10%
t
B
t
D
t
F
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Timing Specifications: Follow VESA Embedded Display Port Standard Version 1
Parameter Description
t1 Power rail rise time, 10% to 90% Source 0.5 10 ms -
t2
t3
t4
t5 Link training duration Source - - mst6 Link idle Source - - ms-
t7
t8
t9
t10
t11
t12 VCCS Power off time Source 500 - ms-
t
A
t
B
t
C
t
D
t
E
t
F
Note (1) Please follow the power on/off sequence described above. Otherwise, the LCD module might
Delay from LCD,VCCS to black
video generation
Delay from LCD,VCCS to HPD
high
Delay from HPD high to link
training initialization
Delay from valid video data from
Source to video on display
Delay from valid video data from
Source to backlight on
Delay from backlight off to end of
valid video data
Delay from end of valid video data
from Source to power off
VCCS power rail fall time, 90% to
10%
LED power rail rise time, 10% to
90%
LED power rail fall time, 90% to
10%
Delay from LED power rising to
LED dimming signal
Delay from LED dimming signal to
LED power falling
Delay from LED dimming signal to
LED enable signal
Delay from LED enable signal to
LED dimming signal
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PRODUCT SPECIFICATION
Reqd.
By
Sink 0 200 ms -
Sink 0 200 ms -
Source - - ms-
Sink 0 50 ms-
Source - - ms-
Source - - ms-
Source 0 500 ms-
Source 0.5 10 ms-
Source 0.5 10 ms-
Source 0 10 ms-
Source 10 - ms-
Source 10 - ms-
Source 10 - ms -
Source 10 - ms -
Value
Min Max
Unit Notes
abnormal display or be damaged.
Note (2) Please avoid floating state of interface signal at invalid period. When the interface signal is invalid, be
sure to pull down the power supply of LCD VCCS to 0 V.
Note (3) The backlight must be turned on after the power supply for the logic and the interface signal is valid.
The backlight must be turned off before the power supply for the logic and the interface signal is
invalid.
Note (4) Please follow the LED backlight power sequence as above. If the customer could not follow, it might
cause backlight flash issue during display ON/OFF or damage the LED backlight controller
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5. OPTICAL CHARACTERISTICS
5.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 3.3 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
LED Light Bar Input Current IL 184 mA
The measurement methods of optical characteristics are shown in Section 5.2. The following items
should be measured under the test conditions described in Section 5.1 and stable environment shown in
Note (5).
5.2 OPTICAL SPECIFICATIONS
Item Symbol Condition Min. Typ. Max. UnitNote
Contrast Ratio CR 500 650 - -
Response Time
Average Luminance of White
Red
Color
Chromaticity
Viewing Angle
White Variation of 5 Points
Green
Blue
White
Horizontal
Verti ca l
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PRODUCT SPECIFICATION
o
25r2
50r10
TR - 2 3 ms
T
- 4 7 ms
F
L
AVE
Rx
Ry
Gx
Gy
Bx
By
=0q, TY =0q
T
x
Viewing Normal Angle
340 400 - cd/m
(0.640)
(0.333)
(0.313)
Typ –
0.03
(0.613)
(0.154)
Typ +
0.03
(0.060)
Wx (0.313) Wy
Tx+
T
TY+
T
GW
-
x
-
Y
5p
CRt10
T
=0q, TY =0q
x
(0.329)
60 70
60 70 50 60 50 60 -
80 - - %
C
%RH
-
-
-
-
-
-
-
Deg.
2
(2),
(5) ,(7)
(3) ,(7)
(4),
(6) ,(7)
(1) ,(7)
(1),(5) ,
(7)
(5),(6) ,
(7)
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Note (1) Definition of Viewing Angle (Tx, Ty):
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PRODUCT SPECIFICATION
Normal
Tx = Ty = 0º
Ty-Ty
TX- = 90º
6 o’clock
T
y- = 90º
x-
y-
Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) = L63 / L0
L63: Luminance of gray level 63
L 0: Luminance of gray level 0
CR = CR (1)
CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6).
Note (3) Definition of Response Time (T
R
, TF):
Tx
Tx
12 o’clock direction
y+
T
y+ = 90º
x+
TX+ = 90º
100%
90%
Optical
Response
10%
0%
T
R
Note (4) Definition of Average Luminance of White (L
AVE
):
T
F
Measure the luminance of gray level 63 at 5 points
L
= [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
AVE
L (x) is corresponding to the luminance of the point X at Figure in Note (6)
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(
)
Note (5) Measurement Setup:
The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt
temperature change during measuring. In order to stabilize the luminance, the measurement
should be executed after lighting Backlight for 20 minutes in a windless room.
LCD Module
LCD Panel
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PRODUCT SPECIFICATION
USB2000
or equivalent
Center of the Screen
500 mm
Note (6) Definition of White Variation (GW):
Measure the luminance of gray level 63 at 5 points
GW
= {Minimum [L (1) ~ L (5)] / Maximum [L (1) ~ L (5)]}*100%
5p
˄˃
ˉ
˛˂ˇ
˅
ˊ
ˆ
CS-2000T
Light Shield Room
Ambient Luminance < 2 lux
or equivalent
ˋ
X
ʳ
: Test Point
X=1 to 13
Active area
˄˃
ˌ
ˇˈ
˄˄
˄˃˄˃
˪˂ˇ˪˂ˇ˪˂ˇ˪˂ˇ
˛
˛˂ˇ˛˂ˇ˛˂ˇ
˄
˄˅
˪
˄˃
˄ˆ
Note (7) The listed optical specifications refer to the initial value of manufacture, but the condition of
the specifications after long-term operation will not be warranted.
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PRODUCT SPECIFICATION
42 2A Standard timing ID # 3
43 2B Standard timing ID # 3
44 2C Standard timing ID # 4
45 2D Standard timing ID # 4
46 2E Standard timing ID # 5
47 2F Standard timing ID # 5
48 30 Standard timing ID # 6
49 31 Standard timing ID # 6
50 32 Standard timing ID # 7
51 33 Standard timing ID # 7
52 34 Standard timing ID # 8
53 35 Standard timing ID # 8
Detailed timing description # 1 Pixel clock (“138.66MHz”, According
54 36
55 37 # 1 Pixel clock (hex LSB first)
56 38 # 1 H active (“1920”)
57 39 # 1 H blank (“160”)
58 3A # 1 H active : H blank (“1920 :160”)
59 3B # 1 V active (”1080”)
60 3C # 1 V blank (”31”)
61 3D # 1 V active : V blank (”1080 :31”)
62 3E # 1 H sync offset (”48”)
63 3F # 1 H sync pulse width ("32”)
64 40 # 1 V sync offset : V sync pulse width (”3 : 5”)
65 41
66 42 # 1 H image size (”382 mm”)
67 43 # 1 V image size (”215 mm”)
68 44 # 1 H image size : V image size (”382 : 215”)
69 45 # 1 H boarder (”0”)
70 46 # 1 V boarder (”0”)
71 47
72 48
73 49 # 2 Pixel clock (hex LSB first)
74 4A # 2 H active (“1920”)
75 4B # 2 H blank (“160”)
76 4C # 2 H active : H blank (“1920 :160”)
77 4D # 2 V active (”1080”)
78 4E # 2 V blank (”53”)
79 4F # 2 V active : V blank (”1080 :53”)
80 50 # 2 H sync offset (”48”)
81 51 # 2 H sync pulse width ("32”)
82 52 # 2 V sync offset : V sync pulse width (”3 : 5”)
83 53
84 54 # 2 H image size (”382 mm”)
85 55 # 2 V image size (”215 mm”)
to VESA CVT Rev1.4)
# 1 H sync offset : H sync pulse width : V sync offset : V sync width
(”48: 32 : 3 : 5”)
# 1 Non-interlaced, Normal Display, Digital Separate Sync, V pol
Negatives, H pol Positives
Detailed timing description # 2 Pixel clock (“235.67MHz”, According
to VESA CVT Rev1.4)
# 2 H sync offset : H sync pulse width : V sync offset : V sync width
(”48: 32 : 3 : 5”)
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
2A 00101010
36 00110110
80 10000000
A0 10100000
70 01110000
38 00111000
1F 00011111
40 01000000
30 00110000
20 00100000
35 00110101
00 00000000
7E 01111110
D7 11010111
10 00010000
00 00000000
00 00000000
1A 00011010
0F 00001111
5C 01011100
80 10000000
A0 10100000
70 01110000
38 00111000
35 00110101
40 01000000
30 00110000
20 00100000
35 00110101
00 00000000
7E 01111110
D7 11010111
Version 1.0 18 February 2011 27 / 30
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PRODUCT SPECIFICATION
86 56 # 2 H image size : V image size (”382 : 215”)
87 57 # 2 H boarder (”0”)
88 58 # 2 V boarder (”0”)
# 2 Non-interlaced, Normal Display, Digital Separate Sync, V pol
89 59
90 5A
91 5B # 3 Pixel clock (hex LSB first)
92 5C # 3 H active (“1920”)
93 5D # 3 H blank (“160”)
94 5E # 3 H active : H blank (“1920 :160”)
95 5F # 3 V active (”1080”)
96 60 # 3 V blank (”58”)
97 61 # 3 V active : V blank (”1080 :58”)
98 62 # 3 H sync offset (”48”)
99 63 # 3 H sync pulse width ("32”)
100 64 # 3 V sync offset : V sync pulse width (”3 : 5”)
101 65
102 66 # 3 H image size (”382 mm”)
103 67 # 3 V image size (”215 mm”)
104 68 # 3 H image size : V image size (”382 : 215”)
105 69 # 3 H boarder (”0”)
106 6A # 3 V boarder (”0”)
107 6B
108 6C
109 6D # 4 Pixel clock (hex LSB first)
110 6E # 4 H active (“1920”)
111 6F # 4 H blank (“160”)
112 70 # 4 H active : H blank (“1920 :160”)
113 71 # 4 V active (”1080”)
114 72 # 4 V blank (”64”)
115 73 # 4 V active : V blank (”1080 :64”)
116 74 # 4 H sync offset (”48”)
117 75 # 4 H sync pulse width ("32”)
118 76 # 4 V sync offset : V sync pulse width (”3 : 5”)
119 77
120 78 # 4 H image size (”382 mm”)
121 79 # 4 V image size (”215 mm”)
122 7A # 4 H image size : V image size (”382 : 215”)
123 7B # 4 H boarder (”0”)
124 7C # 4 V boarder (”0”)
125 7D
126 7E No extension
127 7F Checksum
Negatives, H pol Positives
Detailed timing description # 3 Pixel clock (“260.38MHz”, According
to VESA CVT Rev1.4)
# 3 H sync offset : H sync pulse width : V sync offset : V sync width
(”48: 32 : 3 : 5”)
# 3 Non-interlaced, Normal Display, Digital Separate Sync, V pol
Negatives, H pol Positives
Detailed timing description # 4 Pixel clock (“285.55MHz”, According
to VESA CVT Rev1.4)
# 4 H sync offset : H sync pulse width : V sync offset : V sync width
(”48: 32 : 3 : 5”)
# 4 Non-interlaced, Normal Display, Digital Separate Sync, V pol
Negatives, H pol Positives
10 00010000
00 00000000
00 00000000
1A 00011010
B6 10110110
65 01100101
80 10000000
A0 10100000
70 01110000
38 00111000
3A 00111010
40 01000000
30 00110000
20 00100000
35 00110101
00 00000000
7E 01111110
D7 11010111
10 00010000
00 00000000
00 00000000
1A 00011010
8B 10001011
6F 01101111
80 10000000
A0 10100000
70 01110000
38 00111000
40 01000000
40 01000000
30 00110000
20 00100000
35 00110101
00 00000000
7E 01111110
D7 11010111
10 00010000
00 00000000
00 00000000
1A 00011010
00 00000000
36 00110110
Version 1.0 18 February 2011 28 / 30
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Appendix. OUTLINE DRAWING
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PRODUCT SPECIFICATION
Version 1.0 18 February 2011 29 / 30
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PRODUCT SPECIFICATION
E207943
MADE IN XXX
10
Version 1.0 18 February 2011 30 / 30
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
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