V
CC
Gnd
OSC
V
FB
COMP
Sense
V
REF
V
OUT
Output
Enable
5V
Reference
Internal
Bias
NOR
S
R
PWM
Latch
Current
Sense
Comparator
Oscillator
1 V
R
2 R
V
C
Error
Amplifier
+
–
2.50V
Set/
Reset
Undervoltage
Lock-out Circuit
34V
( ) Indicates CS-3843B
16V/10V
(8.4V/7.6V)
VCC Pwr
Pwr Gnd
REF
■ Very low Start Up Current
(300µA typ)
■
Optimized Off-line
Control
■
Internally Trimmed,
Temperature
Compensated Oscillator
■
Maximum Duty-cycle
Clamp
■ V
REF
stabilization before
Output Enable
■ Pulse-by-pulse Current
Limiting
■ Improved Undervoltage
Lockout
■ Double Pulse Suppression
■ 1% Trimmed Bandgap
Reference
■ High Current Totem Pole
Output
Package Options
CS3842B/3843B
Off-Line Current Mode PWM
Control Circuit
with Very Low Start Up Current
CS3842B/CS3843B
Description
Block Diagram
Absolute Maximum Ratings
Supply Voltage (I
CC
<30mA) ..........................................................Self Limiting
Supply Voltage (Low Impedance Source)...................................................30V
Output Current ...............................................................................................±1A
Output Energy (Capacitive Load) .................................................................5µJ
Analog Inputs (VFB, Sense) ............................................................-0.3V to 5.5V
Error Amp Output Sink Current...............................................................10mA
Lead Temperature Soldering
Wave Solder (through hole styles only) ...................10 sec. max, 260°C peak
Reflow (SMD styles only) ....................60 sec. max above 183°C, 230°C peak
1
COMP
2
3
4
V
FB
Sense
OSC
V
REF
V
CC
V
OUT
Gnd
8
7
6
5
10
7
14
13
12
8
1
2
3
4
5
6
11
9
COMP
NC
V
FB
NC
Sense
NC
OSC
V
REF
NC
V
CC
VCC Pwr
V
OUT
Pwr Gnd
Gnd
14L SO Narrow
Rev. 6/23/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
The CS384XB provides all the necessary features to implement off-line
fixed frequency current-mode control
with a minimum number of external
components. The family has been optimized for very low start up current
(300µA, typ).
The CS384XB family incorporates a
precision temperature-controlled oscillator with an internally trimmed discharge current to minimize variations
in frequency. A precision duty-cycle
clamp eliminates the need for an external oscillator when a 50% duty-cycle is
used. Duty-cycles of almost 100% are
possible. On board logic ensures that
V
REF
is stabilized before the output
stage is enabled. Ion-implant resistors
provide tighter control of undervoltage
lockout.
Other features include pulse-by-pulse
current limiting, and a high-current
totem pole output for driving capacitive loads, such as the gate of a power
MOSFET. The output is LOW in the off
state, consistent with N-channel
devices.
These ICs are available in 8 and 14 lead
surface mount (SO) and 8 lead PDIP
packages.
2
Electrical Characteristics: 0≤T
A
≤70˚C, VCC=15V (Note 1); RT=680Ω, CT=.022µF for triangular mode,
R
T
=10kΩ, CT=3.3nF for sawtooth mode (see Fig. 3), unless otherwise stated
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
CS3842B/3843B
■ Reference Section
Output Voltage TJ=25˚C, I
OUT
=1mA 4.90 5.00 5.10 V
Line Regulation 12≤VIN≤25V 6 20 mV
Load Regulation 1≤I
OUT
≤20mA 6 25 mV
Temperature Stability (Note 2) 0.2 0.4 mV/˚C
Total Output Variation Line, Load, Temperature (Note 2) 4.82 5.18 V
Output Noise Voltage 10Hz≤f≤10kHz, TJ=25˚C (Note 2) 50 µV
Long Term Stability T
A
=125˚C, 1kHrs. (Note 2) 5 25 mV
Output Short Circuit T
A
=25˚C -30 -100 -180 mA
■ Oscillator Section
Initial Accuracy Sawtooth Mode (see Fig. 3), T
J
=25˚C475257kHz
Triangular Mode (see Fig. 3), TJ=25˚C445260kHz
Voltage Stability 12≤VCC≤25V 0.2 1.0 %
Temp. Stability Sawtooth Mode T
MIN≤TA≤TMAX
(Note 2) 5 %
Triangular Mode T
MIN≤TA≤TMAX
(Note 2) 8 %
Amplitude Oscillator peak to peak 1.7 V
Discharge Current T
J
=25˚C 7.5 8.3 9.3 mA
T
MIN≤TA≤TMAX
7.2 9.5 mA
■ Error Amp Section
Input Voltage V
COMP
=2.5V 2.42 2.50 2.58 V
Input Bias Current -0.3 -2.0 µA
A
VOL
2≤V
OUT
≤4V 65 90 dB
Unity Gain Bandwidth (Note 2) 0.7 1.0 MHz
PSRR 12≤V
CC
≤25V 60 70 dB
Output Sink Current VFB=2.7V, V
OSC
=1.1V 2 6 mA
Output Source Current VFB=2.3V, V
OSC
=5V -0.5 -0.8 mA
V
OUT
High VFB=2.3V, RL=15kΩ to ground 5 6 V
V
OUT
Low VFB=2.7V, RL=15kΩ to V
REF
0.7 1.1 V
■ Current Sense Section
Gain (Notes 3 & 4) 2.85 3.00 3.15 V/V
Maximum Input Signal V
COMP
=5V (Note 3) 0.9 1.0 1.1 V
PSRR 12≤VCC≤25V (Note 3) 70 dB
Input Bias Current -2 -10 µA
Delay to Output TJ=25˚C (Note 2) 150 300 ns
■ Output Section
Output Low Level I
SINK
=20mA 0.1 0.4 V
I
SINK
=200mA 1.5 2.2 V
Output High Level I
SOURCE
=20mA 13.0 13.5 V
I
SOURCE
=200mA 12.0 13.5 V