Cherry Semiconductor CS212EN16, CS212EDWR16, CS212EDW16 Datasheet
Features
■ Receives/Transmits Data
on Only Two Leads
■ Low Current Consumption
■ High Noise Immunity
■ Sabotage Surveilled Loop
Input
Package Options
CS212
Security Detector
Serial-Addressable Receiver/Transmitter
CS212
Description
The S-ART is a 16 pin circuit
designed for data transmission on a
two-lead cable. The circuit is specially developed for alarm systems
where it is desired to identify each
detector individually. There can be
up to 30 S-ART circuits/detectors
on the same 2-lead cable. This cable
transmits both DC supply to the
S-ART and information to/from the
S-ART.
The S-ART works on the principle
by which an address is sent on the
line cable and the S-ART which recognizes the address then carries out
the order which can, in principle, be
two things:
1. Transmit data from the line cable
to the S-ART's two outputs OUT0
and OUT1.
2. Answer the S-ART controller
with the condition of the 2 inputs
IN0 and IN1 or IN2-3.
The line signal is divided into 3 levels in order to give a time signal for
synchronizing and a data signal
containing addresses, orders etc.
Typical signal levels for the three
levels would be 15V, 7.5V and 0V.
Block Diagram
1
OUT0
2
3
4
5
6
7
8
A4
A3
A2
A1
A0
IN1
IN0
16
15
14
13
12
11
10
9
OUT1
DSR
IN2
IN3
V
DD
DATA
OUT
Gnd
LINE
16L PDIP & 16L SO Wide
1
A method by
which, in principle,
the system can be
extended to an
infinite number of
S-ART is shown on
the block diagram.
The controller
scans the in/outputs of a number
of lines, each with
a maximum of 30
S-ARTs.
CK "1"
V
DATA "1"
DATA "0"
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
¨
Rev. 4/21/99
Line 1
Controller
Line N
S-ART
Lead Temperature Soldering:
Wave Solder (through hole styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sec. max 260ûC Peak
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Sec max. above 183ûC, 230ûC Peak
Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150ûC
Maximum Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125¡C
Electrical Characteristics: TA= 25¡C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS212
2
Absolute Maximum Ratings
Operating Temperature Range, T
A
-40 85 ¡C
Device Current I
DD
Outputs unloaded 0.47 0.80 mA
Not Addressed Line Voltage=0-15V, VDD=15V
Device Current I
DD
IN0, IN1 are Open 3.55 5.50 mA
Power-Up-Mode IN2, IN3 are Active
(5 corr. addr. bits)CP4-CP5V
DD
=15V
Device Current I
DD
IN2, IN3 not Active 6.24 9.64 mA
Addressed, Line Output IN0, IN1 are Open
Transistor Active VDD=15V
Device Current I
DD
IN2, IN3 not Active 1.84 2.86 mA
Addressed (4 corr.addr.bits) IN0, IN1 are Open
Line Output Transistor Not Active VDD=15V
Output Voltage Low Level VDD=10-15V 1.2 V
Out0, Out1, DSR I
SINK
=1mA
Output sink Current 1.0 mA
Out0, Out1, DSR
Output Voltage High Level 14 V
Out0, Out1, DSR
Leakage Current V
OUT
=14V 30 µA
Out0, Out1, DSR
Input Voltage Level
Low VDD=10-15V 30%V
DD
V
A0-A4, IN0, IN1 High VDD=10-15V 70%V
DD
V
Input Current IN0, IN1=Gnd VDD=18V 150 850 µA
Power-Up Mode
(4 corr.addr.bits)
Input Current VDD=18V 20 µA
A0-A4, IN0, IN1
Not Addressed
Positive Trigger
Threshold VP, C Clock Comparator 11.0 11.7 12.4 V
Voltage Vdd=15V VP, D Data Comparator 4.6 5.7 6.6 V
Negative Trigger V
NC
VDD=15V Clock Comparator 10.2 10.9 11.6 V
Threshold Voltage V
NC
VDD=15V, Data Comparator 3.4 4.3 5.2 V
Hysteresis Voltage VDD=15V 0.7 0.8 V
Clock/Data Comp.
Saturation Voltage For VDD=15V, IC=50mA 1 V
Line Output Driver
Saturation Voltage For VDD=15V, IC=10mA 0.4 V
Line Output Driver
Leakage Current V
LINE
=0-18V, VDD=18V ±16 µA
For the Line Output
Line Signal Freq. VDD=15V±1V 0 20 kHz
Rise/Fall-Time Line Signal 0.25 250.00 µs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS212
3
Electrical Characteristics: TA= 25¡C, unless otherwise specified.
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
1 OUT0 Output (open collector) from S-ART.
2 A4 Address input. Must be connected to VDDor Gnd according to the
relevant address code.
3 A3 Address input. Must be connected to VDDor Gnd according to the
relevant address code.
4 A2 Address input. Must be connected to VDDor Gnd according to the
relevant address code.
5 A1 Address input. Must be connected to VDDor Gnd according to the
relevant address code.
6 A0 Address input. Must be connected to VDDor Gnd according to the
relevant address code.
7 IN1 Input to S-ART.
8 IN0 Input to S-ART.
9 LINE Signal lead in the line cable.
10 Gnd Zero lead in the line cable.
11 DATA
OUT
Output from the S-ART, which is active in the READ-mode.
Transmits data from
S-ART to line.
12 V
DD
Supply voltage to the S-ART. The voltage is derived from the line
signal.
13 IN3 Sabotage surveilled loop (shorting and breaking).
14 IN2 Sabotage surveilled loop (shorting and breaking).
15 DSR Data Set Ready. Output (open collector) from the S-ART which is
active during WRITE-mode, when OUT0 and OUT1 change.
16 OUT1 Output (open collector) from S-ART.
Turn-On Time For 1.0 µs
Line Output Driver
Turn-Off Time For 1.0 µs
Line Output Driver
Line Voltage VL (Note 1) 0 28 V
Loop Current IN2, IN3 0.1 0.5 mA
Alarm Condition IN2-IN3 1 5 k½
Loop Open
Alarm Condition IN2-IN3 5 30 k½
Loop Shorted
Note 1: The circuit shall function in the correct way only between 0 and 18VDC. Data driver must not turn on when line voltage is above 18V.
Loading...