CHASSIS universal (ШАСI унiверсальні) BRANDT B2205LD FINLUX 10065585, 10067191, 10067192, 10067729, 22FLD841 Service manual & schematics
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TABLE OF CONTENTS
1. INTRODUCTION...................................................................................................................... 6
2. TUNER....................................................................................................................................... 7
2.1. General description of TDTC-G101D: .......................................................................... 7
2.2. Features of TDTC-G101D: ............................................................................................ 7
2.3. Pinning: .......................................................................................................................... 7
3. AUDIO AMPLIFIER STAGE WITH MAX9736(8-10WATT)................................................ 8
3.1. General Description........................................................................................................ 8
3.2. Features .......................................................................................................................... 8
3.3. Applications ................................................................................................................... 8
3.4. Absolute Ratings ............................................................................................................ 9
3.4.1. Electrical Characteristics............................................................................................ 9
3.4.2. Operating Specifications .......................................................................................... 11
3.5. Pinning ......................................................................................................................... 12
AUDIO AMPLIFIER STAGE WITH PT2333(2.5 WATT)............................................................ 12
4. POWER STAGE ...................................................................................................................... 14
5. MICROCONTROLLER (MSTAR)......................................................................................... 15
Genaral Description.................................................................................................................. 15
5.1. Features ........................................................................................................................ 15
6. MPEG-2/MPEG-4 DVB Decoder (STi7101) .......................................................................... 16
6.1. General Description...................................................................................................... 16
6.2 Features ........................................................................................................................ 18
6.3 Absolute Maximum Ratings......................................................................................... 21
7 DVB-T DEMODULATOR – STV0362 .................................................................................. 23
8.1 General Description............................................................................................................ 23
8.2 Features .............................................................................................................................. 25
8.3 Absolute Maximum Rating ................................................................................................ 26
8.4 Pinning ............................................................................................................................... 28
8 DVB-C DEMODULATOR – STV0297E................................................................................ 29
8.1 General Desription ....................................................................................................... 29
8.2 Features ........................................................................................................................ 29
8.3 Absolute Maximum Ratings......................................................................................... 30
8.4 Pinning ......................................................................................................................... 30
9 HY5DV281622DT-5 DDR SDRAM 128M ............................................................................ 31
9.1 General Description...................................................................................................... 31
9.2 Features ........................................................................................................................ 31
9.3 Absolute Maximum Ratings......................................................................................... 32
9.4 Pinning ......................................................................................................................... 32
10 HY5DU561622ETP-5 DDR SDRAM 256M....................................................................... 33
11.1 General Description.......................................................................................................... 33
11.2 Features ............................................................................................................................ 33
11.3 Absolute Maximum Ratings............................................................................................. 34
11.4 Pinning ............................................................................................................................. 35
11 STE100P Ethernet PHY ....................................................................................................... 36
11.1 General Description...................................................................................................... 36
11.2 Features ........................................................................................................................ 36
11.3 Absolute Maximum Ratings......................................................................................... 37
12.4 Pinning ............................................................................................................................. 38
12 SAW FILTER ...................................................................................................................... 41
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12.1 IF Filter for Audio Applications – Epcos K9656M ..................................................... 41
12.1.1 Standart: ................................................................................................................... 41
12.1.2 Features: ................................................................................................................... 41
12.1.3 Pin configuration:..................................................................................................... 42
12.1.4 Frequency response:................................................................................................. 42
12.2 IF Filter for Video Applications – Epcos K3958M...................................................... 43
12.2.1 Standart: ................................................................................................................... 43
12.2.2 Features: ................................................................................................................... 43
12.2.3 Frequency response:................................................................................................. 44
13 2048-Bits Serial EEPROM – 24LC02 ................................................................................. 45
13.1 General Description...................................................................................................... 45
13.2 Features ........................................................................................................................ 45
13.3 Electrical Specifications............................................................................................... 46
13.4 Pinning ......................................................................................................................... 47
14 32K Smart Serial EEPROM – 24C32 .................................................................................. 47
14.1 General Description...................................................................................................... 47
14.2 Features ........................................................................................................................ 47
11.3 Absolute Maximum Ratings and Electrical Characteristics......................................... 48
11.4 Pinning ......................................................................................................................... 49
15 512K CMOS Serial Flash – MX25L512.............................................................................. 50
15.1 General Description...................................................................................................... 50
15.2 Features ........................................................................................................................ 50
11.3 Absolute Maximum Ratings......................................................................................... 51
16 IC DESCRIPTIONS............................................................................................................. 53
16.1 LM1117........................................................................................................................ 53
16.1.1 General Description.................................................................................................. 53
16.1.2 Features .................................................................................................................... 53
16.1.3 Applications ............................................................................................................. 53
16.1.4 Absolute Maximum Ratings..................................................................................... 53
16.1.5 Pinning ..................................................................................................................... 54
16.2 74HCT4053.................................................................................................................. 54
16.2.1 General Description.................................................................................................. 54
16.2.2 Features .................................................................................................................... 54
16.2.3 Applications ............................................................................................................. 54
16.2.4 Absolute Maximum Ratings..................................................................................... 55
16.2.5 Pinning ..................................................................................................................... 55
16.3 NUP4004M5 ................................................................................................................ 55
16.3.1 General Description.................................................................................................. 55
16.3.2 Features .................................................................................................................... 56
16.3.3 Absolute Maximum Ratings..................................................................................... 56
16.3.4 Pinning ..................................................................................................................... 56
16.4 FDN336P...................................................................................................................... 57
16.4.1 General Description.................................................................................................. 57
16.4.2 Features .................................................................................................................... 57
16.4.3 Absolute Maximum Ratings..................................................................................... 57
16.4.4 Pinning ..................................................................................................................... 57
16.5 TL062 -......................................................................................................................... 58
16.5.1 General Description.................................................................................................. 58
16.5.2 Features .................................................................................................................... 58
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16.5.3 Absolute Maximum Ratings..................................................................................... 58
16.5.4 Pinning ..................................................................................................................... 59
16.6 PI5V330 ....................................................................................................................... 59
16.6.1 General Description.................................................................................................. 59
16.6.2 Features .................................................................................................................... 59
16.6.3 Absolute Maximum Ratings..................................................................................... 59
16.6.4 Pinning ..................................................................................................................... 60
16.7 AZC099-04S ................................................................................................................ 60
16.7.1 General Description.................................................................................................. 60
16.7.2 Features .................................................................................................................... 60
16.7.3 Absolute Maximum Ratings..................................................................................... 61
16.7.4 Pinning ..................................................................................................................... 61
16.8 TDA1308...................................................................................................................... 61
16.8.1 General Description.................................................................................................. 61
16.8.2 Features .................................................................................................................... 61
16.8.3 Absolute Maximum Ratings..................................................................................... 62
16.8.4 Pinning ..................................................................................................................... 62
16.9 LM358D ....................................................................................................................... 62
16.9.1 General Description.................................................................................................. 62
16.9.2 Features .................................................................................................................... 62
16.9.3 Absolute Maximum Ratings..................................................................................... 63
16.9.4 Pinning ..................................................................................................................... 63
16.10 74LCX244................................................................................................................ 63
16.10.1 General Description.............................................................................................. 63
16.10.2 Features ................................................................................................................ 64
16.10.3 Absolute Maximum Ratings................................................................................. 64
16.10.4 Pinning ................................................................................................................. 65
16.11 74LCX245................................................................................................................ 65
16.11.1 General Description.............................................................................................. 65
16.11.2 Features ................................................................................................................ 65
16.11.3 Absolute Maximum Ratings................................................................................. 66
16.11.4 Pinning ................................................................................................................. 66
16.12 FSA3157................................................................................................................... 66
16.12.1 General Description.............................................................................................. 66
16.12.2 Features ................................................................................................................ 67
16.12.3 Absolute Maximum Ratings................................................................................. 67
16.12.4 Pinning ................................................................................................................. 67
16.13 TSH343 .................................................................................................................... 68
16.13.1 General Description.............................................................................................. 68
16.13.2 Features ................................................................................................................ 68
16.13.3 Absolute Maximum Ratings................................................................................. 68
16.13.4 Pinning ................................................................................................................. 69
16.14 MT48LC4M16A2TG8E........................................................................................... 69
16.14.1 General Description.............................................................................................. 69
16.14.2 Features ................................................................................................................ 69
16.14.3 Absolute Maximum Ratings................................................................................. 70
16.14.4 Pinning ................................................................................................................. 70
16.15 MP1583 .................................................................................................................... 71
16.15.1 General Description.............................................................................................. 71
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16.15.2 Features ................................................................................................................ 71
16.15.3 Absolute Maximum Ratings................................................................................. 71
16.15.4 Pinning ................................................................................................................. 72
16.16 MP2112 .................................................................................................................... 72
16.16.1 General Description.............................................................................................. 72
16.16.2 Features ................................................................................................................ 72
16.16.3 Absolute Maximum Ratings................................................................................. 73
16.16.4 Pinning ................................................................................................................. 73
16.17 MAX809LTR ........................................................................................................... 73
16.17.1 General Description.............................................................................................. 73
16.17.2 Features ................................................................................................................ 73
16.17.3 Absolute Maximum Ratings................................................................................. 74
16.17.4 Pinning ................................................................................................................. 74
17 SERVICE MENU SETTINGS............................................................................................. 75
17.1 Video Setup .................................................................................................................. 75
17.2 AudioSetup................................................................................................................... 75
17.3 Service Scan/Tuning Setup .......................................................................................... 77
17.4 Options ......................................................................................................................... 77
17.5 External Source Settings .............................................................................................. 79
17.6 Preset ............................................................................................................................ 80
17.7 NVM Edit..................................................................................................................... 80
17.8 Programming................................................................................................................ 80
17.9 Diagnostic..................................................................................................................... 80
17.10 Product Info.............................................................................................................. 80
18 SOFTWARE UPDATE DESCRIPTION............................................................................. 81
16.1 17MB37 Analog Part Software Update With Bootloader Procedure ......................... 81
16.2 17MB37 HDCP key upload procedure. ...................................................................... 84
16.3 17MB37 Digital Software Update From SCART ........................................................ 85
16.4 17MB37 Digital Software Update From USB ............................................................. 90
19 BLOCK DIAGRAMS .......................................................................................................... 91
19.1 General Block Diagram................................................................................................ 91
19.2 Power Management...................................................................................................... 93
19.3 MSTAR Block Diagram............................................................................................... 94
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1. INTRODUCTION
17MB37 Main Board consists of MSTAR concept.(Up to 32”) This IC is capable of
handling Video processing, Audio processing, Scaling-Display processing, 3D comb filter,
OSD and text processing, 8 bit dual LVDS transmitter.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards
as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo.
Sound system output is supplying max. 2x8W (10%THD) for stereo 8
change according to IC thay is being used.
Supported peripherals are:
1 RF input VHF I, VHF III, UHF @ 75Ohm(Common)
1 Side AV (SVHS, CVBS, HP, R/L_Audio) (Common)
1 SCART sockets(Common)
1 YPbPr (Common)
1 PC input(Optional)
2 HDMI 1.3 input(2 HDMI inputs are common)
1 Stereo audio input for PC(Common)
1 Line out(Common)
1 S/PDIF output(Common)
1 Side S-Video(Optional)
1 Headphone(Common)
1 Common interface(Common)
1 Digital USB or 1 Analog USB + 2 Digital USB(Optional)
Ω speakers. This will
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2. TUNER
A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH).
The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info about the tuner.
2.1. General description of TDTC-G101D:
The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to
863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.
2.2. Features of TDTC-G101D:
Digital Half-NIM tuner for COFDM
Covers 3 Bands(From 48MHz to 862MHz for COFDM,
From 45.25MHz to 863.25MHz for CCIR CH)
Including IF AGC with SAW Filter
Bandwidth Switching (7/8 MHz) possible
DC/DC Converter built in for Tuning Voltage
Internal(or External) RF AGC, Antenna Power Optional
2.3. Pinning:
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3. AUDIO AMPLIFIER STAGE WITH MAX9736(8-10WATT)
3.1. General Description
The MAX9736A/B Class D amplifiers provide high-performance,thermally efficient
amplifier solutions. The
into a 4Ω load. The MAX9736B delivers 2 x 6W into 8Ω loads or 1 x 12W into a 4Ω
These devices are pinfor pin compatible, allowing a single audio design to work across a
broad range of platforms, simplifying design efforts, and reducing PCB inventory.
Both devices operate from 8V to 28V and provide a high PSRR, eliminating the need for a
regulated power supply. The MAX9736 offers up to 88% efficiency at 12V supply.
Pin-selectable modulation schemes select between filterless modulation and classic PWM
modulation.
Filterless modulation allows the MAX9736 to pass CE EMI limits with 1m cables using
only a low-cost ferrite bead and capacitor on each output. Classic PWM modulation
is optimized for best audio performance when using a full LC filter.
A pin-selectable stereo/mono mode allows stereo operation
operation into 4Ω loads. In
spare device, allowing flexibility in system design. Comprehensive click-and-pop reduction
circuitry minimizes noise coming into and out of shutdown or mute.
Input op amps allow the user to create summing amplifiers, lowpass or highpass filters,
and select an optimal gain. The MAX9736A/B are available in 32-pin TQFN packages
and specified over the -40°C to +85°C temperature range.
MAX9736A delivers 2 x 15W into 8Ω loads, or 1 x 30W
load.
into 8Ω loads or mono
mono mode, the right input op amp becomes available as a
3.2. Features
Wide 8V to 28V Supply Voltage Range
♦ Spread-Spectrum Modulation Enables Low EMI
Solution
♦ Passes CE EMI Limits with Low-Cost Ferrite
Bead/Capacitor Filter
♦ Low BOM Cost, Pin-for-Pin Compatible Family
♦ High 67dB PSRR at 1kHz Reduces Supply Cost
♦ 88% Efficiency Eliminates Heatsink
♦ Therm
♦ < 1μA Shutdown Mode
♦ Mute Function
♦ Space
Package
al and Output Current Protection
-Saving, 7mm x 7mm x 0.8mm, 32-Pin TQFN
3.3. Applications
LCD/PDP/CRT Monitors
LCD/PDP/CRT TVs
MP3 Docking Stations
Notebook PCs
PC Speakers
All-in-One PCs
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3.4. Absolute Ratings
3.4.1. Electrical Characteristics
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3.4.2. Operating Specifications
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3.5. Pinning
AUDIO AMPLIFIER STAGE WITH PT2333(2.5 WATT)
The PT2333 is a Class-D power amplifier designed for audio equipments, maximum
output power can reach
composed of exclusively designed Class-D circuitry (patented) by PTC, along with
the most advanced semi-conductor technology. When compared to the traditional
Class-AB amplifiers, the PT2333’s has a much higher efficiency (>80%), low
heat dissipation, and produces superior audio quality. PT2333’s external circuitry is
simple and easily accessible, and consists of flawless self-protection capabilities.
The chip’s packaging is small, thus it occupies an insignificant amount of space on
the circuit board; therefore, making it the predominant choice when it comes to
audio amplifiers.
up to 2.5W (VDD=5V, RL=4Ω, THD=10%). The PT2333
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Features
CMOS technology
Operating voltage range from 2.7V up to 5.5V
Differential analog input
Maximum output power 2.5W(4Ω) @ THD=10%
Output low-pass LC filter is not required.
Voltage gain determinate by the external resister
Contains shutdown function
POP noises free in shutdown and power ON/OFF
period
Built-in short circuit protection
Built-in overheat protection
High efficiency (8Ω load >85%), low heat
dissipation
Available in MSOP 10-pin and WLCSP 9-pin
miniature packages
Aplications
Cellular phone
Portable media player
GPS
LCD monitor
Small multimedia speakers
Hand-free phone
Laptop
Other audio applications
Block Diagram
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4. POWER STAGE
The DC voltages required at various parts of the chassis and inverters are provided by a
main power supply unit. The power supply generates 33V, 24V, 12V, 5V, 3,3V and 5V,
3,3V stand by mode DC voltages. Power stage which is on-chasis generates 1,26V stand
by voltage and 8V, 2.5V, 2,6V, 1,8V and 1V supplies for other different parts of the
chassis.
ADAPTOR USE (Optional)
The DC voltages required at various parts of the chassis and inverters are provided by an
external power supply unit or produced on the chassis if an adapter is used for the supply.
The 12V dc voltage is switched by IRF 7314 power mosfet in TV sets with mechanical
switch to produce the required standby voltage. Also regulators and mosfets generate
1.8V, 3.3V and 5V and 1.26V voltages for other different parts of the chassis.
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5. MICROCONTROLLER (MSTAR)
Genaral Description
The MST6WB7GQ-3 is a high performance and fully integrated IC for multi-function LCD
monitor/TV with resolutions up to full HD (1920x1080). It is configured with an integrated
triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver, a multi-standard TV video and audio
decoder, two video de-interlacers, two scaling engines, the MStarACE-3 color engine, an on-screen
display controller, an 8-bit MCU and a built-in output panel interface. By use of external frame
buffer, PIP/POP is provided for multimedia applications. Furthermore, 3-D video decoding and
processing are fulfilled for high-quality TV applications. To further reduce system costs, the
MST6WB7GQ-3 also integrates intelligent power management control capability for greenmode requirements and spread-spectrum support for EMI management.
5.1. Features
LCD TV controller with PIP/POP display functions
Input supports up to UXGA & 1080P
Panel supports up to full HD (1920x1080)
TV decoder with 3-D comb filter
Multi-standard TV sound demodulator and decoder
10-bit triple-ADC for TV and RGB/YPbPr
10-bit video data processing
Integrated DVI/HDCP/HDMI compliant receiver
High-quality dual scaling engines & dual 3-D video de-interlacers
3-D video noise reduction
Full function PIP/PBP/POP
MStarACE-3 picture/color processing engine
Embedded On-Screen Display (OSD) controler engine
Built-in MCU supports PWM & GPIO
Built-in dual-link 8/10-bit LVDS transmitter
5-volt tolerant inputs
Low EMI and power saving features
296-pin LQFP
NTSC/PAL/SECAM Video Decoder
Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM
Automatic TV standard detection
Motion adaptive 3-D comb filter for NTSC/PAL
8 configurable CVBS & Y/C S-video inputs
Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip
Macrovision detection
CVBS video output
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Video IF for Multi-Standard Analog TV
Digital low IF architecture
Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution
Maximum IF analog gain of 37dB in addition to digital gain
Programmable TOP to accommodate different tuner gain to optimize noise and linearity
performance
Multi-Standard TV Sound Decoder
Supports BTSC/NICAM/A2/EIA-J demodulation and decoding
FM stereo & SAP demodulation
L/Rx4, mono, and SIF audio inputs
L/Rx3 loudspeaker and line outputs
Supports sub-woofer output
Built-in audio output DAC’s
Audio processing for loudspeaker channel, including volume, balance, mute, tone, EQ, and
virtual stereo/surround
Optional advanced surround available (Dolby1, SRS2, BBE3… etc)
Digital Audio Interface
I2S digital audio input & output
S/PDIF digital audio input & output
HDMI audio channel processing capability
Programmable delay for audio/video synchronization
Analog RGB Compliant Input Ports
Three analog ports support up to UXGA
Supports HDTV RGB/YPbPr/YCbCr
Supports Composite Sync and SOG (Sync-on-Green) separator
Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port
Two HDMI input ports with built-in switch
Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color resolution
Single link on-chip DVI 1.0 compliant receiver
High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver
6. MPEG-2/MPEG-4 DVB Decoder (STi7101)
6.1. General Description
The STi7101 is a new generation, high-definition IDTV / set-top box / DVD decoder chip, and
provides very high performance for low-cost HD systems. STx7101 includes an H.264 video
decoder for new, low bit rate applications. Based on the Omega2 (STBus) architecture, this
system-on-chip is a full back-end processor for digital terrestrial, satellite, cable, DSL and IP
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client high-definition set-top boxes, compliant with ATSC, DVB, DIRECTV, DCII,
OpenCable and ARIB BS4 specifications. It includes all processing for DVD applications.
The STx7101 demultiplexes, decrypts and decodes HD or SD video streams with associated
multi-channel audio. Video is output to two independently formatted displays: a full resolution
display intended for a TV monitor, and a downsampled display intended for a VCR or DVD-R.
Connection to a TV or display panel can be analog through the DACs, or digital through a copy
protected DVI/HDMI. Composite outputs are provided for connection to the VCR with
Macrovision protection. Audio is output with optional PCM mixing to an S/PDIF interface,
PCM interface, or through integrated stereo audio DACs. Digitized analog programs can also
be input to the STx7101 for reformatting and display. The STx7101 includes a graphics
rendering and display capability with a 2D graphics accelerator, three graphics planes and a
cursor plane. A dual display compositor provides mixing of graphics and video with
independent composition for each of the TV and VCR/DVD-R outputs. The STx7101 includes
a stream merger to allow seven different transport streams from different sources to be merged
and processed concurrently. Applications include DVR time-shifted viewing of a terrestrial
program, while acquiring an EPG/data stream from a satellite or cable front end.
The flexible descrambling engine is compatible with required standards including DVB, DES,
AES and Multi2. The STx7101 embeds a 266 MHz ST40-202 CPU for applications and device
control. A dual DDR1 SDRAM memory interface is used for higher performance, to allow the
video decoder the required memory bandwidth for HD H.264 and sufficient bandwidth for the
CPU and the rest of the system. A second memory bus is also provided for flash memory,
storing resident software, and for connection of peripherals. This bus also has a high speed
synchronous mode that can be used to exchange data between two STx7101 devices. This can
be used to connect a second STx7101 as a co-decoder for a dual TV STB application. A harddisk drive (HDD) can be connected either to the serial ATA interface, or as an expansion drive
through the USB 2.0 port.
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The figure below shows the architecture of the Sti7101.
6.2 Features
The STx7101 is a single-chip, high definition video decoder including:
_ H.264 support
_ Linux® and OS21 compatible ST40 CPU core: 266 MHz
_ transport filtering and descrambling
_ video decoder: H.264 (MPEG-4 part 10) and MPEG-2
_ SVP compliant
_ graphics engine and dual display: standard and highdefinition
_ audio decoder
_ DVD data retrieval and decryption
The STx7101 also features the following embedded interfaces:
_ USB 2.0 host controller/PHY interface
_ DVI/HDMI™ output
_ digital audio and video auxiliary inputs
_ low-cost modem
_ 100BT ethernet controller with integrated MAC and MII/ RMII interface for external PHY
_ serial ATA (SATA)
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Processor subsystem
_ ST40 32-bit superscaler RISC CPU
_ 266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU
_ 5-stage pipeline, delayed branch support
_ floating point unit, matrix operation support
_ debug port, interrupt controller
Transport subsystem
_ TS merger/router
_ 2 serial/parallel inputs
_ 1 bidirectional interface
_ merging of 3 external transport streams
_ transport streams from memory support
_ NRSS-A module interface
_ TS routing for DVB-CI and CableCARD
modules
_ Programmable transport interfaces (PTIs)
_ two programmable transport interfaces
_ two transport stream demultiplexers: DVB, DIRECTV®, ATSC, ARIB, OpenCable, DCII
_ integrated DES, AES, DVB and Multi2 descramblers
_ NDS random access scrambled stream protocol (RASP) compliant
_ NDS ICAM CA
_ support for VGS, Passage and DVS042 residue handling
Video/graphics subsystem
_ H.264(MPEG-4 part 10) main and high profile level 4.1/MPEG-2 MP@HL video decoder
_ advanced error concealment and trick mode support
_ dual MPEG-2 MP@HL decode
_ SD digital video input
_ Displays
_ one HD display multi format capable (1080I, 720P, 480P/576P, 480I/576I)
analog HD output RGB or YPbPr
HDMI encoded output
_ one standard-definition display
analog SD output: YPbPr or YC and CVBS
_ Gamma 2D/3D graphics processor
_ triple source 2D gamma blitter engine
_ alpha blending and logical operations
_ color space and format conversion
_ fast color fill
_ arbitrary resizing with high quality filters
_ acceleration of direct drawing by CPU
_ Gamma compositor and video processor
_ 7-channel mixer for high definition output
_ independent 2-channel mixer for SD output
_ 3 graphic display planes
_ high-quality video scaler
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_ motion and detail adaptive deinterlacer
_ linear resizing and format conversions
_ horizontal and vertical filtering
_ Copy protection
_ HDMI /HDCP copy protection hardware
_ SVP compliant
_ Macrovision® copy protection for 480I, 480P, 576I, 576P outputs
_ DTCP-IP
_ AWG-based DCS analog copy protection
Audio subsystem
_ Digital audio decoder
_ support for all the most popular audio standards including MPEG-1 layer I/II, MPEG-2 layer
II, MPEG-2 AAC, MPEG- 4 AAC LC 2-channel/5.1 channel MPEG-4 AAC+SBR 2channel/5.1 channel, Dolby® Digital EX, Pro Logic® II, MLP™ and DTS®
_ PCM mixing with internal or external source and sample rate conversion
_ 6- to 2-channel downmixing
_ PCM audio input
_ independent multichannel PCM output, S/PDIF output and analog output
_ Stereo 24-bit audio DAC for analog output
_ IEC958/IEC1937 digital audio output interface (S/PDIF)
_ CSS/CPxM copy protection hardware Interfaces
_ External memory interface (EMI)
_ 16-bit interface supporting ROM, flash, SFlash, SRAM, peripherals
_ access in 5 banks
_ high speed synchronous mode for interconnecting two STx7101 devices
_ External microprocessor interface (EMPI)
_ 32-bit MPX satellite, target-only interface,
_ synchronous operation at MPX clock speed, capable of 100 MHz,
_ Dual local memory interface (LMI)
_ dual interface (2 x 32-bit) for DDR1 200-MHz (DDR400) memories,
supports 128-, 256- and 512-Mbit devices
_ USB 2.0 host controller/PHY interface
_ Serial ATA hard-disk drive support
_ record and playback with trick modes
_ pause and time shifting, watch and record
_ 100BT Ethernet controller, MAC and MII/RMII
_ On-chip peripherals
_ 4 ASCs (UARTs) with Tx and Rx FIFOS, two of which can be used in smartcard interfaces
_ 2 smartcard interfaces and clock generators (improved to reduce external circuitry)
_ 3 SSCs for I²C/SPI master slaves interfaces
_ serial communications interface (SCIF)
_ 2 PWM outputs
_ teletext serializer and DMA module
_ 6 banks of general purpose I/O, 3.3 V tolerant
_ SiLabs line-side (DAA) interface
_ modem analog front end (MAFE) interface
_ infrared transmitter/receiver supporting RC5, RC6 and RECS80 codes
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_ UHF remote receiver input interface
_ interrupt level controller and external interrupts, 3.3 V tolerant
_ low power/RTC/watchdog controller
_ integrated VCXO
_ DiSEqC 2.0 interface
_ PWM capture/compare functions
_ Flexible multi-channel DMA Services and package
_ JTAG/TAP interface, ST40 toolset support, ST231 toolset support
_ Package
_ 35 x 35 PBGA, 580 + 100 balls (standard version)
6.3 Absolute Maximum Ratings
I/O specifications 3.3 volt pads
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I/O specifications 2.5 volt pads
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1
7 – DVB-T Demodulator (COFDM) DRX3973D
7.1 General description:
The DRX 3973D is the fourth-generation COFDM demodulator that offer today’s highest level of front-end integration
resulting in ultimate DVB-T digital reception, compliant to ETS 300 744, DTG D-Book, EICTA E-Book, and Nordig Unified
v1.0.2 .
The DRX 3973D applies cutting-edge digital filtering techniques in combination with a high-performance A/D-converter
and PLL configuration, resulting in
superior performance figures in the presence of digital and analog adjacent channels.
Progressive channel estimator algorithms provide exceptional performance in multipath- and dynamicecho conditions –
an especially important feature for single-frequency networks and indoor reception.
The state-of-the-art impulsive noise cruncher suppresses interferences originating from sources such as cars, electrical
motors, and household appliances.
7.2 Features
– Highest level of front-end integration and flexibility: • Integrated PGA (programmable gain amplifier) 30 dB
• Single 8 MHz SAW filter operation
• 2 AGC control signals available for RF and IF amplifier control
• Flexible clock reference options
• Re-use of 4 MHz tuner clock reference
• Pre-SAW sense input for optimal RF AGC setting and RF-level measurement
– Excellent digital reception performance:
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2
• Superior digital and analog adjacent channel performance (> 40dB for QEF)
• Impulsive noise cruncher
• Multipath and dynamic echoes
– The input IF frequency ranging up to 44 MHz ensures upward compatibility for new tuner topologies
– Integrated microprocessor to perform autonomous detection and operation of all possible DVB-T modes, without
interaction with the host processor
– Fully automatic and fast signal acquisition: UHF and VHF band-scan in <20 seconds
– Meets all international DVB-T receiver specifications: Nordig Unified, DTG, EICTA
– Comfortable software drivers for integration of tuner and COFDM demodulator
– Secondary serial interface for tuner control
– 5 V tolerant AGC and secondary serial protocol outputs
– 2 general purpose I/O pins (GPIO)
– Configurable parallel or serial MPEG-TS output
– PMQFP64-2 package: footprint 10
10 mm (DRX 3973D)
7.3 Absolute Maximum Ratings
7.4 Pin description:
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345
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8 DVB-C DEMODULATOR – STV0297E
8.1 General Desription
The STV0297E is a complete single-chip QAM (quadrature amplitude modulation)
demodulation and FEC (forward error correction) solution that performs sampled IF to
transport stream (MPEG-2 or MPEG-4) block processing of QAM signals. It is intended for
the digital transmission of compressed television, sound, and data services over cable. It
is fully compliant with ITU-T J83 Annexes A/C or DVB-C specification bitstreams (ETS
300 429, “Digital broadcasting systems for television, sound and data services – Framing
structure, channel coding and modulation - Cable Systems”). It can handle square (16,
64, 256-QAM) and non-square (32, 128-QAM) constellations. Japanese DBS systems
require a transport stream multiplex frame (TSMF) layer to carry digital signals over cable
systems. When the recovered transport stream is a multiplex frame, the STV0297E postprocesses it to extract a single transport stream. Automatic detection of the TSMF layer is
provided. The chip integrates an analog-to-digital converter that delivers the required
performance to handle up to 256-QAM signals in a direct IF sampling architecture, thus
eliminating the need for external downconversion.
8.2 Features
Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams
Processes Japanese transport stream multiplex frame (TSMF)
High-performance integrated A/D converter suitable for direct IF architecture in all
QAM (quadrature amplitude modulation) modes
Supports 16, 32, 64, 128 and 256 point constellations
Small footprint package: (10 x 10 mm²)
Very low power consumption
Full digital demodulation
Variable symbol rates
Front derotator for better low symbol rate performance and relaxed tuner
constraints
Integrated matched filtering
Robust integrated adaptive pre and post equalizer
On-chip FEC A/C with ability to bypass individual blocks
10 programmable GPIO
Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs)
Integrated signal quality monitors, plus lock indicator and interrupt function mapped
to GPIO pin
Improved signal acquisition
System clock generated on-chip from quartz crystal
Low frequency crystal operations 4, 16, 25 - 30 MHz
4 I2C addresses
Easy control and monitoring via 2-wire fast I2C bus
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8.3 Absolute Maximum Ratings
8.4 Pinning
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9 HY5DV281622DT-5 DDR SDRAM 128M
9.1 General Description
The Hynix HY5DV281622 is a 134,217,728-bit CMOS Double Data Rate(DDR)
Synchronous DRAM, ideally suited for the point-to-point applications which requires high
bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations
referenced to both rising and falling edges of the clock. While all addresses and control
inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2.
9.2 Features
3.3V for VDD and 2.5V for VDDQ power supply
All inputs and outputs are compatible with SSTL_2 interface
JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers
when write (centered DQ)
Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the
data strobe
All addresses and control inputs except Data, Data strobes and Data masks
latched on the rising edges of the clock
Write mask byte controls by LDM and UDM
Programmable /CAS latency 3 / 4 supported
Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Full, Half and Matched Impedance(Weak) strength driver option controlled by
EMRS
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9.3 Absolute Maximum Ratings
9.4 Pinning
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10 HY5DU561622ETP-5 DDR SDRAM 256M
11.1 General Description
The Hynix HY5DU561622DTP is a 268,435,456-bit CMOS Double Data Rate(DDR)
Synchronous DRAM, ideally suited for the point-to-point applications which requires high
bandwidth. The Hynix 16Mx16 DDR SDRAMs offer fully synchronous operations
referenced to both rising and falling edges of the clock. While all addresses and control
inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2.
11.2 Features
• 2.5V +/-5% VDD and VDDQ power supply
supports 200 / 166MHz
• All inputs and outputs are compatible with SSTL_2 interface
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has 2 bytewide data strobes (LDQS,UDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered DQ)
• Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data
strobe
• All addresses and control inputs except Data, Data strobes and Data masks latched on
the rising edges
of the clock
• Write mask byte controls by LDM and UDM
• Programmable /CAS latency 3 / 4 supported
• Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Full, Half and Matched Impedance(Weak) strength driver option controlled by EMRS
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11.3 Absolute Maximum Ratings
Page 34
11.4 Pinning
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11 STE100P Ethernet PHY
11.1 General Description
The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet
physical layer interface for 10Base-T and 100Base-TX applications. It was designed with
advanced CMOS technology to provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for
100Base-TX of IEEE802.3u and 10Base-T of IEEE802.3.
The STEPHY1 supports both half-duplex and fullduplex operation, at 10 and 100 Mbps
operation. Its operating mode can be set using auto-negotiation, parallel detection or
manual control. It also allows for the support of auto-negotiation functions for speed and
duplex detection.
11.2 Features
- IEEE802.3u 100Base-TX and IEEE802.3 10Base-T compliant
- Support for IEEE802.3x flow control
- IEEE802.3u Auto-Negotiation support for 10Base-T and 100Base-TX
- MII interface
- Standard CSMA/CD or full duplex operation supported
- Integrates the whole Physical layer functions of 100Base-TX and 10Base-T
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- Provides Full-duplex operation on both 100Mbps and 10Mbps modes
- Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100
Mbps
- Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
- Provides transmit wave-shaper, receive filters, and adaptive equalizer
- Provides loop-back modes for diagnostic
- Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
- Supports external transmit transformer with turn ratio 1:1
- Supports external receive transformer with turn ratio 1:1
- Standard 64-pin QFP package pinout
11.3 Absolute Maximum Ratings
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12.4 Pinning
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12SAW FILTER
12.1 IF Filter for Audio Applications – Epcos K9656M
12.1.1 Standart:
B/G
D/K
I
L/L’
12.1.2 Features:
TV IF audio filter with two channels
Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75
MHz (L’- NICAM)
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Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz
and 33,40 MHz
12.1.3 Pin configuration:
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output
12.1.4 Frequency response:
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12.2 IF Filter for Video Applications – Epcos K3958M
12.2.1 Standart:
B/G
D/K
I
L/L’
12.2.2 Features:
TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
Constant group delay
Pin configuration:
1 Input
2 Input - ground
3 Chip - carrier ground
4 Output
5 Output
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12.2.3 Frequency response:
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132048-Bits Serial EEPROM – 24LC02
13.1 General Description
The 24LC01/02 is a 1K/2K-bit serial read/write non-volatile memory device using the
CMOS floating gate process. Its 1024/2048 bits of memory are organized into 128/256
words and each word is 8 bits. The device is optimized for use in many industrial and
commercial applications where low power and low voltage operation are essential. Up to
eight HT24LC01/02 devices may be connected to the same two-wire bus. The
HT24LC01/02 is guaranteed for 1M erase/write cycles and 40-year data retention.
13.2 Features
Operating voltage: 2.4V~5.5V
Low power consumption
Operation: 5mA max.
Standby: 5mA max.
Internal organization
1K (HT24LC01):128´8
2K (HT24LC02): 256´8
2-wire serial interface
Write cycle time: 5ms max.
Automatic erase-before-write operation
Partial page write allowed
8-byte Page write modes
Write operation with built-in timer
Hardware controlled write protection
40-year data retention
106 erase/write cycles per word
8-pin DIP/SOP package
8-pin TSSOP (HT24LC02 only)
Commerical temperature range (0°C to +70°C)
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13.3 Electrical Specifications
Page 46
13.4 Pinning
1432K Smart Serial EEPROM – 24C32
14.1 General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable
PROM. This device has been developed for advanced, low power applications such as
personal communications or data acquisition. The 24C32 features an input cache for fast
write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4Kbit block of ultra-high endurance memory for data that changes frequently. The 24C32 is
capable of both random and sequential reads up to the 32K boundary. Functional address
lines allow up to eight 24C32 devices on the same bus, for up to 256K bits address
space. Advanced CMOS technology makes this device ideal for low-power non-volatile
code and data applications. The 24C32 is available in the standard 8-pin plastic DIP and
8-pin surface mount SOIC package.
14.2 Features
Voltage operating range: 4.5V to 5.5V
Peak write current 3 mA at 5.5V
Maximum read current 150 µA at 5.5V
Standby current 1 µA typical
Industry standard two-wire bus protocol, I2C compatible
Including 100 kHz and 400 kHz modes
Self-timed write cycle (including auto-erase)
Power on/off data protection circuitry
Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance Block,
1,000,000 E/W cycles guaranteed for Standard Endurance Block
8 byte page, or byte modes available
1 page x 8 line input cache (64 bytes) for fast write loads
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Schmitt trigger, filtered inputs for noise suppression
Output slope control to eliminate ground bounce
2 ms typical write cycle time, byte or page
Up to 8 chips may be connected to the same bus for up to 256K bits total memory
Electrostatic discharge protection > 4000V
Data retention > 200 years
8-pin PDIP/SOIC packages
Temperature ranges: Commercial (C): 0°C to +70°C, Industrial (I): -40°C to +85°C
11.3 Absolute Maximum Ratings and Electrical Characteristics
Page 48
11.4 Pinning
Page 49
15512K CMOS Serial Flash – MX25L512
15.1 General Description
The MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as
65,536 x 8 internally. The MX25L512 feature a serial peripheral interface and software
protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the
device is enabled by CS# input. The MX25L512 provide sequential read operation on
whole chip. After program/erase command is issued, auto program/ erase algorithms
which program/ erase and verify the specified page or sector/block locations will be
executed. Program command is executed on page (256 bytes) basis, and erase
command is executes on chip or sector (4K-bytes). To provide user with ease of interface,
a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via
WIP bit. When the device is not in operation and CS# is high, it is put in standby mode
and draws less than 10uA DC current. The MX25L512 utilize MXIC's proprietary memory
cell, which reliably stores memory contents even after 100,000 program and erase cycles.
15.2 Features
GENERAL
Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
524,288 x 1 bit structure
16 Equal Sectors with 4K byte each
Any Sector can be erased individually
Single Power Supply Operation
2.7 to 3.6 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
High Performance
Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock
(30pF + 1TTL Load)
Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.)
and 2s(max.)/chip(512Kb)
Low Power Consumption
Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and
4mA(max.) at 33MHz
Low active programming current: 15mA (max.)
Low active erase current: 15mA (max.)
Low standby current: 10uA (max.)
Deep power-down mode 1uA (typical)
Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
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Input Data Format
1-byte Command code
Block Lock protection
The BP0~BP1 status bit defines the size of the area to be software protected
against Program and Erase instructions.
Auto Erase and Auto Program Algorithm
Automatically erases and verifies data at selected sector
Automatically programs and verifies data at selected page by an internal algorithm
that automatically times the program pulse widths (Any page to be programed
should have page in the erased state first)
Status Register Feature
Electronic Identification
JEDEC 2-byte Device ID
RES command, 1-byte Device ID
HARDWARE FEATURES
SCLK Input
Serial clock input
SI Input
Serial Data Input
SO Output
Serial Data Output
WP# pin
Hardware write protection
HOLD# pin pause the chip without diselecting the chip
PACKAGE
8-pin SOP (150mil)
All Pb-free devices are RoHS Compliant
11.3 Absolute Maximum Ratings
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16IC DESCRIPTIONS
16.1 LM1117
16.1.1 General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA
of load current. It has the same pin-out as National Semiconductor’s industry standard
LM317. The LM1117 is available in an adjustable version, which can set the output
voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF
tantalum capacitor is required at the output to improve the transient response and
stability.
16.1.2 Features
Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
Space Saving SOT-223 Package
Current Limiting and Thermal Protection
Output Current 800mA
Line Regulation 0.2% (Max)
Load Regulation 0.4% (Max)
Temperature Range
LM1117 0°C to 125°C
LM1117I -40°C to 125°C
16.1.3 Applications
2.85V Model for SCSI-2 Active Termination
Post Regulator for Switching DC/DC Converter
High Efficiency Linear Regulators 15
32” TFT TV Service Manual 10/01/2005
Battery Charger
Battery Powered Instrumentation
16.1.4 Absolute Maximum Ratings
Page 53
16.1.5 Pinning
16.2 74HCT4053
16.2.1 General Description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The
74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs
(Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to
S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to
S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and
E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
16.2.2 Features
Low ON resistance:
80 W (typical) at VCC - VEE = 4.5 V
70 W (typical) at VCC - VEE = 6.0 V
60 W (typical) at VCC - VEE = 9.0 V
Logic level translation:
To enable 5 V logic to communicate with ±5 V analog signals
Typical ‘break before make’ built in
Complies with JEDEC standard no. 7A
ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22-
A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
16.2.3 Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
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16.2.4 Absolute Maximum Ratings
16.2.5 Pinning
16.3 NUP4004M5
16.3.1 General Description
This 5-Pin bi-directional transient suppressor array is designed for applications requiring
transient overvoltage protection capability. It is intended for use in transient voltage and
Page 55
ESD sensitive equipment such as computers, printers, cell phones, medical equipment,
and other applications. Its integrated design provides bi-directional protection for four
separate lines using a single TSOP-5 package. This device is ideal for situations where
board space is a premium.
16.3.2 Features
Bi-directional Protection for Four Lines in a Single TSOP-5 Package
Low Leakage Current
Low Capacitance
Provides ESD Protection for JEDEC Standards JESD22
Machine Model = Class C
Human Body Model = Class 3B
Provides ESD Protection for IEC 61000-4-2, 15 kV (Air), 8 kV (Contact)
This is a Pb-Free Device
16.3.3 Absolute Maximum Ratings
16.3.4 Pinning
Page 56
16.4 FDN336P
16.4.1 General Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),
organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C
bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM
data clocked out from the rising edge of the signal applied on VCLK. The device will
switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL
pin. The ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power
supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages
are available.
16.4.2 Features
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
2.5V to 5.5V SINGLE SUPPLY VOLTAGE
400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE
TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP PERFORMANCES
16.4.3 Absolute Maximum Ratings
16.4.4 Pinning
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16.5 TL062 -
16.5.1 General Description
Low-power JFET-input operational amplifier
16.5.2 Features
Very Low Power Consumption
Typical Supply Current . . . 200 µA (Per Amplifier)
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Common-Mode Input Voltage Range Includes VCC+
Output Short-Circuit Protection
High Input Impedance . . . JFET-Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate . . . 3.5 V/µs Typ
16.5.3 Absolute Maximum Ratings
Page 58
16.5.4 Pinning
16.6 PI5V330
16.6.1 General Description
Pericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the
Company.s advanced CMOS low-power technology, achieving industry leading
performance. The PI5V330 is a true bidirectional Quad 2-channel
multiplexer/demultiplexer that is recommended for both RGB and composite video
switching applications. The VideoSwitch. can be driven from a current output RAMDAC or
voltage output composite video source. Low ON-resistance and wide bandwidth make it
ideal for video and other applications. Also this device has exceptionally high current
capability which is far greater than most analog switches offered today. A single 5V
supply is all that is required for operation. The PI5V330 offers a high-performance, lowcost solution to switch between video sources. The application section describes the
PI5V330 replacing the HC4053 multiplier and buffer/amplifier.
16.6.2 Features
High-performance, low-cost solution to switch between video sources
Wide bandwidth: 200 MHz
Low ON-resistance: 3Ω
Low crosstalk at 10 MHz: .58 dB
Ultra-low quiescent power (0.1 µA typical)
Single supply operation: +5.0V
Fast switching: 10 ns
High-current output: 100 mA
Packages available:
16-pin 300-mil wide plastic SOIC (S)
16-pin 150-mil wide plastic SOIC (W)
16-pin 150-mil wide plastic QSOP (Q)
16.6.3 Absolute Maximum Ratings
Page 59
16.6.4 Pinning
16.7 AZC099-04S
16.7.1 General Description
AZC099-04S is a high performance and low cost design which includes surge rated diode
arrays to protect high speed data interfaces. The AZC099-04S family has been
specifically designed to protect sensitive components, which are connected to data and
transmission lines, from over-voltage caused by Electrostatic Discharging (ESD),
Electrical Fast Transients (EFT), and Lightning.
AZC099-04S is a unique design which includes surge rated, low capacitance steering
diodes and a unique design of clamping cell which is an equivalent TVS diode in a single
package. During transient conditions, the steering diodes direct the transient to either the
power supply line or to the ground line. The internal unique design of clamping cell
prevents over-voltage on the power line, protecting any downstream components.
AZC099-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2,
Level 4 (± 15kV air, ±8kV contact discharge).
16.7.2 Features
ESD Protect for 4 high-speed I/O channels
Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air),
±8kV (contact) IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O, 40A for Power
IEC 61000-4-5 (Lightning) 4A (8/20
5V operating voltage Low capacitance : 1.0pF typical
Fast turn-on and Low clamping voltage
Array of surge rated diodes with internal equivalent TVS diode
Small package saves board space
Solid-state silicon-avalanche and active circuit triggering technology
μs)
Page 60
16.7.3 Absolute Maximum Ratings
16.7.4 Pinning
16.8 TDA1308
16.8.1 General Description
The TDA1308; TDA1308A is an integrated class-AB stereo headphone driver contained in
an SO8, DIP8 or a TSSOP8 plastic package. The TDA1308AUK is available in an 8 bump
wafer level chip-size package (WLCSP8). The device is fabricated in a 1 mm
Complementary Metal Oxide Semiconductor (CMOS) process and has been primarily
developed for portable digital audio applications. The difference between the TDA1308
and the TDA1308A is that the TDA1308A can be used at low supply voltages.
16.8.2 Features
Wide temperature range
No switch ON/OFF clicks
Excellent power supply ripple rejection
Low power consumption
Short-circuit resistant
High performance
High signal-to-noise ratio
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High slew rate
Low distortion
Large output voltage swing
16.8.3 Absolute Maximum Ratings
16.8.4 Pinning
16.9 LM358D
16.9.1 General Description
The LM158 series consists of two independent, high gain, internally frequency
compensated operational amplifiers which were designed specifically to operate from a
single power supply over a wide range of voltages. Operation from split power supplies is
also possible and the low power supply current drain is independent of the magnitude of
the power supply voltage. Application areas include transducer amplifiers, dc gain blocks
and all the conventional op amp circuits which now can be more easily implemented in
single power supply systems. For example, the LM158 series can be directly operated off
of the standard +5V power supply voltage which is used in digital systems and will easily
provide the required interface electronics without requiring the additional ±15V power
supplies. The LM358 and LM2904 are available in a chip sized package (8-Bump micro
SMD) using National’s micro SMD package technology.
16.9.2 Features
Available in 8-Bump micro SMD chip sized package,
Internally frequency compensated for unity gain
Large dc voltage gain: 100 dB
Wide bandwidth (unity gain): 1 MHz (temperature compensated)
Wide power supply: Single supply: 3V to 32V or dual supplies: ±1.5V to ±16V
Page 62
Low supply current drain (500 µA)—essentially independent of supply voltage
Low input offset voltage: 2 mV
Input common-mode voltage range includes ground
Differential input voltage range equal to the power supply voltage
Large output voltage swing
16.9.3 Absolute Maximum Ratings
16.9.4 Pinning
16.10 74LCX244
16.10.1 General Description
The LCX244 contains eight non-inverting buffers with 3-STATE outputs. The device may
be employed as a memory address driver, clock driver and bus-oriented
Page 63
transmitter/receiver. The LCX244 is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal environment. The LCX244 is
fabricated with an advanced CMOS technology to achieve high speed operation while
maintaining CMOS low power dissipation.
16.10.2 Features
5V tolerant inputs and outputs
2.3V to 3.6V VCC specifications provided
6.5ns Tpd max. (VCC=3.3V), 10µA ICCmax.
Power down high impedance inputs and outputs
Supports live insertion/withdrawal
±24mA output drive (VCC=3.0V)
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500mA
ESD performance:Human body model>2000V, Machine model>200V
Leadless DQFN package
16.10.3 Absolute Maximum Ratings
Page 64
16.10.4 Pinning
16.11 74LCX245
16.11.1 General Description
The LCX245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and
is intended for bus oriented applications. The device is designed for low voltage (2.5V and
3.3V) VCC applications with capability of interfacing to a 5V signal environment. The T/R
input determines the direction of data flow through the device. The OE input disables both
the A and B ports by placing them in a high impedance state.
The LCX245 is fabricated with an advanced CMOS technology to achieve high speed
operation while maintaining CMOS low power dissipation.
16.11.2 Features
5V tolerant inputs and outputs
2.3V to 3.6V VCC specifications provided
7.0ns tPDmax. (VCC=3.3V), 10µA ICCmax.
Power down high impedance inputs and outputs
Supports live insertion/withdrawal
±24mA output drive (VCC=3.0V)
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds 500mA
ESD performance: Human body model>2000V, Machine model>200V
Leadless DQFN package
Page 65
16.11.3 Absolute Maximum Ratings
16.11.4 Pinning
16.12 FSA3157
16.12.1 General Description
The NC7SB3157 / FSA3157 is a high-performance, single- pole / double-throw (SPDT)
analog switch or 2:1 multiplexer/ de-multiplexer bus switch. The device is fabricated with
advanced sub-micron CMOS technology to achieve high-speed enable and disable times
and low on resistance. The break-beforemake select circuitry prevents disruption of
signals on the B Port due to both switches temporarily being enabled during select pin
Page 66
switching. The device is specified to operate over the 1.65 to 5.5V VCC operating range.
The control input tolerates voltages up to 5.5V, independent of the VCC operating range.
16.12.2 Features
Useful in both analog and digital applications
Space-saving, SC70 6-lead surface mount package
Ultra-small, MicroPak™ Pb-free leadless package
Low On Resistance: <10Ω on typical at 3.3V VCC
Broad VCC operating range: 1.65V to 5.5V
Rail-to-rail signal handling
Power-down, high-impedance control input
Over-voltage tolerance of control input to 7.0V
Break-before-make enable circuitry
250 MHz, 3dB bandwidth
16.12.3 Absolute Maximum Ratings
16.12.4 Pinning
Page 67
16.13 TSH343
16.13.1 General Description
The TSH343 is a triple single-supply video buffer featuring an internal gain of 6dB and a
large bandwidth of 280MHz. The main advantage of this circuit is that its input DC level
shifter allows for video signals on 75
tip of the video signal, while using a single 5V power supply with no input capacitor. The
DC level shifter is internally fixed and optimized to keep the output video signals between
low and high output rails in the best position for the greatest linearity. Chapter 4 of this
datasheet gives technical support when using the TSH343 as Y-Pb-Pr driver for video
DAC output on a video line (see TSH344 for RGB signals). The TSH343 is available in
the compact SO8 plastic package for optimum space-saving.
Ω video lines without damage to the synchronization
16.13.2 Features
Bandwidth: 280MHz
5V single-supply operation
Internal input DC level shifter
No input capacitor required
Internal gain of 6dB for a matching between 3 channels
AC or DC output-coupled
Very low harmonic distortion
Slew rate: 780V/μs
Specified for 150Ω and 100Ω loads
Tested on 5V power supply
Data min. and max. are tested during production
16.13.3 Absolute Maximum Ratings
Page 68
16.13.4 Pinning
16.14 MT48LC4M16A2TG8E
16.14.1 General Description
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of
the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits.
Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8
bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
ollowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0-A11 select the row).
16.14.2 Features
PC66-, PC100- and PC133-compliant
143 MHz, graphical 4 Meg x 16 option
Fully synchronous; all signals registered on positive edge of system clock
Internal pipelined operation; column address can be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and AutO Refresh
Modes
Self Refresh Modes: standard and low power
64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
Page 69
16.14.3 Absolute Maximum Ratings
16.14.4 Pinning
Page 70
16.15 MP1583
16.15.1 General Description
The MP1583 is a step-down regulator with a built in internal Power MOSFET. It achieves
3A continuous output current over a wide input supply range with excellent load and line
regulation.
Current mode operation provides fast transient response and eases loop stabilization.
Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.
Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown mode
the regulator draws 20µA of supply current.
The MP1583 requires a minimum number of readily available external components to
complete a 3A step down DC to DC converter solution.
16.15.2 Features
3A Output Current
Programmable Soft-Start
100mΩ Internal Power MOSFET Switch
Stable with Low ESR Output Ceramic Capacitors
Up to 95% Efficiency
20µA Shutdown Mode
Fixed 385KHz frequency
Thermal Shutdown
Cycle-by-Cycle Over Current Protection
Wide 4.75 to 23V operating Input Range
Output Adjustable From 1.22 to 21V
Under Voltage Lockout
Available in 8 pin SOIC Package
3A Evaluation Board Available
16.15.3 Absolute Maximum Ratings
Page 71
16.15.4 Pinning
16.16 MP2112
16.16.1 General Description
The MP2112 is a 1MHz constant frequency, current mode, PWM step-down converter.
The device integrates a main switch and a synchronous rectifier for high efficiency without
an external Schottky diode. It is ideal for powering portable equipment that powered by a
single cell Lithium-Ion (Li+) battery. The MP2112 can supply 1A of load current from a
2.5V to 6V input voltage. The output voltage can be regulated as low as 0.6V. The
MP2112 can also run at 100% duty cycle for low dropout applications.
The MP2112 is available in a space-saving 6-pin QFN package.
16.16.2 Features
High Efficiency: Up to 95%
1MHz Constant Switching Frequency
1A Available Load Current
2.5V to 6V Input Voltage Range
Output Voltage as Low as 0.6V
100% Duty Cycle in Dropout
Current Mode Control
Short Circuit Protection
Thermal Fault Protection
<0.1µA Shutdown Current
Space Saving 3mm x 3mm QFN6 Package
Page 72
16.16.3 Absolute Maximum Ratings
16.16.4 Pinning
16.17 MAX809LTR
16.17.1 General Description
The MAX809 and MAX810 are cost-effective system supervisor circuits designed to
monitor VCC in digital systems and provide a reset signal to the host processor when
necessary. No external components are required. The reset output is driven active within
~200msec of VCC falling through the reset voltage threshold. Reset is maintained active
for a timeout period which is trimmed by the factory after VCC rises above the reset
threshold. The MAX810 has an active-high RESET output while the MAX809 has an
active-low RESET output. Both devices are available in SOT-23 and SC-70 packages.
The MAX809/810 are optimized to reject fast transient glitches on the VCC line. Low
supply current of 0.5 A (VCC = 3.2 V) makes these devices suitable for battery powered
applications.
16.17.2 Features
Precision VCC Monitor for 1.5 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies
Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps
Four Guaranteed Minimum Power-On Reset Pulse Width Available (1 ms, 20 ms,
100 ms, and 140 ms)
RESET Output Guaranteed to VCC = 1.0 V.
Low Supply Current
Compatible with Hot Plug Applications
VCC Transient Immunity
No External Components
Wide Operating Temperature: -40°C to 105°C
Pb-Free Packages are Available
Page 73
16.17.3 Absolute Maximum Ratings
16.17.4 Pinning
Page 74
17SERVICE MENU SETTINGS
In order to reach service menu, First Press “MENU” Then press the remote control code,
which is
“4725”.
“4725”. In DTV mode, first press “MENU” and select “TV SETUP”. Then, press
17.1 Video Setup
Panel Info <..................................>
32_LC_SAC1
Blue Background <.....>
If “Menu” selected, “Blue Background” item is seen in “Feature”
menu.
If “Yes” selected,
“Feature” menu
Film Mode <.....>
If “Yes” selected, “Film Mode” feature is active.
Dynamic Contrast <.....>
If “Yes” selected, “Dynamic Contrast” feature is active.
Game Mode <...........>
If “Yes” selected, “Game Mode” feature is active
SRGB For PC <...........>
If “Yes” selected, PCs can use SRGB option.
Dynamic Noise Reduction<...........>
If “Yes” selected, “Dynamic Noise Reduction” feature is active
WSS Option<...........>
If “Yes” selected, WSS Option can be used
“Blue Background” is on and not seen in
17.2 AudioSetup
BG<.....>
Europe
New Zelland
Australia
No
DK<.....>
I<.....>
L<.....>
Equalizer <.....>
If “Yes” selected, “Equalizer” item is seen in “Sound” menu.
Headphone <.....>
If “Yes” selected, “Headphone” item is seen in “Sound” menu.
Power On/Off Melody <.....>
If “Yes” selected, when power on/off conditions, the power on/off
melody can be heard.
Dynamic Bass <.....>Value between 0 to 12
Effect<.....> Value between 0 to 7
Audio Delay ,offset <.....> Value between 0 to 190
Audio Setup Cont...2
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Carrier mute<.......> Value between 0 to 28
Headphone Sound Select <.......>
Always Active Select
Always Inactive Select
Menu
Always Main Menu
Always PIP/PAP Window
Sound Mode Detect Time <.......>
Noise Reduction Threshold <.......> Value between 0 to 255
Noise Reduction Time <.......> Value between 0 to 15
AVL Attack Time <.......> Value between 0 to 255
AVL Release Time <.......> Value between 0 to 255
Prescales ( AVL On)
FM Prescale<.......>
AM Prescale <.......> Value between 0 to 255
NICAM Prescale <.......> Value between 0 to 255
SCART Prescale <.......> Value between 0 to 255
FAV Prescale <.......> Value between 0 to 255
DTV Prescale <.......> Value between 0 to 255
HDMI Prescale <.......> Value between 0 to 255
YPbPr/PC Prescale <.......> Value between 0 to 255
An. USB Prescale <.......> Value between 0 to 255
Dig. USB Prescale <.......> Value between 0 to 255
Prescales ( AVL Off)
FM Prescale<.......>
AM Prescale <.......> Value between 0 to 255
NICAM Prescale <.......> Value between 0 to 255
SCART Prescale <.......> Value between 0 to 255
FAV Prescale <.......> Value between 0 to 255
DTV Prescale <.......> Value between 0 to 255
HDMI Prescale <.......> Value between 0 to 255
YPbPr/PC Prescale <.......> Value between 0 to 255
An. USB Prescale <.......> Value between 0 to 255
Dig. USB Prescale <.......> Value between 0 to 255
Clipping Levels ( AVL On)
FM Clipping <.......>
AM Clipping <.......> Value between 0 to 255
NICAM Clipping <.......> Value between 0 to 255
SCART Clipping <.......> Value between 0 to 255
FAV Clipping <.......> Value between 0 to 255
DTV Clipping <.......> Value between 0 to 255
HDMI Clipping <.......> Value between 0 to 255
YPbPr/PC Clipping <.......> Value between 0 to 255
An. USB Clipping <.......> Value between 0 to 255
Dig. USB Clipping <.......> Value between 0 to 255
Clipping Levels ( AVL Off)
FM Clipping <.......>
AM Clipping <.......> Value between 0 to 255
NICAM Clipping <.......> Value between 0 to 255
Value between 0 to 255
Value between 0 to 255
Value between 0 to 255
Value between 0 to 255
Value between 0 to 255
Page 76
SCART Clipping <.......> Value between 0 to 255
FAV Clipping <.......> Value between 0 to 255
DTV Clipping <.......> Value between 0 to 255
HDMI Clipping <.......> Value between 0 to 255
YPbPr/PC Clipping <.......> Value between 0 to 255
An. USB Clipping <.......> Value between 0 to 255
Dig. USB Clipping <.......> Value between 0 to 255
17.3 Service Scan/Tuning Setup
First Search for L/L’ <.......>
ATS Delay Time (ms) <.......>
Main Tuner Setup
Tuner Type
LC_TDTC_GXX1D
Thomson DTT7543X
Philips TD1318AF-3
Samsung DTOs403LH172A
Generic ( Analog Only)
Control Byte <.......>
BSW1 <.......> Value between 0 to +255
BSW2 <.......> Value between 0 to +255
BSW3 <.......> Value between 0 to +255
Low-Mid – Low Byte <.......>
Low-Mid – High Byte <.......>
Mid-High – Low Byte <.......>
Mid-High – High Byte <.......>
S Band TOP <.......>
VIF TOP <.......>
VIF TOP SECAM <.......> Value between 0 to +15
VIF TOP DK<.......> Value between 0 to +15
Synch Threshold<.......> Value between 0 to +40
Value between 0 to +15
Value between 0 to +200
Value between 0 to +255
17.4 Options
Options-1
Power Up
Standby
Last state
TV Open Mode
Source
1st TV
Last Tv
First APS <.......>
APS Volume <.......> Value between 0 to +63
Burn In Mode <.......>
APS Test
If “Yes” selected, first time TV opens by asking APS.
If “Yes” selected, TV opens with Burn-In mode. This mode is
used in manufacturing.
Page 77
Autostore <.......>
Unicode Enabled <.......>
Files.
Options-2
Source List menu <.......>
press “source” button.
RC Select <.......>
RC Group 1
RC Group 2
RC Group 3
RC Group 4
RC Group 5
RC Group 6
Double Digit Key <.......>
Protection <.......>
Led Type <.......>
1 Led 1 Color
1 Led 2 Color
2 Led 2 Color
1 Led 3 Color
2 Led 3 Color
200 Programme <.......>
If “Yes” selected, totaly 200 programmes can be used.
TouchPad <.......>
If “Yes” selected, TouchPad can be used.
Teletext Options
TXT Darkness <.......>
TXT Type <.......>
Fasttext&Toptext
No
Default
Fastext
Toptext
TXT Language <.......>
Menu
West
East
Cyrillic
Turk/Gre
Arabic
Persian
Auto
No Txt Warning <.......>
If “Yes” selected, Channel is automatically stored.
If “Yes” selected,Unicode characters can be read in the USB
If “Yes” selected, Sorce List Menu appears on the screen when
If “Yes” selected, Double Digit Button on RC activates.
If “Yes” selected,short circuit protection activates.
Value between 0 to +63
Page 78
Txt Subtitle <.......>
Optional Features
Default Zoom <.......>
Menu
16:9
4:3
Panaromic
14:9 Zoom
Menu Timeout <.......>
Menu
15 Sec
30 Sec
60 Sec
No Time
Backlight <.......>
100 Step Slider <.......>
Analog USB Enabled <.......>
Menu Double Size <.......>
CEC Enable <.......>
Digital USB Hotplug <.......>
If “Yes” selected, “No Txt Transmission” warning appears on
the screen when pressing txt button from RC.
If “Yes” selected, Teletext subtitles can be seen.
If “Yes” selected, “Backlight” feature is active.
If “Yes” selected, 64 step sliders will become 100 step sliders.
If “Yes” selected, “Analog USB” option is active.
If “Yes” selected, menu sizes increases.
If “Yes” selected, “CEC” feature is active.
If “Yes” selected, “Digital USB Hotplug” feature is active.
PIP Options
Pip <......>
AV PIP
No PIP
PC PIP
Hotel Options <......>
Hotel TV <......>
If “Yes” selected, “Hotel TV” feature is active.
IR Smartloader <......>
If “Yes” selected, “IR Smartloader” feature is active.
17.5 External Source Settings
TV <.......>
DTV <.......>
Ext 2 <.......>
Ext 2 S <.......>
FAV <.......>
BAV <.......>
Page 79
S-Video <.......>
HDMI 1 <.......>
HDMI 2 <.......>
HDMI 3 <.......>
HDMI 4 <.......>
YPbPr <.......>
PC <.......>
17.6 Preset
User Ad.j
ADC Adj.
Service Adj.
All Adj.
Init Factory Channels.
17.7 NVM Edit
NVM-edit addr. (hex)
NVM-edit data (hex)
NVM-data dec
17.8 Programming
HDMI DDC Update Mode <.......>
HDCP Key Update Mode <.......>
Software Bypass <.......>
If “On” selected, speaker effects are bypassed.
LVDS Clock Step <.......> Value between 0 to +255
Memory Clock Step <.......> Value between 0 to +255
DTV Download <.......>
If “On” selected, DTV software can be updated from SCART.
DSUB9 Download <.......>
If “On” selected, DTV software can be updated from DSUB9.
17.9 Diagnostic
Eeprom I2C
Tuner I2C
IF I2C
HDMI I2C
17.10 Product Info
Page 80
18 SOFTWARE UPDATE DESCRIPTION
16.1 17MB37 Analog Part Software Update With Bootloader Procedure
1.1 The File Types Used By The Bootloader
All file types that used by the bootloader software are listed below:
1. The Binary File : It has “.bin” extension and it is the tv application. Its size is 1920 Kb.
2. The Config Binary File : It has “.cin extension and it is the config of the tv application.
Its size may be 64 Kb or a few times 64 Kb.
3. The Test Script File : It has “.txt” extension and it is the test script that is parsed and
executed by the bootloader. It don’t have to be any times of 64 Kb.
4. The Test Binary File : It has “.tin” extension and it is used and written by the test
groups. It is run to understand the problem part of the hardware.
Alltough a file that is used by the bootloader can be had any one of these extensions, its
name has to be “VESTEL_S” and it has to be located in the root directory of the usb
device.
1.2 Usage of The Bootloader
1. The starting to pass through : The chassis is only powered up.
2. The starting to download something : When chassis is powered up the menu key has to
be pushed.Before the chassis is powered up and if any usb device is plugged to the usb
port, the programme is downloaded from usb firstly.
Any usb device is plugged to usb port , user must open hyperterminal in the pc and
connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c connectors.
Serial connection settings are listed below:
- Bit per second: 115200
- Data bits: 8
- Parity: None
- Stop bits: 1
- Flow control: None
In this case the bootloader sofware puts “C” character to uart. After repeating “C”
characters are seen in the hyperterminal user can send any file to chassis by selecting
Transfer -> Send File menu item and choosing “
1K Xmodem” from protocol section.
Page 81
Figure 1. The Sample Output Before Sending The File
2. EEProm update
To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.
Serial connection settings are listed below:
- Bit per second: 9600
- Data bits: 8
- Parity: None
- Stop bits: 1
- Flow control: None
Programming menu item is choosed in the service menu and switch “HDCP Key Update
Mode” from off to on.
Page 82
Figure 2. The Programming Service Menu
After then you must see Xmodem menu in the hyperterminal.To download hdcp key press
k or to download eeprom content press w.
Figure 3. Xmodem Menu
If the repeated “C” characters are seen you can transfer file content via select Transfer>Send File and choose “
Xmodem” protocol and click the “Send” button.
Page 83
Figure 4. The Starting To Send
16.2 17MB37 HDCP key upload procedure.
1) Turn on TV set.
2) Open a COM connection using fallowing parameters and select ISP COM Port No
Baud Rate: 9600 bps
Data Bits: 8
Stop Bits: 1
Parity: None
Flow Control: None
3) Enter service menu by pressing “4” “7” “2” 5” consecutively while main menu is
open
4) Select “9. Programming”
5) Select “HDMI HDCP Update Mode” yes.
6) On Hyper Terminal Window press “k”
7) Click on send file under Transfer Tab.
8) Select Xmodem and choose the HDCP key to be uploaded.
9) Press send button
10)Restart TV set
Page 84
16.3 17MB37 Digital Software Update From SCART
Adjusting DTV Download Mode:
1. Power on the TV.
2. Exit the Stby Mode.
3. Enter the “Tv Menu”.
4. Enter “4725” for jumping to “Service Settings”.
5. Select “8. Programming” step.
6. Change “6. DTV Download” to “On”.
7. Switch to the Stby mode.
Adjusting HyperTerminal:
1. Connect the “MB37 SCART Interface” to SCART1 (bottom SCART plug).
2. Also connect the “MB37 SCART Interface” to PC.
3. Open “HyperTerminal”.
4. Determine the “COM” settings listed and showed below.
Bit per second: 115200
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None
COM Properties Window
Page 85
6. Click “OK”.
Software Updating Procedure
1. In the HyperTerminal Menu, click the “Connect” button.
2. Exit the Stby Mode.
3. The “Space” button on the keyboard must be pressed, when the following window can
be seen.
Selection Window
4. Press the “2” button on the keyboard for choosing “2. Upgrade Application with
Xmodem”.
5. Repeating “C” characters are seen in the “HyperTerminal” menu.
Page 86
The Sample Output Before Sending The File
6. Click the “Send” button on the HyperTerminal
7. Select the “Filename
xxxx_slot1.img” using “Browse”.
8. Choose the “1K Xmodem” from “Protocol” option.
Selection of File
File and Protocol Selection Window
Note: In the Software updating Procedure section, when the first “C” character is seen,
the filename selection process must be finished before 10 seconds. If the process can not
be finished, the file sending operation will be cancelled. The following figure shows this
situation.
Page 87
Capture of Receving Data Failing
9. When sending the file the following window must be seen.
Capture of Sending Process
10. After the sending process the following HyperTerminal window must be seen.
Page 88
Capture of End of The Sending Process
11. For sending second program file, the Software Updating Procedure must be repeated
from the step
X. Select the “Filename xxxx_slot2.img” using “Browse”.
12. After sending the second program file, the Software Updating Procedure will be
succesful.
Note: After the File Sending Process,
1. Upgrade Application with FUM
2. Upgrade Application with Xmodem, options must be seen.
End of The Sending Process
Page 89
Checking Of The New Software
1. Turn off and on the TV.
2. Enter the “Setup” submenu in the “DTV Menu”.
3. Choose the “Configuration” option.
4. For controlling new software, check the “Receiver Upgrade” option.
16.4 17MB37 Digital Software Update From USB
Software upgrade is possible via USB disk by folowing the steps below.
1. Copy the bin file, including higher version than the software loaded in flash, into the
USB flash memory root directory. This file should be named up.bin.
2. Insert the USB disk.
3. Digital module performs version and CRC check. If version and CRC check is
successful, then a message prompt appears to notify user about new version. If the
user confirms loading of new version, upgrade.bin file is written into flash unused
slot.
4. Digital module disables the previous software in the flash and then a system reset
is performed.
5. After the reset, digital module starts with new software.
Revert operation:
With revert operation, it is possible to downgrade the software.
Revert operation is very similar to upgrade process. In the revert operation, file name
should be f_up.bin. Also user confirmation is not asked.
1. Copy the bin file into the USB flash memory root directory. This file should be
named force_upgrade.bin.
2. Insert the USB disk.
3. A lower version than the software in flash can be loaded with revert operation.
Digital module performs only CRC check. If CRC check is successful, then
force_upgrade.bin file is written into flash unused slot.
4. Digital module disables the previous software in the flash.
5. A message prompt is displayed to notify user about end of revert process.
6. Power off/on is required to start digital module with the new software.
For controlling new software, check the “Receiver Upgrade” option.
Page 90
I2C_5V
I2C_TUN_DVB
74HCT4053
I2C & AGC
SWITCH
RF_AGC_DVB
RF_AGC_A
DVB-T COFDM
DEMOD.
STV0362
TS_T
TS_CI
RJ45
ETHERNET PHY
STE101P
BUFFERS
74LCX244
CI_BUFFERS
19 BLOCK DIAGRAMS
19.1 General Block Diagram
I2C
THOMSON
DTT75430
LG
TDTC-GXX1D
SAW
K9656M
SCART
ON/OFF
TRANSISTOR
SWITCH
I2C2/UART
RF AGC
ANALOG IF
K3958M
SAW
IF AGC
DIGITAL IF
DVB-C QAM
DEMOD.
STV0297
FSA3157
IF AGC
SWITCH
IF AGC_C
IF AGC_T
This Block does not exist,
unless PCB has enough
space
TS_C
USB HUB
USB2503
I2C_5V
DDC
TMDS DATA/CLK
MPEG4
DECODER
STi7101
I2C LEVEL
SHIFTER CIRCUIT
VIF_TUNER
SIF_TUNER
SC1 CVBS
SC1 RGB/FB
SC1 AUD_IN
SC1_CVBS_OUT
SC1_AUD_OUT
EDID
E2PROM
24C02
UART
SPDIF
I2C
2xFLASH
NOR 64Mbit (common)
NAND 2Gbit (w/ethernet)
4xDDR1
16Mx16
YPbPr
SCL/SDA
HDMI1
HDMI2
DDC
TMDS DATA/CLK
Y/C
SVHS
14.3181MHz
XTAL
RESET IC
MAX809LTR
CVBS
AUDIO L/R
FAV_Video/Audio
EEPROM
24C32
SCL/SDA2
MST6Wx7
YPbPr
AUDIO L/R
VGA/YPbPr
1MB Serial
Flash
LINE OUT
LINE OUT L/R
2MB SD
RAM
TS_CI
I/O PORTS
DVD Y/C_IN
LVDS
CONNECTOR
VCC SW
PANEL_ VCC_ ON/OFF
I/O PORTS
+3V3_STBY
+1V2_STBY
+2V6
+3V3
MAIN SPEAKER
OUT L/R
HP OUT
L/R
+5V
HP
AMPLIFIER
TDA1308T
PT2333 or MP1720
PANEL
SUPPLY
PANEL
PANEL_VCC
KEYBOARD
+12V
AUDIO AMP.
2 x 2.5W
POP NOISE
MUTE
CIRCUIT
DETACHED HP
BACKLIGHT_ON/OFF
BACKLIGHT_DIMMING
POWER_ON/OFF
StBy M TV/AV +P -P +V -V
I/O PORTS
LED1
LED2
DDC_WP
PANEL_VCC_ON/OFF
POWER ON/OFF
SCART1 PIN8
MPEG DECODER IRQ
PROTECTION
NVM_WP
Main Speaker 4R
4 Layer PCB
VESTEL ELECTRONICS R&D
GROUP
17MB37 BLOCK DIAGRAM
DATE:03.03.2009
DRAWN BY: SADIK ŞEHİT
EDID
E2PROM
24C02
HDMI_1
HDMI1
TMDS DATA/CLOCK 2
HDMI_2
PI5V330
RGB Switch
IDTV/YPbPr_SW
IDTV_YPbPr/SOY
YPbPr
DDC
DVD AUDIO_IN
IR
“”
VGA
DVD
Connector
IR ON/OFF
+24V
+12V
+5V_STBY
+5V
POWER
MODULE
+3V3_STBY
+3V3
DVD_SENSE
DVD Power
Connector
+12V
Page 91
1 2 3 4 5 6 7 8
LG
AIF
A
DIF1
DIF2
IF_AGC
AS
NC
B2
SDA
SCL
TU102 TDTC-G101D
RF_AGC
B1
B
ANT_PWR
Samsung/Thomson
IFOUT-
IFOUT+
VT
IF_AGC
+5V
AIF_OUT
C
TU101
SDA
SCL
DTOS403LH172A
SAS
RF_AGC
BA
TUNER_PIN11
TUNER_PIN10
D
12
11
10
9
8
7
6
5
4
3
2
1
11
10
9
8
7
6
5
4
3
2
1
ANALOG_IF
TUNER_PIN11
TUNER_PIN10
IF_AGC_DVB_IN
ADDRESS_SEL_TUNER
5V_TUN
SDA_TUNER
SCL_TUNER
RF_AGC
33V_TUNER
ACT_ANT
21
21
1u
L116
C626
47p
33V_TUNER
IF_AGC_DVB_IN
5V_TUN
21
S308
SDA_TUNER
SCL_TUNER
RF_AGC
ADDRESS_SEL_TUNER
S104
ACT_ANT
C913
DIGITAL_IF-
1n
50V
C914
1n
50V
C1029
50V
2p2
DIGITAL_IF+
TUNER_PIN11
50V
TUNER_PIN10
ANALOG_IF
21
ACTIVE ANTENNA
OVER_CUR_DETECT
TP151
1
ACT_ANT
RF_AGC_A
SCL_TUNER
SDA_TUNER
5V_TUN
R502
10k
N.C.
R482
21
4R7
2R1
21
21
21
3
2
21
R504
10k
5V_TUN
21
10k
R501
1
T_AGC
R622
1k
BC848B
Q115
21
3
2
1
IF_AGC_DVB_IN
R503
10k
21
10V
100n
C136
ANT_CTRL
R505
1
2
10k
21
IF_AGC_DVB
TH101
21
330R
2 1
F234
Q102
FDN336P
C359
2
10u
1
10V
D121
1N4148
R111
12k
1
C448
47u
2
16V
This part must be placed near the tuner
R126
21
2
1
2
1
C586
47p
50V
C587
47p
50V
47R
R127
47R
SCL_TUN
21
SDA_TUN
5V_TUN
5V_TUN
TUNER SUPPLY OPSION
U123
LM1117
3 2
GND
OUTIN
VOUT
4
1
21
R408
1k
8V_VCC
F116
330R
21
1
C600
47u
2
16V
!!!En az 1.8 cm2 altta ve üstte soðutma alaný býrakýlmalý.
AGC AND I2C SWITCH PART
33V_TUNER
C532
1u
50V
SCL_TUN
SDA_TUN_DVB
SDA
R254
21
4k7
3
R595
2
1
22k
21
RF_AGC
10V
100n
C137
NEAR THE TUNER
1
2
SCL_TUN_DVB
SCL
RF_AGC_DVB
RF_AGC_A
U115
74HCT4053
1
2Y1
2
2Y0
3
3Y1
4
3Z
5
3Y0
6
E
7
VEE
GND S3
VCC
1Y1
1Y0
2Z
1Z
S1
S2
100n
5V_VCC
C128
21
10V
16
15
14
13
12
11
10
98
Q116
BC848B
330R
R460
330R
1K
2
1
5V_VCC
IDTV_SW
21
R624
2 1
S105
1k
SDA_TUN
2
1
C360
10u
10V
21
F159
330R
2
1
C134
100n
10V
21
C1158
220u
6V3
Near Tuner
supply pin
5V_TUN
A
5V_TUN
B
C
D
2
21
C129
100n
10V
C611
220u
1
6V3
21
C364
21
21
21
6k8
3k3
R473
R231
2
Q140
BSN20
Z101
IN1 OUT1
K9656M
IN2
OUT2
GND
3
Z102
IN1 OUT1
K3958M
IN2
2
GND
3
OUT2
41
5
SIFP
SIFM
VIFM
21
41
5
L104
2u2
N.C.
C546
21
C547
10n
16V
21
5V_TUN
6k8
R474
22k
R594
2 1
21
10n
16V
21
SIF_CTL
R483
1k2
2
OPTIONAL COIL
1u
1u
L101
2 1
2 1
21
3
Q144
BF799
1
21
10R
R384
L114
680R
2 1
R735
R125
47R
L111
1u
R1300
220R
21
1
2
C545
10n
16V
C520
47u
16V
21
R680
56R
21
21
R252
21
R623
4k7
1k
5V_TUN
E
ANALOG_IF
R38
220R
C135
100n
2
10V
1
R209
100k
BA782
2 1
D145
21
21
100k
R210
1
N.C.
2
3
WARNING!!! This part must be close to chip
C363
21
10u
10V
3V3_VCC
WARNING!!! Saw filter outputs must be close the chip
VIFP
C131
100n
5V_TUN
10V
10u
21
10V
21
C467
C132
21
100n
10V
21
3V3_STBY
3V3_VCC
F187
330R
F184
330R
C361
21
F186
330R
10u
10V
21
C510
2
100n
1
10V
4k7
R253
F185
330R
21
WARNING!!! This part must be close to chip
F
C636
2
220n
1
10V
10V
21
C130
21
10u
C597
220p
50V
10V
100n
SIFP
SIFM
VIFM
VIFP
21
C620
50V
U138
100p
MST6WB7GQ-3
62
AVDD_MPLL
63
VR27
64
VR12
65
AVDD_RXS
66
GND_RXS
67
SIFP
68
SIFM
69
VIFM
70
VIFP
71
GND_RXV
72
AVDD_RXV
73
TAGC
4
E
T_AGC
F
V-1 e gecerken yapilan updateler
Video SAW filitre cikislari caprazlandý
VESTEL
SCH NAME :
DRAWN BY :
ANALOG IF
SADIK SEHIT
PROJECT NAME :
17mb37
SHEET:
14-10-2009_09:09
87654321
OF:
A3
181
AX M
Page 92
1 2 3 4 5 6 7 8
5V_VCC
21
1
TP101
C138
2
100n
1
10V
1
2
3
VGA_VSNC
VGA_HSNC
50V
VGA_B
VGA_G
VGA_R
D104
5
4
NUP4004M5
TP284
21
50V
27p
C441
F216
2 1
600R
F211
600R
TP297
TP298
F212
600R
TP296
21
D185
C5V6
PROJECT NAME :
A/V INTERFACE
SADIK SEHIT
50V
27p
2 1
C442
75R
R637
75R
R638
R639
75R
C440
2 1
27p
50V
21
3
D146
BAV70
VGA_DDC_5V
A
1
1
TP104
TP103
1
TP102
8
7
6
5 4
A0
VCC
U112
A1
WP
ST24LC21
A2
SCL
GNDSDA
1
2
3
1
TP105
B
VGA INPUT
10V
5V_VCC33k
21
R683
21
R682
RCA_Y
33k
21
TP294
21
21
21
RCA_PR
TP293
RCA_PB
C365
10u
TP292
50V
1n
2 1
C473
21
50V
1n
2 1
C474
SAV_AUD_R_IN
SAV_AUD_L_IN
SAV_CVBS
50V
2 1
C113
220p
C
D
E
F
OF:
A3
182
AX M
17mb37
SHEET:
14-10-2009_09:10
87654321
220p
C103
TP356
SC1_R
TP355
TP351
TP354
TP360
TP352
50V
1n
C477
21
C475
1n
50V
50V
2 1
21
21
21
D112
2 1
C5V6
C106
21
220p
50V
TP346
D111
2 1
C5V6
47R
2 1
R128
R255
4k7
SC1_CVBS_OUT
SC1_FB
SC1_PIN8
21
C140
2 1
100n
10V
F198
21
21
SC1_AUD_L_IN
R219
21
100R
C484
1n
50V
600R
F197
600R
SC1_AUD_R_IN
SC1_AUD_R_OUT
IPOD INTERFACE
TP15
POP_MUTE
IPOD_Y_IN
TP8
R120
21
10k
D115
2 1
75R
2 1
R644
75k
2 1
R641
50V
220p
2 1
C107
75R
2 1
R643
C5V6
D117
2 1
C5V6
D116
2 1
PROG_EN
TX/SDA_SC
SC1_G
RX/SCL_SC
C5V6
SC1_AUD_L_OUT
21
TP18
CN141
12V_IPOD
12V_IPOD 12V_IPOD
21
43
65
87
109
1211
SPDIF_OUT_COAXIAL
5V_VCC
S_VIDEO_C_IN
S-VIDEO IN
SPDIF OUTPUT INTERFACE
12V_IPOD
TP16
TP9
1413
TP11 TP5
IPOD_R IPOD_L
TP22
MAIN_R MAIN_L
C1059
100n
2 1
10V
IPOD_GPIO2
IPOD_GPIO3
C1060
2 1
100n
10V
RX/SCL TX/SDA
DVD_IPOD_SW
DVD_Y_IN
IPOD_Y_IN
SW_Y_IN
IPOD_C_IN
SW_C_IN
TP24
TP19
TP17
R1250
21
47R
TP14 TP13
C1049
100n
21
10V
R1261
1k
2 1
S293
R1326
S277
DVD_C_IN
S292
R1328
S278
R1325
R1327
75R
75R
75R
75R
1615
1817
TP21
2019
2221
2423
IPOD_GPIO1
TP20
2625
2827
1
2
3
4
5
6
7
8
R1251
47R
U194
PI5V330
IN
S1A
S2A
DA
S1B
S2B
DB
GND
VCC
S1D
S2D
S1C
S2C
21
C1044
100n
EN
DD
DC
3029
21
21
21
21
SW_R_IN
2 1
10V
16
15
14
13
12
11
10
9
C1061
F293
600R
AMP_MUTE
IPOD_C_IN
2 1
21
TP2
5V_VCC
F118
330R
50V
220p
R400
1k
C229
100n
10V
100n
C1139
27p
2 1
21
21
10V
21
50V
5V_VCC
TP287
21
A
20
321
4
NUP4004M5
D106
21
5
C105
50V
220p
SC1_CVBS_IN
TP361
19
18
75R
17
R640
21
16
15
14
50V
220p
2 1
C104
13
12
B
SC101
C
SCART1
F207
2 1
600R
D
JK111
4
RED
3
2
WHT
1
11
SCART LT1
10
9
8
7
6
5
4
3
2
1
TP348
TP334
TP347
21
C5V6
D183
C5V6
21
F196
F204
600R
D184
F205
600R
21
600R
21
R596
22k
D140
2 1
C15V
SC1_B
50V
220p
2 1
TP358
TP359
C108
TP363TP357
TP336
C478
R217
100R
TP362
50V
1n
C488
21
TP335
F195
600R
21
LINE_R_OUT
1n
50V
21
F194
21
600R
R213
21
100R
C489
21
1n
R216
100R
50V
21
LINE_L_OUT
21
AUDIO LINE OUT
E
21
F215
600R
TP301
TP289
TP300
TP299
JK104
BLK
RED
WHT
6
5
4
3
2
1
F
TP302
50V
220p
C115
S217
F208
600R
F209
600R
21
SPDIF_OUT_COAXIAL
21
C479
21
C480
1n
50V
1n
50V
21
21
YPBPR_AUD_R_IN
YPBPR_AUD_L_IN
COAXIAL SPDIF OUTPUT
YPBPR/PC LINE INPUT
21
21
C366
21
C5V6
C111
5V_SPDIF
IR_IN
21
10k
R1236
10k
R1235
10k
R1238
10k
R1239
10k
R1229
10k
R1228
10k
R1231
10k
R1230
D172
C5V1
10V
10u
D113
Q117
BC848B
S192
21
21
21
21
21
21
21
JK102
4 3
5
3
1
21
5V_VCC
5V_VCC
S281
5V_VCC
21
2
S282
C1007
100n
10V
5V_SPDIF
TP282
21
4k7
R752
C602
21
100n
10V
4k7
R242
S276
S294
SW_L_IN
21
C5V6
21
10k
R1234
C1143
1u
6V3
10k
R1237
C1144
1u
6V3
R1232
C1141
R1233
C1142
D114
50V
CN143
10k
1u
6V3
10k
1u
6V3
TP291TP290
50V
220p
2 1
220p
12
11
10
9
8
7
6
5
4
3
2
1
21
21
21
21
2 1
R464
100R
C116
C112
S_VIDEO_Y_IN
21
SPDIF_OUT
C1090
220n
C1121
25V
C15V
D194
F289
TP7
600R
TP6
F290
21
600R
F288
TP1
600R
F291
TP12
600R
F292
TP10
600R
R1254
47R
TP4
C1113
R1286
22k
50V
1n
C1119
R1288
22k
50V
C1118
R1287
C1120
R1284
50V
1n
1n
22k
50V
1n
22k
50V
21
21
21
21
21
21
21
21
TP382
21
1
25V
10u
21
21
C1135
27p
C1136
50V
21
21
27p
50V
C1140
27p
50V
21
C1137
21
C1138
27p
21
220p
50V
27p
50V
2 1
C1075
DVD_AUD_L_IN
IPOD_L
DVD_AUD_R_IN
IPOD_R
!
FS1
4A/24VDC
TP3
21
21
21
21
75R
R1329
2 1
15
14
13
12
11
10
9
8
VGA_DDC_5V
TP304
7
6
5
4
VGA CONNECTOR
3
TP288
2
1
CN118
DVD CONNECTION
D187
C18V
21
12V_VCC
R1240
21
R1285
22k
DVD_C_IN
DVD_Y_IN
DVD_IR
DVD_AUD_L_IN
DVD_SPDIF
10k
21
DVD_AUD_R_IN
R1267
4k7
C1050
100n
2 1
10V
321
4
321
NUP4004M5
3V3_VCC
DVD_SENSE
21
NUP4004M5
2k2
2k2
R712
2 1
21
C439
5
D101
21
4
2 1
27p
D102
5
R711
50V
C437
TP305
TP303
21
10k
R506
27p
TP306
JK101
RED
BLU
GRN
YPBPR INPUT
TP295
JK106
RED
WHT
YLW
TP283
SIDE AV INPUT
VESTEL
SCH NAME :
DRAWN BY :
R349
50V
21
R507
100R
C438
6
5
4
3
2
1
6
5
4
3
2
1
10k
R511
8
7
6
5 4
21
21
21
10k
R584
100R
R1
R2
R3
R4
27p
321
Page 93
1 2 3 4 5 6 7 8
Place 75R termination resistors
close to Paulo reference GNDs
A
SW_C_IN 47R
SW_Y_IN
S_VIDEO_C_IN
B
SC1_CVBS_IN
SAV_CVBS
DVB_CVBS
C
75R
R651
R650
75R
R653
75R
R652
75R
R654
75R
R649
2 1
75R
R664
2 1
75R
R665
2 1
75R
21
21
21
21
21
SC1_B
SC1_G
R667
2 1
75R
R666
2 1
75R
SC1_R
D
SW_PB
R656
2 1
75R
SW_Y RCA_PB
R657
2 1
75R
R655
2 1
SW_PR RIN2P
75R
E
R659
2 1
VGA_B
VGA_G
F
VGA_R
75R
R658
2 1
75R
R660
2 1
75R
R143
R142
47R
R141
47R
R140
47R
R137
47R
R138
47R
R139
47R
R149
47R
R148
47R
R403
470R
R147
47R
R829
47R
R831
47R
R404
470R
R830
47R
47R
R145
R144
47R
47R
R146
R773
470R
U138
MST6WB7GQ-3
C150
100n
10V
C420
47n
16V
21
C425
47n
C416
47n
F119
330R
17
HSYNC1
18
VSYNC1
19
VCLAMP
20
REFP
21
REFM
21
22
BIN1P
23
SOGIN1
24
GIN1P
25
RIN1P
26
BIN0M
21
27
BIN0P
28
GIN0M
29
GIN0P
30
SOGIN0
31
RIN0P
32
AVDD_33_3
33
GND3
34
HSYNC0
35
VSYNC0
21
36
VSYNC2
37
BIN2P
38
SOGIN2
39
GIN2P
40
RIN2P
41
C1
42
Y1
43
C0
44
Y0
45
CVBS3
46
CVBS2
47
CVBS1
48
VCOM1
21
49
CVBS0
50
VCOM0
21
51
AVDD_33_4
52
CVBSOUT1
53
CVBSOUT0
54
GND4
AVDD_AU_1
2
AVDD_AU_2
LINE_IN_0L
LINE_IN_0R
LINE_IN_1L
LINE_IN_1R
LINE_IN_2L
LINE_IN_2R
LINE_IN_3L
LINE_IN_3R
LINE_IN_MONO
LINE_OUT_3L
LINE_OUT_3R
LINE_OUT_2L
LINE_OUT_2R
LINE_OUT_1L
LINE_OUT_1R
LINE_OUT_0L
LINE_OUT_0R
SCART VIDEO OUTPUT AMPLIFIERS
21
1
BC858B
R646
75R
Q146
21
R753
4k7
3
2
R620
300R
21
Q119
BC848B
21
21
R777
2
1
3
75R
Q154
2N7002
VGA_HSNC
16V
47n
21
21
C0
C432
C434
21
47n
47n
21
C423
C422
21
47n
C424
21
47n
C612
21
16V
16V
16V
16V
Y0
21
BIN1P
SOGIN1
GIN1P
21
C1
Y1S_VIDEO_Y_IN
21
RIN1P
BIN0P
GIN0P
CVBS1
21
RIN0P
SOGIN0
21
AVDD_33
1n
50V
C433
21
47n
C435
21
47n
C421
21
47n
C418
21
47n
16V
16V
16V
16V
CVBS2
21
CVBS3
21
BIN0P
21
GIN0P
21
C152
100n
10V
21
VGA_VSNC
C151
100n
10V
R133
47R
R134
47R
C143
100n
SC1_FB
BIN2P
SOGIN2
GIN2P
RIN2P
21
21
21
SOGIN0
10V
C1
Y1
C0
C419
47n
21
R687
16V
33k
Y0
C417
21
47n
C428
21
47n
C426
21
47n
C490
21
C427
21
47n
C429
47n
C431
47n
C491
21
C430
47n
16V
16V
16V
1n
50V
16V
16V
16V
1n
50V
16V
RIN0P
21
BIN2P
21
GIN2P
21
SOGIN2
21
AVDD_33
CVBS0_OUT
21
BIN1P
21
GIN1P
21
SOGIN1
21
RIN1P
21
CVBS3
CVBS2
CVBS1
R859
10k
C144
2 1
100n
10V
R351
100R
5V_VCC
SC1_CVBS_OUT
21
GAIN_SW1
AUVRM
AUVRP
AUVAG
AUCOM
21
R402
3
1
100R
GND5
470R
2 1
2
R221
21
R674
21
R467
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
39k
15k
C378
2 1
10u
10V
C148
2 1
100n
AVDD_AU
AVDD_AU
10V
10V
10u
2 1
C368
10V
10u
2 1
C369
C659
100n
16V
LINE_IN_0L
LINE_IN_0R
16V
10V
10u
2 1
C375
R739
C121
21
220p
50V
R678
82k
21
R692
2 1
33k
21
1
OUT1
2
IN1-
3
V+
IN1+
VSS IN2+
LINE_IN_1L
LINE_IN_1R
C149
S106
21
LINE_IN_2L
100n
10V
21
LINE_IN_2R
LINE_IN_3L
LINE_IN_3R LINE_IN_2L
R686
21
33k
SC1_AUD_R_OUT
C649
SC_1_R 20k
100n
U118
TL062
VDD
OUT2
IN2-
C631
100n
16V
F217
2 1
600R
8
7
6
54
V+
R691
C120
220p
50V
R677
82k
33k
21
8V_VCC
21
21
10V
10u
2 1
C374
R738
20k
SC1_AUD_L_OUT
C650
21
100n
16V
SC1_L
DSP_CH2_L
DSP_CH2_R
DSP_CH4_L
DSP_CH4_R
DSP_CH1_L
LINE_R_OUT
DSP_CH1_R
DSP_CH3_L
DSP_CH3_R
AVDD_AU
Pin79
C142
100n
10V
2
1
Pin74
10V
100n
C145
2
1
21
330R
F120
AVDD_AU DECOUPLING CAPACITORS
3V3_VCC
POP_MUTE
R751
3k3
LINE_OUT_R
V+
C646
100n
16V
AUDIO PREAMPLIFIERS
Place close to Paulo
C666
1u
16V
CVBS0_OUT
R522
10k
C367
21
100n
2 1
21
C662
16V
10u
10V
R690
10V
10u
2 1
C372
3
BC848B
2
Q121
1
R737
20k
33k
R685
21
33k
R684
R155
47R
50V
220p
21
C119
R676
82k
21
V+
21
8V_VCC
2 1
33k
21
8V_VCC
21
1
OUT1
U117
2
IN1-
TL062
3
IN1+
VSS IN2+
DSP_CH4_L
C630
100n
16V
VDD
OUT2
IN2-
DVB_PR
DVB_Y
R662
75R
DSP_CH2_R
F219
600R
R689
33k
8
7
6
54
21
21
C443
2 1
27p
50V
R661
75R
SW_PR
C444
2 1
27p
50V
R224
100R
21
V+
R153
47R
50V
220p
C118
R675
82k
DVB/YPBPR_SW
21
R228
100R
R229
100R
21
10V
10u
2 1
21
C371
BC848B
21
Q120
21
R736
20k
RCA_PR
RCA_Y
21
3
1
100n
2
C663
16V
R627
1k
LINE_L_OUT
R521
2 1
10k
3k3
2 1
R750
LINE_OUT_L
21
1
2
3
4
5
6
7
8
U129
PI5V330
IN
S1A
S2A
DA
S1B
S2B
DB
GND
SW_Y
21
C555
21
C554
2 1
2 1
10n
10n
C550
2 1
10n
16V
16V
16V
22k
R419
22k
R420
22k
R415
HP_LDSP_CH2_L
21
HP_R
21
LINE_OUT_L
21
Place close to Paulo
R225
DSP_CH4_R
AUDIO OUTPUT FILTERS
100R
21
C551
2 1
10n
16V
LINE_OUT_R 100R
22k
21
R416
VESTEL
SCH NAME :
DRAWN BY :
AUDIO INPUT VOLTAGE DIVISION AND DC BLOCK
Place close to PauloVIDEO TERMINATIONS AND DIFFERENTIAL TRACING
LINE_IN_0L
LINE_IN_0R
LINE_IN_1L
LINE_IN_1R
LINE_IN_2R
LINE_IN_3L
POP_MUTE
LINE_IN_3R
100n
16
VCC
15
S1D
S2D
S1C
S2C
EN
DD
DC
C1006
14
13
12
11
10
9
DSP_CH1_L
DSP_CH1_R
<DRAWING NAME HERE>
<YOUR NAME HERE>
C656
100n
16V
R513
21
10k
C655
100n
16V
R514
21
10k
C645
100n
16V
R515
21
10k
C644
100n
16V
R516
21
10k
C642
100n
16V
R517
21
10k
C643
100n
16V
R518
21
10k
C660
100n
16V
R519
21
10k
C661
100n
16V
R520
21
10k
10V
2 1
C147
10u
D167
F151
330R
10V
R227
100R
R226
100R
DSP_CH3_L
DSP_CH3_R
PROJECT NAME :
R607
21
22k
C493
21
1n
R606
50V
22k
21
C492
21
1n
R605
50V
22k
21
C495
21
1n
R603
50V
22k
21
C494
21
1n
R601
50V
22k
21
C497
21
1n
R600
50V
22k
21
C496
21
1n
R599
50V
22k
21
C498
21
1n
R598
50V
22k
21
C499
21
1n
50V
DVB/YPBPR SWITCH
C5V1
21
5V_VCC
DVB_PB
R663
2 1
75R
SW_PB
21
16V
2 1
C553
10n
21
16V
2 1
10n
C552
R223
21
100R
2 1
C549
R222
21
2 1
C548
17mb37
14-10-2009_09:10
SC1_AUD_L_IN
SC1_AUD_R_IN
SW_L_IN
SW_R_IN
YPBPR_AUD_L_IN
YPBPR_AUD_R_IN
SAV_AUD_L_IN
SAV_AUD_R_IN
27p
21
C445
R418
22k
22k
R417
16V
10n
16V
10n
SHEET:
87654321
MAIN_L
21
MAIN_R
21
SC1_L
22k
R414
SC_1_R
22k
R413
OF:
21
21
A3
A
B
C
D
E
F
183
AX M
Page 94
1 2 3 4 5 6 7 8
A
CN121
21
20
1
2
3
4
5
6
7
8
9
10
11
12
HDMI1
13
14
B
15
16
17
18
19
CEC
21
R491
47k
R492
C
D
CN122
21
20
1
2
3
4
5
6
E
F
7
8
HDMI2
9
10
11
12
13
14
15
16
17
18
19
CEC
HDMIA_5V
21
1k
R632
21
R493
47k
21
47k
HDMI Receiver In_B
R386
10R
R388
10R
2 1
R389
10R
R391
10R
R392
10R
10R
R396
21
47k
HDMI Receiver In_A
R10
10R
R15
10R
R13
10R
R18
10R
R12
10R
R14
10R
R9
10R
R8
10R
R17
10R
R16
10R
R11
10R
R494
R385
21
R387
21
R394
21
R390
21
21
R393
21
21
21
21
21
21
21
21
21
21
21
21
10R
10R
10R
10R
10R
21
21
21
21
HDMIB_2+
HDMIB_2HDMIB_1+
HDMIB_1HDMIB_0+
HDMIB_0HDMIB_C+
HDMIB_C-
HDMIB_SCL
HDMIB_SDA
HDMIB_5V
HDMIB_HPD
HDMIA_2+
HDMIA_2-
HDMIA_1+
HDMIA_1-
HDMIA_0+
HDMIA_0-
HDMIA_C+
HDMIA_C-
HDMIA_SCL
HDMIA_SDA
HDMIA_HPD
1
2
3
4
1
2
3
4
TP134
A0
U110
A1
24LC02
A2
VSS
A0
U193
A1
24LC02
A2
VSS
VCC
SCL
SDA
TP411
5V_VCC
1
WP
5V_VCC
VCC
WP
SCL
SDA
BAV70
D147
2 1
3
C153
2
100n
1
1
TP133
TP412
1
1
TP410
HDMIB_SCL
HDMIB_SDA
BAV70
D193
2 1
1
TP409
10V
3
C1069
2
100n
1
10V
HDMIA_SCL
HDMIA_SDA
TP106
8
1
7
6
5
1
TP132
1
8
7
6
5
21
4k7
HDMIB_5V
R257
HDMI_WP1
21
4k7
R1282
VDDP
AVDD_33
HDMIA_5V
HDMI_WP2
2
1
100n
10V
1
100n
10V
C156
C155
2
Pin6 Pin13 Pin285
C159
C158
2
F124
330R
2
1
21
100n
10V
2
1
100n
1
10V
C173
100n
10V
HDMIA_C-
HDMIA_C+
HDMIA_0-
HDMIA_0+
AVDD_33
HDMIA_HPD
Q179
BC848B
HDMIA_5V
21
1k
R1263
3
1
R1264
2
21
1k
AVDD_33
4k7
R1281
2 1
HDMIA_2-
HDMIA_2+
HDMIA_1-
HDMIA_1+
R412
390R
HDMIA_SDA
Pin236Pin216Pin196
C157
2
100n
1
10V
3V3_HDMI
HDMIB_C-
C154
100n
10V
HDMIA_SCL
21
VDDC
HDMIB_C+
2
1
C160
100n
10V
HDMIB_0-
AVDD_33
HDMIB_0+
HDMIB_1-
HDMIB_1+
AVDD_USB3V3_VCC
HDMIB_HPD
BC848B
Q123
HDMIB_5V
21
1k
R629
3
1
2
HDMIB_2-
HDMIB_2+
R630
21
1k
R258
2 1
HDMIB_SDA
HDMIB_SCL
4k7
1
RXACKN
2
RXACKP
3
GND1
4
RXA0N
5
RXA0P
6
AVDD_33_1
7
RXA1N
8
RXA1P
9
GND2
10
RXA2N
11
RXA2P
12
HPLUGA
13
AVDD_33_2
21
14
REXT
15
DDCDA_SDA
16
DDCDA_SCL
282
VDDC5
283
RXBCKN
284
RXBCKP
285
AVDD_33_5
286
RXB0N
287
RXB0P
288
GND
289
RXB1N
290
RXB1P
291
GND18
292
RXB2N
293
RXB2P
294
HPLUGB
295
DDCDB_SDA
296
DDCDB_SCL
3V3_HDMI
U138
MST6WB7GQ-3
USB20_REXT
1
AVDD_USB
USB20_DM
USB20_DP
USB_VBUS
USB_DM
USB_DP
USB_CID
GND11
VDDP2
GND12
VDDP3
ICLK
DI[0]
DI[1]
DI[2]
DI[3]
VDDP5
DI[4]
DI[5]
DI[6]
DI[7]
DI[8]
DI[9]
191
192
193
194
195
196
197
216
217
218
219
220
231
232
233
234
235
236
237
238
239
240
241
242
R119
21
910R
AVDD_USB
USB_DM_A
USB_DP_A
VDDP
VDDP
I2S_WS_DVB
I2S_CLK_DVB
I2S_DATA_DVB
VDDP
A
B
C
D
E
F
VESTEL
SCH NAME :
DRAWN BY :
HDMI&USB
SADIK SEHIT
PROJECT NAME :
17mb37
14-10-2009_09:10
87654321
SHEET:
OF:
A3
184
AX M
Page 95
1 2 3 4 5 6 7 8
R277
CN106
1
10
5V_STBY
LED1
LED2
3V3_STBY
3V3_STBY
9
8
7
6
5
4
3
2
2 1
4k7
R276
2 1
4k7
56
57
A
D130
2 1
C5V6
D149
2 1
C5V6
LED&VFD
5
4
3
2
CN119
1
S119
S118
21
R43
220R
B
R421
10k
3
2
21
1
Q130
BC848B
21
10k
R528
BC858B
LED2
3V3_STBY
5V_STBY
S117
S125
21
21
F225
21
600R
3
2
Q148
1
21
R382
220R
3
Q149
1
220R
KEYBOARD & TOUCHPAD
C
DVD_IR
BC848B
IR_IN
D
1
2
21
47k
R1330
Q178
R1269
2 1
3
4k7
21
N.C.
S299
4k7
R1268
2 1
3V3_VCC
BC858B
21
R381
21
21
2
IR_IN
21
10k
3V3_STBY
5V_STBY
C608
27p
50V
Q131
BC848B
R531
R552
2 1
2 1
F229
600R
2 1
2 1
21
3
2
1
MECH_SWITCH
R527
10k
21
R526
10k
D148
C5V6
F228
600R
F230
600R
R422
10k
3V3_STBY10k
21
VFD_CSB
3V3_STBY
VFD_CLK_STBY
21
3V3_STBY
21
LED1
MECH_ONBOARD
D150
21
C5V6
F231
21
600R
VFD_DATA_STBY
STBY_ON/OFF_NOT
VDDP VDDC
C598
21
50V
CN114
C5V6
1
220p
D152
2 1
3
2
3V3_STBY
R608
22k
C177
100n
10V
2
1
2
C176
100n
10V
2
1
C175
100n
10V
2 1
2
1
PIN272 PIN226PIN108 PIN110
KEYBOARD_ONBOARD
R167
47R
21
F188
600R
F280
C1037
4
4u7
C1036
100n
VFD_CLK_STBY
VFD_DATA_STBY
21
4k7
R265
3
Q125
BC848B
1
C174
2
100n
1
10V
21
3V3_STBY
1
TP383
STBY_ON/OFF
C178
2
100n
1
10V
KEYBOARD_STBY
TK_SUPPLY
DVD_IR_ON/OFF
6
5
4
3
2
1
CN130
CN142
MECH_ONBOARD
21
43
KEYBOARD_ONBOARD
TK_SUPPLY
C447
21
27p
50V
X104
C446
21
27p
50V
DVB/YPBPR_SW
IDTV_SW
PROTECT
NVM_WP
VFD_CLK_STBY
HDMI_WP2
HDMI_WP1
VFD_DATA_STBY
HDMIB_5V
HDMIA_5V
PROTECT_PANEL
ANT_CTRL
VFD_CSB
DVD_IPOD_SW
IPOD_GPIO3
IPOD_GPIO2
21
21
1M
R110
14.31818MHZ
DVB_IRQ
3V3_STBY
3V3_STBY
3V3_VCC
3V3_STBY
3V3_STBY
SIF_CTL
STBY_ON/OFF_NOT
R748
21
47R
3V3_VCC
DVB_RESET
GAIN_SW1
3V3_VCC
3V3_VCC
3V3_VCC
3V3_VCC
DVD_IR_ON/OFF
R840
4k7
R858
3V3_STBY
3V3_VCC
R1266
2 1
4k7
2 1
2 1
4k7
R1277
3V3_STBY
R274
4k7
2 1
2 1
R269
2 1
4k7
R270
2 1
4k7
4k7
2 1
R271
2 1
2 1
R1278
4k7
R288
4k7
R268
4k7
R283
4k7
R264
4k7
21
R395
1k
USB_OCD
S193
R757
4k7
5V_TOLERANT
5V_TOLERANT
21
R8574k7
R267
21
2 1
4k7
PROG_EN
21
VDDP
VDDC
5V_TOLERANT
1k
5V_TOLERANT
58
59
60
61
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
149
150
151
152
153
154
155
156
157
158
159
U138
MST6WB7GQ-3
GPIOL[0] SAR0
GPIOL[1]
GPIOL[2]
GPIOL[3]
GPIOL[4]
XOUT
XIN
GPIOD[0]
GPIOD[1]
GPIOD[2]
GPIOD[3]
GPIOD[4]
GPIOD[5]
GPIOD[6]
GPIOD[7]
GPIOD[8]
GPIOD[9]
VDDP1
GND6
VDDC1
GPIOD[10]
GPIOD[11]
GPIOD[12]
GPIOD[13]
GPIOD[14]
GPIOD[15]
GPIOD[16]
GPIOD[17]
GPIOR[0]
GPIOR[1]
GPIOR[2]
GPIOR[3]
GPIOR[4]
3
SAR1
SAR2
SAR3
PWM0
PWM1
DDCR_SDA
DDCR_SCL
DDCA_SDA
DDCA_SCL
INT
IRIN
GPIOB[0]
GPIOB[1]
PWM2
PWM3
GND14
VDDP4
GPIOT[0]
GPIOT[1]
GPIOT[2]
GPIOT[3]
HWRESET
VDDP7
GND17
GPIOE[3]
GPIOE[2]
GPIOE[1]
GPIOE[0]
GPIOM[0]
GPIOM[1]
GPIOM[2]
GPIOM[3]
GPIOR[5]
GPIOR[6]
GPIOR[7]
GPIOR[8]
GPIOR[9]
GPIOR[10]
20455
205
206
207
208
209
210
211
212
213
214
215
221
222
223
224
225
226
227
228
229
230
243
272
273
274
275
276
277
278
279
280
281
PUSH V+ AND V- AT THE SAME TIME FOR MENU
N.C.
E
5V_STBY
RX/SCL
TX/SDA
S120
R164
47R
R163
47R
DEBUG SOCKET
PROG_EN
5V_STBY
CN145
21
1
2
21
3
21
4
3
SW5
1
21
R1332
4
2
270R
3
SW4
1
21
R1331
4
2
470R
3
SW1
1
21
R1289
4
2
1k2
3
SW6
1
21
R1333
VOL-TV/AVVOL+P-P+
4
2
2k7
3
SW3
1
21
R1305
3k9
STBY
4
3
4
SW2
2
1
2
5k1
R1292
C180
21
4k7
1
R280
2
Q128
BC848B
3
R282
2 1
4k7
F
4k7
R281
2 1
RX/SCL_SC
RX/SCL
UART_RXD
U127
M74HC4052
1
2Y0
2
2Y2
3
2Z
4
2Y3
5
2Y1
6
E
7
VEE
GND S1
VCC
1Y2
1Y1
1Y0
1Y3
16
15
14
13
1Z
12
11
10
S0
98
21
100n
10V
TX/SDA
TX/SDA_SC
UART_TXD
4k7
R284
5V_STBY
SW_UPDATE_SELECT
21
5V_STBY
PROG_EN
0
SW_UPDATE_SELECT
0
1
HC4052 DISABLE
HC4052 ENABLE1
DVB_SW_UPDATE
ANALOG_SW_UPDATE
KEYBOARD_ONBOARD
PDP_IRQ
BACKLIGHT_DIM
21
S196
S195
S194
21
21
MEGA_DCR
R232
4k7
C529
220p
50V
R1345
2
21
4k7
21
2
1
1
C1163
100n
10V
2
21
R745
3
1
1k
Q126
BC848B
S18
S121
21
3V3_VCC
21
5V_VCC
21
S123
21
1
Q147
2
BC858B
3
R352
21
100R
3
1
Q127
BC848B
R353
100R
R354
100R
R355
100R
21
21
21
21
10V
10u
C383
21
2
R233
4k7
C530
220p
50V
R234
4k7
C531
220p
50V
21
21
N.C.
4k7
2 1
R293
3V3_STBY
KEYBOARD_STBY
SC1_PIN8
DVD_SENSE
For Internal CPU Selection
R524
2 1
10k
R1280
2 1
4k7
For Internal CPU Selection
3V3_STBY
4k7
2 1
R287
4k7
2 1
R286
4k7
2 1
R289
4k7
2 1
R290
4k7
2 1
R294
4k7
2 1
R278
VDDP
OPTION2
R291
R161
47R
R162
47R
2 1
4k7
21
21
R292
2 1
4k7
VDDP
R1248
21
47R
4k7
R31
47R
21
21
HP_DETECT
R261
2 1
4k7
R262
2 1
4k7
USB_ENA_A
5V_VCC
AMP_SHDN
47R
R964
R1036
2 1
DIMMING
VESTEL
SCH NAME :
DRAWN BY :
R742
2 1
20k
4k7
2 1
R279
3V3_STBY
3V3_STBY
3V3_STBY
3V3_STBY
3V3_STBY
3V3_STBY
AMP_MUTE
3V3_VCC
3V3_VCC
3V3_STBY
3V3_STBY
1
2
3
1
CONTROLLER
SADIK SEHIT
OVER_CUR_DETECT
BACKLIGHT_DIM
3V3_STBY
3V3_STBY
SDA_NVM
SCL_NVM
U103
24C32
E0
VCC
E1
WC
E2
SCL
VSS SDA
TP111
TP350
TP353
TP307
PROJECT NAME :
SDA
SCL
TX/SDA
RX/SCL
IR_IN
SW_UPDATE_SELECT
R1283
21
22k
4k7
2 1
R1279
DVB_RXD
DVB_TXD
R356
2 1
100R
3V3_STBY
C181
2 1
100n
10V
8
7
6
54
1
1
1
1
PROG_EN
SW_UPDATE_SELECT
RESET_7101
A
C5V6
D174
B
IPOD_GPIO1
10V
1
100k
R724
100n
2
2 1
C182
C
1
TP159
R1265
1k
Reset IC supplyi 3V3 stbyden alindi
21
GND RST
VCC
3
100n
21
D155
MAX810
MAX809LTR
U130
10V
21
C183
1N4148
C1129
22u
25V
D
3V3_STBY
NVM_WP
SCL_NVM
SDA_NVM
TP110
TP109
TP108
TP112
E
F
OF:
A3
185
AX M
17mb37-1
SHEET:
14-10-2009_16:25
87654321
Page 96
A
SCZ
3V3_STBY
SERIAL FLASH
B
MEMORY
C
D
E
1 2 3 4 5 6 7 8
U138
SDO
TP113
TP1151TP114
1
1
21
100R
R365
MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
MADR[0]
MADR[1]
MADR[2]
MADR[3]
TP119
1
MX25L512
1
CS#
2
SO
3
WP#
GND SI
LDM
WEZ
CASZ
RASZ
BADR[0]
BADR[1]
U132
HOLD#
VCC
SCLK
3
2
1
100R
R1310
3
2
1
100R
R1312
R4
R3
R2
R1
R4
R3
R2
R1
R1315
1
2
3
R1324
R1338
R1337
R1336
R1335
R1334
100R
R1
R2
R3
R4
8
7
6
54
54
6
7
8
54
6
7
8
100R
22R
22R
22R
22R
22R
8
7
6
54
TP118
TP117
1
1
VDD_DMC
VDD_DMQ
VDD_DMQ
VDD_DMC
21
21
21
21
21
21
VDD_DMC
TP116
1
C184
2
100n
1
4k7
R761
2 1
10V
SDI
1
TP160
8MB SDRAM
MT48LC4M16A2TG8E
1
VDD1
2
DQ0
3
VDDQ1
4
DQ1
5
DQ2
6
VSSQ1
7
DQ3
8
DQ4
9
VDDQ2
10
DQ5
11
DQ6
12
VSSQ2
13
DQ7
14
VDD2
15
DQML
16
WE#
17
CAS#
18
RAS#
19
CS#
20
BA0
21
BA1
22
A10
23
A0
24
A1
25
A2
26
A3
27
VDD3
D169
C5V1
SCK
C605
2
10u
1
10V
U195
F150
330R
VSS3
DQ15
VSSQ4
DQ14
DQ13
VDDQ4
DQ12
DQ11
VSSQ3
DQ10
DQ9
VDDQ3
DQ8
VSS2
NC2
DQMH
CLK
CKE
NC1
A11
VSS1
MST6WB7GQ-3
DVB_SPDIF
SPDIF_OUT
3V3_VCC
3V3_VCC
R296
4k7
R295
4k7
DVD_SPDIF
21
21
VDDM
S220
R357
100R
BADR1
BADR0
RASZ
VDDC
CASZ
21
3V3_STBY
F125
330R
VDDC
PIN129 PIN203
2
1
21
C194
100n
10V
2
1
C469
10u
10V
2
1
C201
100n
10V
2
1
C202
100n
10V
2
1
C200
100n
10V
2
1
100n
10V
2
1
100n
10V
C198
C199
PIN131 PIN147 PIN162 PIN168 PIN173 PIN179 PIN184
C195
2
100n
1
10V
2
1
100n
10V
1
100n
10V
C196
C197
2
BACKLIGHT_ON/OFF
BC848B
VDDM3V3_VCC
Q157
BKL_ON/OFF
PANEL_VCC_ON/OFF
S216
R795
10k
R794
10k
C1145
BKL_ON/OFF
3V3_VCC
BKL_ON/OFF
6V3
1u
WEZ
MADR[11]
MADR[10]
MADR[9]
54
53
52
51
50
49
VDD_DMQ
48
3
2
1
100R
R1309
R4
R3
R2
R1
54
6
7
8
MDATA[15]
MDATA[14]
MDATA[13]
MDATA[12]
47
46
45
44
43
VDD_DMQ
3
2
1
100R
R1311
R4
R3
R2
R1
54
6
7
8
MDATA[11]
MDATA[10]
MDATA[9]
MDATA[8]
3V3_VCC
42
MADR[8]
MADR[7]
MADR[6]
MADR[5]
MADR[4]
MADR[3]
MADR[2]
MADR[1]
MADR[0]
VDDM
F157
330R
21
2
1
41
40
R1323
100R
MCLK
21
R1314
1
2
3
R1313
1
2
3
100R
R1
R2
R3
R4
100R
R1
R2
R3
R4
UDM
Place MCLKE Clock resistor close to MSTAR Pin
R1322
21
MCLKE100R
8
MADR[11]
7
MADR[10]
6
MADR[9]
54
MADR[8]
8
MADR[7]
7
MADR[6]
6
MADR[5]
54
MADR[4]
VDDM
F287
60R
21
1
C1077
220u
2
6V3
PIN1 PIN14
C1066
2
2
100n
1
1
10V
C1067
100n
10V
PIN27
2
1
C1068
100n
10V
VDD_DMC
39
38
37
36
35
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
AD[0] DQM0
120
AD[1]
121
AD[2]
122
AD[3]
123
WRZ
124
RDZ
21
125
ALE
126
BADR[1]
127
BADR[0]
128
RASZ
129
VDDC2
130
GND7
131
AVDD_MI_1
132
CASZ
133
WEZ
134
WADR[11]
135
WADR[10]
136
WADR[9]
137
WADR[8]
138
WADR[7]
139
WADR[6]
140
WADR[5]
141
WADR[4]
142
WADR[3]
143
WADR[2]
144
WADR[1]
145
WADR[0]
146
GND8
147
AVDD_MI_2
148
AVDD_MIPLL
C213
100n
10V
5
AVDD_MI_3
MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]
AVDD_MI_4
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
AVDD_MI_5
MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]
AVDD_MI_6
MDATA[12]
MDATA[13]
MDATA[14]
MDATA[15]
AVDD_MI_7
SPI_SCK
SPI_SDI
SPI_SCZ
SPI_SDO
DQS0
GND9
GND10
DQS1
DQM1
MCLKZ
MCLK
MCLKE
MVREF
GND13
VDDC3
160119
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
198
199
200
201
202
203
LDM
VDDM
MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]
VDDM
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
VDDM
MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]
VDDM
MDATA[12]
MDATA[13]
MDATA[14]
MDATA[15]
VDDM
UDM
R499
MCLKE
R1316
100R
8
R1
7
R2
6
R3
5 4
R4
VDDC
21
1
2
3
2
1
MCLK100R
SCK
SDI
SCZ
SDO
C1112
1n
50V
21
R536
10k
21
R535
VDDM
10k
2
1
C501
1n
50V
2
1
A
B
C
D
C193
100n
10V
E
1
2
C1076
220u
6V3
PIN3
2
1
C1065
100n
10V
2
1
C1063
100n
10V
F286
VDDM
C1045
2
100n
1
F
10V
21
60R
2
1
C1062
100n
10V
PIN49PIN43PIN9
2
1
C1064
100n
10V
VDD_DMQ
F
WARNING!!!DON'T USE VIA FOR MCLK AND DATA SIGNALS
VESTEL
SCH NAME :
DRAWN BY :
MEMORY INTERFACE
ÖNDER GENÇ
PROJECT NAME :
17mb37
SHEET:
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OF:
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AX M
Page 97
1 2 3 4 5 6 7 8
S128
S127
S126
2
21
21
21
16V
100u
2 1
C453
BC858B
R542
2 1
10k
Q150
1N4148
2 1
21
10k
R546
1
3
D124
2
21
R729
21
10k
100k
R1241
1N4148
2 1
21
10k
R541
A
D127
B
HEADPHONE AMPLIFIER
HP_DETECT
POP NOISE CIRCUIT
12V_VCC
5V_VCC
3V3_VCC
A
C503
1n
50V
C632
HP_R
C537
2
2n2
50V
220n
10V
1
B
C541
2 1
21
100u
R423
4k7
16V
21
R237
C665
1u
16V
21
20k
R211
100k
C122
21
21
50V
220p
1
OUTA
U128
2
INAN
TDA1308T
3
INAP
VSS INBP
VDD
OUTB
INBN
21
8
100k
R212
7
6
R238
54
1N4148
2 1
D126
C386
2
10u
1
10V
21
21
20k
C123
C540
100u
50V
220p
4k7
R424
16V
1N4148
2 1
D125
C502
21
C633
21
220n
50V
1n
10V
R800
1
2
22R
2
1
C538
2n2
50V
8V_VCC
HP_L
MUTE_HP_R
R801
22R
50V
2n2
C625
2
1
F191
MUTE_HP_L
C624
9
2
1
2n2
50V
6
8
5
7
4
3
JK110
2
1
5k1
3k3
R1291
R1290
VDD_AUDIO
5V_VDD_AUDIO
21
21
15k
15k
R123
R1223
21
S296
HP_DETECT
AMP_EN
21
600R
8V_VCC
AMP_MUTE
R722
10k
3
BC848B
2
21
Q133
1
21
3k9
R236
C668
100n
50V
BC848B
Q132
3
1
MUTE_HP_R
2.5 WATT OPTION
GNDA
INP
A1
A2
A3
MAIN_L_AUDIO
C
L_AUDIO_N
C4
10V
2u2
50V
R39
150k
D
AUDIO INPUTS
5V_VDD_AUDIO
3
BC848B
S12
2
Q2
R20
1
100R
16V
1u
R1320
150k
15K
C1131
MAIN_L_AUDIO
MAIN_L
E
5V_VDD_AUDIO
3
BC848B
S11
2
Q1
R19
1
100R
16V
1u
C1130
R1318
150k
15K
MAIN_R_AUDIO
MAIN_R
F
L2
47u
F7
60R
1n
C1117
5V_VDD_AUDIO
VDDA
OUTN
B1
L_OUT_N
2
1
PT2333U192
GNDB
VDD1
B2
B3
C1056
2
100n
1
10V
C1042
10u
10V
5V_VDD_AUDIO
INN
C1
15K
150k
R1319
SDB
C2
AMP_EN
C1132
1u
16V
OUTP
C3
L_OUT_P
AMP_EN
60R
F4
L3
47u
C1115
R24
10k
5V_VDD_AUDIO
50V
1n
5V_VCC
150k
C5
R41
10V
L_AUDIO_P
2u2
AMP_SHDN
R27
10k
R25
10k
S14
1u
C11
S15
MAIN_R_AUDIO
MAIN_R_AUDIO
R_AUDIO_N
16V
1u
C10
16V
C9
1u
16V
C3
10V
2u2
R40
150k
MAIN_L_AUDIO
MUTE
9
SHDN
10
REGEN
11
COM
12
AGND1
13
AGND2
14
REG
15
VS
16
INP
A1
A2
L1
47u
60R
F6
1n
50V
C1116
5V_VDD_AUDIO
8
NC2
NC3
17
5V_VDD_AUDIO
VDDA
OUTN
GNDA
A3
B1
R_OUT_N
2
1
R30
20k
7
6
FBL
INL
NC1
MAX9736B
U1
MOD
FBR
INR
18
19
R29
20k
10k
R26
C1043
10u
10V
R28
5
20
S13
PT2333U191
VDD1
B2
C1057
2
100n
1
10V
10k
4
MONO
C1N
21
C14
100n
50V
GNDB
B3
BOOT
C1P
3
22
C13
1u
25V
C1
INN
C2
150k
R1317
15K
C1133
1u
16V
2
OUTL-1
OUTR-1
23
SDB
C3
AMP_EN
1
OUTL+2
OUTL-2
OUTL+1
PVDD2
PGND2
PGND1
PVDD1
OUTR+2
OUTR+1
OUTR-2
24
OUTP
L4
47u
F5
60R
R_OUT_P
S17
S16
32
31
30
29
28
27
26
25
C1114
50V 1n
VDD_AUDIO
R_OUT_N
10V
2u2
R42
150k
L_OUT_N
L_OUT_P
C15
R_OUT_P
R_AUDIO_P
C6
50V
100n
C16
100n
VDD_AUDIO
50V
5V_VCC
5V_Audio
24V_VCC
12V_VCC
18V_VCC
S298
S279
SCH NAME :
DRAWN BY :
MUTE_HP_L
S22
S20
S23
21
F3
60R
21
R_AUDIO_P
R_AUDIO_N
L_AUDIO_P
L_AUDIO_N
R_AUDIO_P
R_AUDIO_N
L_AUDIO_P
L_AUDIO_N
VESTEL
AUDIO
SADIK SEHIT
3
BC848B
Q134
BC848B
Q135
2
1
3
2
1
D1
SK24
47k
R44
21
10V
220u
C1134
C19
2
100n 10V
1
C18
2
10V100n
1
OPTIONAL
PROJECT NAME :
R544
2 1
10k
R545
2 1
10k
CN115
CN3
C12
330u
35V
D2
1
2
3
4
1
2
3
4
5
6
17mb37
C385
5V_VCC
21
10u
10V
POP_MUTE
VDD_AUDIO
21
1N4148
5V_VDD_AUDIO
SHEET:
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OF:
C
D
E
F
A3
187
AX M
Page 98
A
B
1V0D_FE1
C
1V0D_FE1
D
E
F
3V3D_FE
1V0D_FE1
3V3D_FE
3V3D_FE
DIGITAL_IF-
DIGITAL_IF+
1 2 3 4 5 6 7 8
U174
TS431AIL
1 5
A
C908
2
1
21
C1161
6V3
2V5_QAM
C937C941
100n
C723
100n
10V
100n
16V
2
3 4
RC
C945
1n
50V
Q176
BC846B
50V
33p
FE1_SCL
FE1_SDA
50V
33p
SDA_TUN_DVB
SCL_TUN_DVB
RF_AGC_DVB
16V
IF_AGC_T
C700
2
100n
1
10V
C223
2
100n
1
10V
BCP56-16
Q175
2V5_QAM
C699
2
100n
1
10V
C207
2
100n
1
10V
R928
10k
R1209
1k
BA159
BC817-25
Q103
2
C227
Q171
BC847B
Q170
BC847B
3V3D_FE
2
1
D166
2V5_QAM
1
10V
100n
C206
100n
10V
3V3_VCC
1V_QAM
3
1
1
IF_AGC_T
IF_AGC_C
3V3_QAM
C1157
220u
3V3_VCC
2
R117
150R
1V_QAM
R1018
4k7
2 1
R803
4k7
2 1
6V3
2
F264
1k
C304
33p
50V
C305
33p
50V
R407
2 1
C830
C849
100n
100n
21
X101
21
1k
C905
IDTV_SW
IDTV_SW
1V0_FE
C930
27MHZ
21
2V5_QAM
2V5_QAM
C228
100n
10V
1V_QAM
100n
3V3_QAM
16V
10u
2
1
1V0_FE
1V0_FE
1V_QAM
C658
100n
C657
100n
DIGITAL_IF-
DIGITAL_IF+
C929
2V5_QAM
49
GNDD_AD12
50
VCCD_AD12
51
GNDA_PLL
52
VCCA_PLL
53
GNDD_PLL
54
VCCD_PLL
55
ZO
56
VCCA_OSC
57
A
58
GNDA_OSC
59
VBASE
60
VDD10REG
61
VDD4
62
GND4
63
VDD_IO_3V3_4
64
CLK_TST
F255
220R
F256
220R
TP161
1
C217
2
100n
1
10V
16V
10u
2
1
C224
48
VCCA_AD12
GPIO9
1
R31421100R
C750
2
100n
1
10V
C216
100n
10V
16V
10n
2 1
C384
C356
10n
16V
21
IF_M
R1061
1k
R1060 IF_CM
1k
C928
IF_P
IF_P
10V
1
2
100n
47
46
REFP
GNDA_AD12
45
REFM
IF_CM
44
INCM
C935
2V5_QAM
4p7
50V
42
43
INP
VCCAISO_D
41
INM
DVB-C
DEMODULATOR
U109
STV0297E
GPIO8
TDI
TDO
TRST
TCK
TMS
GPIO7/AUX_CLK
8
7
6
5
4
3
2
21
100R
R313
21
2
1
1V0D_FE1
C220
2
100n
1
10V
21
33R
R1098
C_RESET
4k7
R239
3V3_QAM
SCL_TUN_DVB
SDA_TUN_DVB
1V0A_FE1
C749
2
100n
1
10V
C215
2
100n
1
10V
C1041
100n
2
1
C214
2
100n
1
10V
10V
C748
100n
10V
16V
10u
C904
100n
IF_M
3V3_QAM
38
39
40
GNDAS_AD
VDD_IO_3V3_3
N_RESET
VDD1
9
11
10
1V_QAM
21
33R
R171
RESET_DVB
IF_AGC_C
IF_AGC_T
IF_AGC_C
IF_AGC_T
VESTEL
SCH NAME :
DRAWN BY :
16V
1V_QAM
35
36
37
GND3
VDD3
GPIO0/AGC2
GPIO1/AGC1
GND1
VDD_IO_3V3_1
GPIO6/CS0
GPIO5/CS1
14
13
12
S235
S234
21
4k7
R463
3V3_QAM
3V3_QAM
1
B1
2
GND
FSA3157
B0 A
S240
S239
DVB COFDM & QAM
ERTUG BAL
21
10k
R331
33
34
GPIO4/SDAT
GPIO2
TS_DATA[7]
GPIO3/SCLT
TS_DATA[6]
TS_DATA[5]
TS_DATA[4]
VDD_IO_3V3_2
TS_DATA[3]
TS_DATA[2]
TS_DATA[1]
TS_DATA[0]
SDA
SCL
16
15
21
100R
100R
R311
2 1
FE1_SDA
FE1_SCL
S
U182
VCC
PROJECT NAME :
C1020C1024
C1026
C1021
C1032
1u
6V3
C1031
1u
6V3
16V
100n
16V
100n
16V
100n
16V
100n
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C1022
16V
10n
2 1
C757
C756
10n
16V
100n
21
1V0D_FE1
GPIO1
VDD_3V3_5
VDD_1V_6
GPIO8
GPIO7
GPIO6
VDD_1V_7
VDD_3V3_6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO9
VDD_1V_8
VDD_3V3_7
TEST
16V
C695
R1063
1k
R1062
1k
33R
R1341
R1153
10V
10u
IM_1
IP_1
8
1
48
1
TSPKTERR_1
TSVALID_1
7
6
R2
3
2
46
47
ERROR
D/NOT_P
RF_LEVEL
VDDA_2V5_1QPQM
3
2
C911
30k
100n
REFP_1
REFM_1
C927
10u
3V3_VCC
TSPKTCLK_1
TSBYTECLK_1
TS_DATA7_1
TS_DATA6_1
TS_DATA5_1
TS_DATA4_1
3p9
C916
54
R3R1R4
45
STR_OUT
VDD_1V_5
R1116
44
CLK_OUT
43
33R
D7
8
1
7
2
42
D6
6
R2
R3R1R4
3
3V3D_FE
41
VDD_3V3_4
54
R1117
1V0D_FE1
38
39
40
D5
D4
VDD_1V_4
DVB-T
DEMODULATOR
U152
STV0362
VDDA_ISO
VDDA_2V5_2
REFP
REFM
INCMIMIP
9
8
7
6
5
4
16V
2V5A_FE
16V
C912
C946
100n
6V3
1n
16V
220u
50V
C758
REFP_1
2 1
C1159
REFM_1
INCM_1
16V
10n
F237
330R
INCM_1
IM_1
21
C1160
22u
6V3
10
C936
4p7
50V
11
C799
100p
50V
C1023
100n
16V
TS_DATA3_1
TS_DATA2_1
8
33R
1
36
37
D3
D2
VDDA_1V
VDDA_2V5_3
13
12
IP_1
2V5A_FE
1V0A_FE1
C1028
C721
2
100n
1
10V
7
R2
2
D165
BA159
BA159
D164
35
D1
XTAL_O
14
X108
27MHz
33p
TS_DATA1_1
TS_DATA0_1
6
54
R3R1R4
3
3V3D_FE
33
34
D0
VDD_3V3_3
XTAL_I
VDDA_2V5_4
16
15
50V
C1027
2V5A_FE
NOT_RESET
VDD_1V_3
VDD_3V3_2
GPIO0
VDD_1V_2
AUX_CLK
VDD_3V3_1
VDD_1V_1
AGC_RF
AGC_IF
C910
100n
16V
2V5A_FE
50V
33p
2V5A_FE
F127
330R
SCL
SDA
CS1
CS0
SDAT
SCLT
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3V3_VCC
3V3_VCC
21
2
1
C283
10u
10V
3V3_VCC 220R
R1141
47k
S267
S266
1V0D_FE1
R1077
100R
R1078
100R
3V3D_FE
16V16V
C1019
100n
100n
C1025
1V0D_FE1
R1042
R1043
4k7
1V0D_FE1
R911
R910
R908
10k
R909
10k
4k7
10k
10k
C907
F238
330R
22u
6V3
100u
C221
2
100n
1
10V
R1059
RESET_DVB
RESET_T
3V3D_FE
R1083
100R
R1084
100R
3V3D_FE
R1168
180R
16V
C909
100n
3V3D_FE
R1167
180R
16V
C906
100n
21
C1162
6V3
F128
330R
22u
C1151
C725
2
100n
1
10V
place this cap close to pin#56
IF_AGC_C
100n
C225
2
1
R332
10k
4k7
2 1
R298
GND2
VDD2
M_ERR
M_VALID
M_SYNC
M_CKOUT
R312
21
4k7
R469
3V3_QAM
6
5
43
IF_AGC_DVB
10V
21
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4k7
R1038
4k7
R1037
17mb37
3V3_QAM
R427
33R
1
R1
2
R2
3
R3
R4
3V3_QAM
1V_QAM
R426
1
R1
2
R2
3
R3
R4
R1342
1
R1
2
R2
3
R3
R4
AGC_S1
S256
10V
C743
100n
C1033
14-10-2009_09:10
87654321
8
7
6
54
8
7
6
54
8
7
6
54
10V
100n
SHEET:
C_D7
C_D6
C_D5
C_D4
C_D3
C_D2
C_D1
C_D0
C_ERR
C_VAL
C_STRT
C_CLK
C188
2
15p
1
50V
5V_VCC
IF_AGC_DVB
A3
OF:
A
B
C
D
E
F
188
AX M
Page 99
A
B
C
D
E
F
VDD_S_LMI_2V6
S_LMIDATA[0]
VDD_S_LMI_2V6
S_LMIDATA[1]
S_LMIDATA[2]
S_LMIDATA[3]
S_LMIDATA[4]
VDD_S_LMI_2V6
S_LMIDATA[5]
S_LMIDATA[6]
S_LMIDATA[7]
VDD_S_LMI_2V6
S_LDQS[0]
VDD_S_LMI_2V6
S_LDQM[0]
S_LWE
S_LCAS
S_LRAS
S_LCS
S_LBANK[0]
S_LBANK[1]
S_LMI_AD[10]
S_LMI_AD[0]
S_LMI_AD[1]
S_LMI_AD[2]
S_LMI_AD[3]
VDD_S_LMI_2V6
S_LMI_DATA0
S_LMI_DATA1
S_LMI_DATA2
S_LMI_DATA3
S_LMI_DATA4
S_LMI_DATA5
S_LMI_DATA6
S_LMI_DATA7
S_LMI_DATA8
S_LMI_DATA9
S_LMI_DATA10
S_LMI_DATA11
S_LMI_DATA12
S_LMI_DATA13
S_LMI_DATA14
S_LMI_DATA15
S_NOTLCLK
S_LMI_CLK
S_LMI_NOTCLK
S_LMI_CKEN
1k
R10011kR1003
C249
2
100n
1
10V
1 2 3 4 5 6 7 8
LMI SYSTEM DDR LMI SYSTEM DDR LMI VIDEO DDR LMI VIDEO DDR
2
1
3
2
1
3
2
1
3
2
1
3
2
1
C248
100n
10V
1
VDD1
2
DQ0
3
VDDQ1
4
DQ1
5
DQ2
6
VSSQ1
7
DQ3
8
DQ4
9
VDDQ2
10
DQ5
11
DQ6
12
VSSQ2
13
DQ7
14
NC1
15
VDDQ3
16
LDQS
HY5DU561622D
17
NC2
18
VDD2
19
NC3
20
LDM
21
WE#
22
CAS#
23
RAS#
24
CS#
25
NC4
26
BA0
27
BA1
28
A10/AP
29
A0
30
A1
31
A2
32
A3
33
VDD3
33R
R4
54
R3
6
R2
7
R1
8
R442
33R
R4
54
R3
6
R2
7
R1
8
R441
33R
R4
54
R3
6
R2
7
R1
8
R439
33R
R4
54
R3
6
R2
7
R1
8
R438
R315
21
100R
R193
33R
21
R186
33R
21
R188
21
33R
C250
2
100n
1
10V
C289
2
10u
1
10V
U156
S_LMIDATA[0]
S_LMIDATA[1]
S_LMIDATA[2]
S_LMIDATA[3]
S_LMIDATA[4]
S_LMIDATA[5]
S_LMIDATA[6]
S_LMIDATA[7]
S_LMIDATA[8]
S_LMIDATA[9]
S_LMIDATA[10]
S_LMIDATA[11]
S_LMIDATA[12]
S_LMIDATA[13]
S_LMIDATA[14]
S_LMIDATA[15]
S_LCLK
S_LCLK
S_NOTLCLK
S_LCKEN
S_LMI_VREF
C676
10u
10V
VDD_S_LMI_2V6
66
VSS3
65
DQ15
VSSQ5
DQ14
DQ13
VDDQ5
DQ12
DQ11
VSSQ4
DQ10
DQ9
VDDQ4
DQ8
NC7
VSSQ3
UDQS
NC6
VREF
VSS2
UDM
CLK#
CLK
CKE
NC5
A12
A11
A9
A8
A7
A6
A5
A4
VSS1
S_LMIDATA[23]
64
63
S_LMIDATA[22]
62
S_LMIDATA[21]
61
VDD_S_LMI_2V6
60
S_LMIDATA[20]
59
S_LMIDATA[19]
58
57
S_LMIDATA[18]
56
S_LMIDATA[17]
55
VDD_S_LMI_2V6
54
S_LMIDATA[16]
53
52
51
S_LDQS[2]
50
49
S_LMI_VREF
48
47
S_LDQM[2]
46
S_NOTLCLK
45
S_LCLK
44
S_LCKEN
43
42
S_LMI_AD[12]
41
S_LMI_AD[11]
40
S_LMI_AD[9]
39
S_LMI_AD[8]
38
S_LMI_AD[7]
37
S_LMI_AD[6]
36
S_LMI_AD[5]
35
S_LMI_AD[4]
34
S_LMI_DATA16
S_LMI_DATA17
S_LMI_DATA18
S_LMI_DATA19
S_LMI_DATA20
S_LMI_DATA21
S_LMI_DATA22
S_LMI_DATA23
S_LMI_DATA24
S_LMI_DATA25
S_LMI_DATA26
S_LMI_DATA27
S_LMI_DATA28
S_LMI_DATA29
S_LMI_DATA30
S_LMI_DATA31
R315 DDR IC'LERE YAKIN OLMALI
C288 & C289 DDR PIN33'LERE YAKIN OLMALI
C??? DDR IC'LERE YAKIN OLMALI
C254 STi7101'E YAKIN OLMALI
C277 VE R? BIRBIRINE YAKIN OLMALI
S_LMI_AD[3]
33R
R4
R3
3
R2
2
R1
1
R452
33R
R4
R3
3
R2
2
R1
1
R451
33R
R4
R3
3
R2
2
R1
1
R443
33R
R4
R3
3
R2
2
R1
1
R445
VDD_S_LMI_2V6
S_LMIDATA[8]
VDD_S_LMI_2V6
S_LMIDATA[9]
S_LMIDATA[10]
S_LMIDATA[11]
S_LMIDATA[12]
VDD_S_LMI_2V6
S_LMIDATA[13]
S_LMIDATA[14]
S_LMIDATA[15]
VDD_S_LMI_2V6
S_LDQS[1]
VDD_S_LMI_2V6
S_LDQM[1]
S_LBANK[0]
S_LBANK[1]
S_LMI_AD[10]
S_LMI_AD[0]
S_LMI_AD[1]
S_LMI_AD[2]
VDD_S_LMI_2V6
S_LMIDATA[16]
54
S_LMIDATA[17]
6
S_LMIDATA[18]
7
S_LMIDATA[19]
8
S_LMIDATA[20]
54
S_LMIDATA[21]
6
S_LMIDATA[22]
7
S_LMIDATA[23]
8
S_LMIDATA[24]
54
S_LMIDATA[25]
6
S_LMIDATA[26]
7
S_LMIDATA[27]
8
S_LMIDATA[28]
54
S_LMIDATA[29]
6
S_LMIDATA[30]
7
S_LMIDATA[31]
8
S_LWE
S_LCAS
S_LRAS
S_LCS
1
VDD1
2
DQ0
3
VDDQ1
4
DQ1
5
DQ2
6
VSSQ1
7
DQ3
8
DQ4
9
VDDQ2
10
DQ5
11
DQ6
12
VSSQ2
13
DQ7
14
NC1
15
VDDQ3
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
S_LMI_NOTBANK1
S_LMI_NOTBANK0
S_LMI_RDNOTWR
U154
LDQS
HY5DU561622D
NC2
VDD2
NC3
LDM
WE#
CAS#
RAS#
CS#
NC4
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD3
S_LMI_ADDR0
S_LMI_NOTCS0
S_LMI_ADDR10
S_LMI_ADDR3
S_LMI_ADDR2
S_LMI_ADDR1
S_LMI_ADDR4
S_LMI_ADDR9
S_LMI_ADDR12
S_LMI_ADDR11
S_LMI_ADDR7
S_LMI_ADDR8
S_LMI_ADDR5
S_LMI_ADDR6
S_LMI_NOTRAS
S_LMI_NOTCAS
S_LMI_DQS0
S_LMI_DQM0
S_LMI_DQM2
S_LMI_DQS2
S_LMI_DQS1
S_LMI_DQM1
S_LMI_DQM3
S_LMI_DQS3
VSS3
DQ15
VSSQ5
DQ14
DQ13
VDDQ5
DQ12
DQ11
VSSQ4
DQ10
DQ9
VDDQ4
DQ8
NC7
VSSQ3
UDQS
NC6
VREF
VSS2
UDM
CLK#
CLK
CKE
NC5
A12
A11
VSS1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
A9
A8
A7
A6
A5
A4
33R
R4
R3
R2
R1
R450
33R
R4
R3
R2
R1
R444
33R
R4
R3
R2
R1
R446
33R
R4
R3
R2
R1
R437
33R
R4
R3
R2
R1
R183
33R
R4
R3
R2
R1
R434
33R
R4
R3
R2
R1
R435
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
S_LMIDATA[31]
S_LMIDATA[30]
S_LMIDATA[29]
VDD_S_LMI_2V6
S_LMIDATA[28]
S_LMIDATA[27]
S_LMIDATA[26]
S_LMIDATA[25]
VDD_S_LMI_2V6
S_LMIDATA[24]
S_LDQS[3]
S_LMI_VREF
S_LDQM[3]
S_NOTLCLK
S_LCLK
S_LCKEN
S_LMI_AD[12]
S_LMI_AD[11]
S_LMI_AD[9]
S_LMI_AD[8]
S_LMI_AD[7]
S_LMI_AD[6]
S_LMI_AD[5]
S_LMI_AD[4]
S_LMI_AD[0]
S_LCS
S_LBANK[1]
S_LMI_AD[10]
S_LMI_AD[3]
S_LMI_AD[2]
S_LMI_AD[1]
S_LMI_AD[4]
S_LMI_AD[9]
S_LMI_AD[12]
S_LMI_AD[11]
S_LMI_AD[7]
S_LMI_AD[8]
S_LMI_AD[5]
S_LMI_AD[6]
S_LBANK[0]
S_LRAS
S_LCAS
S_LWE
S_LDQS[0]
S_LDQM[0]
S_LDQM[2]
S_LDQS[2]
S_LDQS[1]
S_LDQM[1]
S_LDQM[3]
S_LDQS[3]
V_LMI_ADDR0
V_LMI_NOTCS0
V_LMI_CKEN
V_LMI_ADDR11
V_LMI_ADDR3
V_LMI_ADDR2
V_LMI_ADDR1
V_LMI_ADDR4
V_LMI_ADDR12
V_LMI_ADDR9
V_LMI_ADDR10
V_LMI_ADDR8
V_LMI_ADDR7
V_LMI_ADDR6
V_LMI_ADDR5
V_LMI_NOTBANK1
V_LMI_NOTBANK0
V_LMI_NOTRAS
V_LMI_NOTCAS
V_LMI_DQS2
V_LMI_DQM2
V_LMI_DQM0
V_LMI_DQS0
V_LMI_DQS3
V_LMI_DQM3
V_LMI_DQM1
V_LMI_DQS1
3
2
1
R1105
3
2
1
R1115
3
2
1
R1107
3
2
1
R1104
3
2
1
R1106
3
2
1
R1112
3
2
1
R1114
33R
R4
R3
R2
R1
33R
R4
R3
R2
R1
33R
R4
R3
R2
R1
33R
R4
R3
R2
R1
33R
R4
R3
R2
R1
33R
R4
R3
R2
R1
33R
R4
R3
R2
R1
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
54
6
7
8
V_LMI_AD[0]
V_LCS
V_LCKEN
V_LMI_AD[11]
V_LMI_AD[3]
V_LMI_AD[2]
V_LMI_AD[1]
V_LMI_AD[4]
V_LMI_AD[12]
V_LMI_AD[9]
V_LMI_AD[10]
V_LMI_AD[8]
V_LMI_AD[7]
V_LMI_AD[6]
V_LMI_AD[5]
V_LBANK[1]
V_LBANK[0]
V_LRAS
V_LCAS
V_LDQS[2]
V_LDQM[2]
V_LDQM[0]
V_LDQS[0]
V_LDQS[3]
V_LDQM[3]
V_LDQM[1]
V_LDQS[1]
VDD_V_LMI_2V6
V_LMIDATA[23]
VDD_V_LMI_2V6
V_LMIDATA[22]
V_LMIDATA[21]
V_LMIDATA[20]
V_LMIDATA[19]
VDD_V_LMI_2V6
V_LMIDATA[18]
V_LMIDATA[17]
V_LMIDATA[16]
VDD_V_LMI_2V6
V_LDQS[2]
VDD_V_LMI_2V6
V_LDQM[2]
V_LWE
V_LCAS
V_LRAS
V_LCS
V_LBANK[0]
V_LBANK[1]
V_LMI_AD[10]
V_LMI_AD[0]
V_LMI_AD[1]
V_LMI_AD[2]
V_LMI_AD[3]
VDD_V_LMI_2V6
V_NOTLCLK
V_LMI_CLK
V_LMI_NOTCLK
V_LMI_RDNOTWR
R318 DDR IC'LERE YAKIN OLMALI
C289 DDR PIN33'E YAKIN OLMALI
C??? DDR IC'LERE YAKIN OLMALI
C260 STi7101'E YAKIN OLMALI
C278 VE R? BIRBIRINE YAKIN OLMALI
1
VDD1
2
DQ0
3
VDDQ1
4
DQ1
5
DQ2
6
VSSQ1
7
DQ3
8
DQ4
9
VDDQ2
10
DQ5
11
DQ6
12
VSSQ2
13
DQ7
14
NC1
15
VDDQ3
16
LDQS
HY5DU561622D
17
NC2
18
VDD2
19
NC3
20
LDM
21
WE#
22
CAS#
23
RAS#
24
CS#
25
NC4
26
BA0
27
BA1
28
A10/AP
29
A0
30
A1
31
A2
32
A3
33
VDD3
R318
21
100R
R182
33R
21
R189
21
33R
R190
21
33R
U153
VSS3
DQ15
VSSQ5
DQ14
DQ13
VDDQ5
DQ12
DQ11
VSSQ4
DQ10
DQ9
VDDQ4
DQ8
NC7
VSSQ3
UDQS
NC6
VREF
VSS2
UDM
CLK#
CLK
CKE
NC5
A12
A11
A9
A8
A7
A6
A5
A4
VSS1
V_LCLK
V_LCLK
V_NOTLCLK
V_LWE
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V_LMI_DATA10
V_LMI_DATA11
V_LMI_DATA12
V_LMI_DATA13
V_LMI_DATA14
V_LMI_DATA15
R1004
V_LMIDATA[0]
V_LMIDATA[1]
V_LMIDATA[2]
VDD_V_LMI_2V6
V_LMIDATA[3]
V_LMIDATA[4]
V_LMIDATA[5]
V_LMIDATA[6]
VDD_V_LMI_2V6
V_LMIDATA[7]
V_LDQS[0]
V_LMI_VREF
V_LDQM[0]
V_NOTLCLK
V_LCLK
V_LCKEN
V_LMI_AD[12]
V_LMI_AD[11]
V_LMI_AD[9]
V_LMI_AD[8]
V_LMI_AD[7]
V_LMI_AD[6]
V_LMI_AD[5]
V_LMI_AD[4]
V_LMI_DATA0
V_LMI_DATA1
V_LMI_DATA2
V_LMI_DATA3
V_LMI_DATA4
V_LMI_DATA5
V_LMI_DATA6
V_LMI_DATA7
V_LMI_DATA8
V_LMI_DATA9
1k
1k
R1002
C273
2
2
100n
1
1
10V
2
1
C247
100n
10V
1
2
3
1
2
3
1
2
3
1
2
3
C266
100n
10V
R453
33R
R432
33R
R448
33R
R449
33R
C677
10u
10V
VDD_V_LMI_2V6
V_LMIDATA[31]
VDD_V_LMI_2V6
V_LMIDATA[30]
V_LMIDATA[29]
V_LMIDATA[28]
V_LMIDATA[27]
VDD_V_LMI_2V6
V_LMIDATA[26]
V_LMIDATA[25]
V_LMIDATA[24]
VDD_V_LMI_2V6
V_LDQS[3]
VDD_V_LMI_2V6
V_LDQM[3]
V_LWE
V_LCAS
V_LRAS
V_LCS
V_LBANK[0]
V_LBANK[1]
V_LMI_AD[10]
V_LMI_AD[0]
V_LMI_AD[1]
V_LMI_AD[2]
V_LMI_AD[3]
VDD_V_LMI_2V6
8
R1
R2
R3
R4
R1
R2
R3
R4
R1
R2
R3
R4
R1
R2
R3
R4
7
6
54
8
7
6
54
8
7
6
54
8
7
6
54
V_LMI_VREF
C675
10u
10V
VDD_V_LMI_2V6
V_LMIDATA[0]
V_LMIDATA[1]
V_LMIDATA[2]
V_LMIDATA[3]
V_LMIDATA[4]
V_LMIDATA[5]
V_LMIDATA[6]
V_LMIDATA[7]
V_LMIDATA[8]
V_LMIDATA[9]
V_LMIDATA[10]
V_LMIDATA[11]
V_LMIDATA[12]
V_LMIDATA[13]
V_LMIDATA[14]
V_LMIDATA[15]
VESTEL
SCH NAME :
DRAWN BY :
1
VDD1
2
DQ0
3
VDDQ1
4
DQ1
5
DQ2
6
VSSQ1
7
DQ3
8
DQ4
9
VDDQ2
10
DQ5
11
DQ6
12
VSSQ2
13
DQ7
14
NC1
15
VDDQ3
16
LDQS
HY5DU561622D
17
NC2
18
VDD2
19
NC3
20
LDM
21
WE#
22
CAS#
23
RAS#
24
CS#
25
NC4
26
BA0
27
BA1
28
A10/AP
29
A0
30
A1
31
A2
32
A3
33
VDD3
V_LMI_DATA16
V_LMI_DATA17
V_LMI_DATA18
V_LMI_DATA19
V_LMI_DATA20
V_LMI_DATA21
V_LMI_DATA22
V_LMI_DATA23
V_LMI_DATA24
V_LMI_DATA25
V_LMI_DATA26
V_LMI_DATA27
V_LMI_DATA28
V_LMI_DATA29
V_LMI_DATA30
V_LMI_DATA31
U155
VSS3
DQ15
VSSQ5
DQ14
DQ13
VDDQ5
DQ12
DQ11
VSSQ4
DQ10
DQ9
VDDQ4
DQ8
NC7
VSSQ3
UDQS
NC6
VREF
VSS2
UDM
CLK#
CLK
CKE
NC5
A12
A11
A9
A8
A7
A6
A5
A4
VSS1
PROJECT NAME :
DDR RAM FOR STi7101
HUSEYIN E. CETIN
1
2
3
1
2
3
1
2
3
1
2
3
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
R436
33R
R1
R2
R3
R4
R433
33R
R1
R2
R3
R4
R440
33R
R1
R2
R3
R4
R447
33R
R1
R2
R3
R4
V_LMIDATA[8]
V_LMIDATA[9]
V_LMIDATA[10]
VDD_V_LMI_2V6
V_LMIDATA[11]
V_LMIDATA[12]
V_LMIDATA[13]
V_LMIDATA[14]
VDD_V_LMI_2V6
V_LMIDATA[15]
V_LDQS[1]
V_LMI_VREF
V_LDQM[1]
V_NOTLCLK
V_LCLK
V_LCKEN
V_LMI_AD[12]
V_LMI_AD[11]
V_LMI_AD[9]
V_LMI_AD[8]
V_LMI_AD[7]
V_LMI_AD[6]
V_LMI_AD[5]
V_LMI_AD[4]
8
V_LMIDATA[16]
7
V_LMIDATA[17]
6
V_LMIDATA[18]
54
V_LMIDATA[19]
8
V_LMIDATA[20]
7
V_LMIDATA[21]
6
V_LMIDATA[22]
54
V_LMIDATA[23]
8
V_LMIDATA[24]
7
V_LMIDATA[25]
6
V_LMIDATA[26]
54
V_LMIDATA[27]
8
V_LMIDATA[28]
7
V_LMIDATA[29]
6
V_LMIDATA[30]
54
V_LMIDATA[31]
17mb37
SHEET:
14-10-2009_09:10
87654321
OF:
A
B
C
D
E
F
A3
189
AX M
Page 100
1 2 3 4 5 6 7 8
17PW26 CONNECTOR
A
B
C
D
E
F
KEYBOARD_ONBOARD
C7
47u
16V
5V_VCC
1
TP31
12V_STBY
18V_VCC
12V_VCC
TP26
5V_PW
5V_PW
12V_STBY
18V_VCC
12V_VCC
1
TP23
12V_STBY
MOSFET_CONTROL
24V_VCC
5V_PW
FS6
7A/32VDC
!
TP33
17IPS17 CONNECTOR
1
20 19
18 17
16 15
14 13
12 11
10 9
CN137
S303
5V_STBY
TP29
1
21
1
8 7
6 5
4 3
2 1
21
C1086
220n
25V
C108521R1296
R1276
2 1
4k7
C1055
100n
10V
CN4
3V3_VCC
1
1
1
12V_VCC
C1102
22u
16V
25V
220n
2
2
1
21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
TP25
TP28
TP27
2
1
33k
2 1
33k
R1297
2 1
3
1
A/D DIMMING SELECTION
R22
4k7
R21
4k7
R23
4k7
12V_STBY
3V3_VCC
12V_STBY
5V_STBY
C5V6
D182
2 1
21
D180
C5V6
C1071
2
10n
1
16V
C1103
2
22u
1
16V
D188
21
SS33
43
R1253
21
47R
Q181
BC848B
21
21
21
6V3
220u
C8
3V3_VCC
5V_STBY
12V_VCC
C5V6
2 1
1
BS
2
IN
3
SW
4
GND
L122
10u
5
2
5V_VCC
3V3_VCC
24V_VCC
1
TP30
S19
21
PIN 13-14 OF CN4 ARE 3V3
D181
U187
MP1583
COMP
21
SS
EN
FB
2
1
8
7
6
5
C1098
22u
16V
C1097
22u
21
1k
R1257
21
30k
R1306
16V
R1270
4k7
R1271
4k7
R1275
4k7
R1272
4k7
MECH_SWITCH
C1122
21
5n6
C1080
50V
100n
TP380
1
2
1
21
R1301
21
16V
5V_STBY
!
FS3
6
1
Q183
FDC642P
TP387
7A/32VDC
3V3_STBY12V_STBY
21
DIMMING
21
BACKLIGHT_ON/OFF
21
STBY_ON/OFF
21
STBY_ON/OFF_NOT
10V
100n
C1046
21
3k9
NC
R1245
10k
3V3_STBY
MOSFET_CONTROL
21
5V_VCC
PAULO DECOUPLING
3V3_STBY
1V26_STBY
3V3_STBY
12V_VCC
STBY_ON/OFF
STBY_ON/OFF_NOT
12V_STBY
F146
330R
F147
330R
F145
330R
F279
330R
10V
10V
10V
S305
C1088
220n
25V
ADAPTER OPTIONS
21
S21
21
C1092
R1274
2 1
4k7
C1054
100n
10V
5
4
JK109
3
2
1
21
2 1
10u
21
2 1
10u
21
2 1
10u
21
1
2
21
220n
2
1
S289
S280
25V
2
C408
C410
C409
C470
47u
16V
C1110
22u
33k
R1299
2 1
33k
R1298
2 1
3
1
7A/32VDC
7A/32VDC
16V
VDDP
C307
2
100n
1
10V
VDDC
C308
2
100n
1
10V
AVDD_33
C306
2
100n
1
10V
U122
LM1117
3 2
GND
OUTIN
VOUT
4
1
MOSFET_CONTROL
C1074
10n
16V
C1111
2
2
22u
1
1
16V
D190
21
SS33
R1252
21
47R
Q177
BC848B
5V_STBY
!
FS5
21
12V_PSU
!
FS4
21
12V_INV
2
1
5
43
2
12V_STBY
1
2
3
4
21
R411
BS
IN
SW
GND
L124
10u
6
1
2k
R378
10k
U190
MP1583
COMP
21
Q182
FDC642P
S301
S300
C1089
220n
25V
21
C452
21
8
SS
7
EN
6
5
FB
C1108
C1109
2
22u
22u
1
16V
MOSFET_CONTROL
1
D179
TP381
21
21
8V_VCC
25V
10u
R476
1k
21
1k
R1262
21
30k
R1308
16V
C5V6
21
21
3k9
C1124
5n6
50V
C1083
16V
100n
TP388
1
2
1
3V3_VCC
C1105
22u
16V
2V6_ST
R1339
100n
10V
C1058
21
21
NC
21
12V_STBY
5V_Audio
2 1
2
1
D191
SS33
3V3_STBY
3k9
R1340
R1303
3k9
R1242
10k
R1273
4k7
C1053
100n
10V
C1072
10n
16V
C1104
2
22u
1
16V
21
21
12V_PSU
21
21
2
1
2
1
S269
1
2
3
4
2
BS
IN
SW
GND
L125
10u
C1100
22u
16V
MP1583
S210
21
C1084
21
33k
3
1
12V_STBY
12V_VCC
U189
21
6V3
2 1
C464
220u
NC NC
F8
330R
C20
100n
MOSFET_CONTROL
S302
21
C1079
4u7
16V
21
33k
25V
R1294
220n
2 1
R1249
R1295
Q180
BC848B
8
SS
7
EN
6
COMP
5
FB
21
2k
R1321
21
15k
21
R1293
C1099
2
22u
1
16V
2
1
47R
S306
S307
C578
22u
16V
2V5_ST
C1125
5n6
50V
TP378
1
2
1
R702
33k
21
21
21
C1047
100n
21
C1081
100n
NC
NC
2
1
10V
16V
C576
22u
16V
21
C1093
220n
25V
43
21
R1304
3k9
21
D178
4 3
MP2112
VINA
5
EN
6
C535
21
1n
D186
C18V
6
5
Q184
FDC642P
2
1
12V_IPOD
21
R1246
10k
3V3_STBY
C5V6
GND
U144
12V_VCC
12V_STBY
1
TP377
21
SWVINB
10u
2
L110
FB
1
1V0_ST
12V_VCC
2V5_ST
12V_VCC
BACKLIGHT_ON/OFF
DIMMING
1
TP384
C1051
100n
10V
5V_VCC
12V_VCC
3V3_VCC
PANEL_VCC_ON/OFF
C972
220u
25V
2
1
21
C575
2
22u
1
16V
200k
R249
R818
180k
C816
C876
22u
100n
F244
R931
10k
R1074
10k 2k7
C875
C815
100n
22u
F243
R930
10k
R1075
10k
TP386
11
10
F170
21
60R
F171
21
C579
2
22u
1
16V
NC
2 1
S134
8
7
6
5 4
8
7
6
5 4
2
1
C1052
9
8
1V26_STBY
VCC
U183
SYNCH
GND
L5985
FSW
VCC
U184
SYNCH
GND
L5985
FSW
1
10V
100n
7
6
25V
220n
C1
21
OUT
INH
COMPFB
OUT
INH
COMPFB
5
60R
F172
60R
F285
21
C618
21
21
25V
220n
21
33k
60R
10k
R566
2 1
R575
2 1
10k
C309
100n
10V
3
2
2
1
1
VESTEL
SCH NAME :
DRAWN BY :
POWER
SADIK SEHIT
D177
D176
D161
C761
10n
C812
22u
16V
R1139
R1064
SK24
1
2
3
L120
10u
R1142
C920
10p
D162
C814
C759
10n
22u
16V
R1176
R1152
SK24
1
2
3
R929
10k
L121
10u
C918
10p
INVERTER SOCKET
1
TP385
C1091
220n
4
3
2
43
R700
R205
21
47R
C2
2
22u
1
Q139
BC848B
16V
PANEL SUPPLY SWITCH
PROJECT NAME :
1
5
2
CN144
6
1
C17
2
22u
1
16V
FDC642P
25V
Q104
17mb37
87654321
1V0_ST
2V5_ST
C764
10n
16V
1V0_ST
C754
47u
16V
390R
6k8
C779
10n
16V
2V5_ST
C753
47u
16V
2k
30k
12V_INV
C1078
4u7
16V
TP149
1
PANEL_VCC
SHEET:
OF:
15-10-2009_15:59
A
B
C
D
E
F
A3
1810
AX M
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