MX8
S6240-xxx
TECHNICAL REFERENCE
®
Intel
Pentium
or
Intel® Celeron
PROCESSOR-BASED
SBC
®
4
®
WARRANTY The product is warranted against material and manufacturing defects for two years from
date of delivery. Buyer agrees that if this product proves defective Chassis Plans. is only
obligated to repair, replace or refund the purchase price of this product at Chassis Plans’
discretion. The warranty is void if the product has been subjected to alteration, neglect,
misuse or abuse; if any repairs have been attempted by anyone other than Chassis Plans;
or if failure is caused by accident, acts of God, or other causes beyond the control of
Chassis Plans. Chassis Plans reserves the right to make changes or improvements in any
product without incurring any obligation to similarly alter products previously
purchased.
In no event shall Chassis Plans be liable for any defect in hardware or software or loss or
inadequacy of data of any kind, or for any direct, indirect, incidental or consequential
damages arising out of or in connection with the performance or use of the product or
information provided. Chassis Plans’ liability shall in no event exceed the purchase
price of the product purchased hereunder. The foregoing limitation of liability shall be
equally applicable to any service provided by Chassis Plans.
R
ETURN POLICY Products returned for repair must be accompanied by a Return Material Authorization
(RMA) number, obtained from Chassis Plans prior to return. Freight on all returned
items must be prepaid by the customer, and the customer is responsible for any loss or
damage caused by common carrier in transit. Items will be returned from Chassis Plans
via Ground, unless prior arrangements are made by the customer for an alternative
shipping method
To obtain an RMA number, call us at (858) 571-4330. We will need the following information:
Return company address and contact
Model name and model # from the label on the back of the board
Serial number from the label on the back of the board
Description of the failure
An RMA number will be issued. Mark the RMA number clearly on the outside of each
box, include a failure report for each board and return the product(s) to our San Diego,
CA facility:
Chassis Plans
8295 Aero Place, Suite 200
San Diego, CA 92123
Attn: Repair Department
(858) 571-4330
TRADEMARKS IBM, PC, VGA, EGA, OS/2 and PS/2 are trademarks or registered
trademarks of International Business Machines Corp.
AMI and AMIBIOS are trademarks of American Megatrends Inc.
Intel, Pentium and Celeron are registered trademarks of Intel Corporation.
ATI is a registered trademark of ATI Technologies Incorporated.
MS-DOS and Microsoft are registered trademarks of Microsoft Corp.
PICMG and the PICMG logo are registered trademarks of the PCI
Industrial Computer Manufacturers Group.
SCSISelect is a trademark of Adaptec, Inc.
All other brand and product names may be trademarks or registered
trademarks of their respective companies.
L
IABILITY
DISCLAIMER
This manual is as complete and factual as possible at the time of printing; however, the
information in this manual may have been updated since that time. Chassis Plans
reserves the right to change the functions, features or specifications of their products at
any time, without notice.
Copyright © 2004 by Chassis Plans. All rights reserved.
E-mail: Support@chassisplans.com
Web: www.chassisplans.com
Chassis Plans
8295 Aero Place • Suite 200 • San Diego, California 92123
Sales: (858) 571-4330 • Fax: (858) 571-6146 • Web: www.chassisplans.com
MX8 Technical Reference
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
SBC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
SBC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Bus Speed - PCI and PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Bus Speed - System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
DMA Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
BIOS (Flash). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
NetBurst Micro-Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
DDR Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
Error Checking and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
PCI-X/PCI Local Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
Ultra XGA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
System Hardware Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
PCI Ethernet Interfaces (Dual) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
Hub Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
PCI SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
Serial ATA/150 Ports (Dual) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
PCI Enhanced IDE Interfaces (Dual) . . . . . . . . . . . . . . . . . . . . . . . .1-10
Floppy Drive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
Enhanced Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10
PS/2 Mouse Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
Chassis Plans i
MX8 Technical Reference
Table of Contents
Specifications (continued)
Power Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11
Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12
Temperature/Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12
Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-13
Ethernet LEDs and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14
System BIOS Setup Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-16
ISA/PCI Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
ISA Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
ISA Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
ISA Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
PCI Local Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
PCI Local Bus Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
PCI Local Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
PCI Local Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
PCI Local Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .2-14
PICMG Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . .2-18
System BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
BIOS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Password Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
BIOS Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
Running AMIBIOS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
BIOS Setup Utility Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
BIOS Setup Utility Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
Security Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
Change Supervisor Password . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
Disabling Supervisor Password. . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Change User Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Clear User Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Boot Sector Virus Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Exit Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
Chassis Plansii
MX8 Technical Reference
Advanced Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
PCI Plug and Play Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Boot Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
Table of Contents
CPU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
IDE Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
IDE Device Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13
Floppy Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17
SuperIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19
Remote Access Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23
USB Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25
Boot Settings Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Boot Device Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
Hard Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9
Removable Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
CD/DVD Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13
Chipset Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
NorthBridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
SouthBridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
Appendix A - BIOS Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
BIOS Beep Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
BIOS Error Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2
Bootblock Initialization Code Checkpoints . . . . . . . . . . . . . . . . . . .A-6
Bootblock Recovery Code Checkpoints. . . . . . . . . . . . . . . . . . . . . .A-7
Post Code Checkpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-8
DIM Code Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-10
Additional Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-11
Chassis Plans iii
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MX8 Technical Reference
Copyright 2004 by Trenton Technology Inc. All rights reserved.
Chassis Plansiv
MX8 Technical Reference
HANDLING
PRECAUTIONS
S
OLDER-SIDE
COMPONENTS
_______________________________________________________________________
WA R NI N G : This product has components which may be damaged by electrostatic
discharge.
_______________________________________________________________________
To protect your single board computer (SBC) from electrostatic damage, be sure to
observe the following precautions when handling or storing the board:
• Keep the SBC in its static-shielded bag until you are ready to perform your
installation.
• Handle the SBC by its edges.
• Do not touch the I/O connector pins. Do not apply pressure or attach labels
to the SBC.
• Use a grounded wrist strap at your workstation or ground yourself
frequently by touching the metal chassis of the system before handling any
components. The system must be plugged into an outlet that is connected to
an earth ground.
• Use antistatic padding on all work surfaces.
• Avoid static-inducing carpeted areas.
This SBC has components on both sides of the PCB. It is important for you to observe
the following precautions when handling or storing the board to prevent solder-side
components from being damaged or broken off:
• Handle the board only by its edges.
• Store the board in padded shipping material or in an anti-static board rack.
• Do not place an unprotected board on a flat surface.
Chassis Plans v
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MX8 Technical Reference
Copyright 2004 by Trenton Technology Inc. All rights reserved.
Chassis Plansvi
Before You BeginMX8 Technical Reference
Before You Begin
INTRODUCTION It is important to be aware of the system considerations listed below before installing
your MX8 SBC. Overall system performance may be affected by incorrect usage of
these features.
MOUSE/KEYBOARD
“Y” CABLE
When using a “Y” cable attached to the bracket mounted mouse/keyboard mini Din
connector, be sure to use Chassis Plans’ “Y” cable, part number 5886-000. Using a nonChassis Plans cable may result in improper SBC operation.
DDR MEMORY The memory modules used in the MX8 may be PC2100, PC2700 or PC3200 ECC or
non-ECC, unbuffered DIMMs. If two modules of different speeds are used, the DIMMs
will operate in dual-channel mode at the speed of the slowest DIMM. If the modules are
different sizes, they will operate in single-channel mode. Registered DIMMs are not
supported. All memory modules must have gold contacts.
In addition, the DIMMs must have the following features:
• 184-pin with gold-plated contacts
• ECC (72-bit) or non-ECC (64-bit) DDR memory
• Unbuffered configuration
B
OOT FROM LAN The MX8 supports bootup from a LAN device. If you are not booting from a LAN
device, the boot from LAN options on the Boot Device Priority screen should always be
set to Disabled to eliminate unnecessary delays during the bootup process. This may be
done via the Boot Device Priority option on the Boot Setup screen of the BIOS Setup
Utility.
P
OWER
The following are typical values:
REQUIREMENTS
Processor
Speed
+5V * +12V ** +3.3V * -12V *
Intel® Pentium® 4 Processor - 533MHz FSB/512K cache:
2.8GHz
2.4GHz
Intel
2.5GHz
2.0GHz
* From backplane via PICMG connector.
** From ATX12V power supply or equivalent via P24 connector.
______________________________________________________________________
NOTE: The MX8 requires an additional on-board power connector due to the power
requirements of the Intel
+12V from an external power supply that conforms to the ATX12V power specification.
The external power supply must have a wattage rating of 250W or higher.
Chassis Plans
4.95 Amps
4.95 Amps
®
Celeron® Processor - 400MHz FSB/128K cache:
4.95 Amps
4.95 Amps
®
4.63 Amps
5.00 Amps
4.60 Amps
4.20 Amps
2.50 Amps
2.50 Amps
2.50 Amps
2.50 Amps
Pentium® 4 processor. This 4-pin connector (P24) requires
< 100 mAmps
< 100 mAmps
< 100 mAmps
< 100 mAmps
Before You Begin MX8 Technical Reference
The MX8 also requires that +3.3V must be applied to the backplane from the power
supply, as specified in the PCI Industrial Computer Manufacturers Group (PICMG
®
Specification. When using a backplane which is not a Chassis Plans product, check with
your backplane manufacturer to ensure that the backplane provides +3.3V to the SBC.
______________________________________________________________________
O
PERATING
TEMPERATURE
Adequate airflow is essential to ensure effective operation of the MX8. The following
are operating temperature requirements:
0
º C. to 45º C.
0º C. to 45º C. with 250 LFM of airflow (for processors with 800MHz FSB/1M
cache and 3.06GHz processor with 533MHz FSB/512K cache)
HYPER-THREADING The factory setting of the HyperThreading option in the system BIOS is Disabled.
This option may be set to Enabled for processors which support Hyper-Threading
functionality.
Hyper-Threading improves overall performance in many systems designed for multiprocessing, high-demand multi-tasking and multi-threaded applications. If you are using
a system which can take advantage of Hyper-Threading technology, you may use the
BIOS Setup Utility to change the setting of the HyperThreading option to Enabled.
This option is found on the CPU Configuration screen in the Advanced Setup section of
the BIOS Setup Utility.
®
Intel
recommends enabling Hyper-Threading on systems that use Microsoft®
Windows
®
XP® or Linux® 2.4.x operating systems.
)1.0
F
OR MORE
INFORMATION
For systems which use applications and operating systems which cannot take advantage
of Hyper-Threading technology, the HyperThreading option should remain Disabled.
Intel recommends disabling Hyper-Threading when using the following operating
systems: Microsoft Windows 98
®
IBM
OS/2® and any version of Linux before revision 2.4.x. These operating systems
®
, Windows NT®, Windows 2000®, Windows ME®,
are not optimized for Hyper-Threading technology and some applications may actually
experience some performance degradation.
For more information on any of these features, refer to the appropriate sections of the
MX8 Technical Reference Manual (#87-006243-000). The latest revision of this manual
may be found on Chassis Plans’ website - www.chassisplans.com.
Copyright 2004 by Trenton Technology Inc. All rights reserved.
Chassis Plans
SpecificationsMX8 Technical Reference
Chapter 1 Specifications
INTRODUCTION The MX8 full-featured PCI/ISA processors are single board computers (SBCs) which
feature the Intel® Pentium® 4 or Intel® Celeron® microprocessor, 400/533/800MHz
system bus, ATI Technologies® video interface, support for 2GB DDR memory, PCI
Local Bus, cache memory, floppy controller, dual Ultra ATA/100 EIDE interfaces,
optional Ultra160 SCSI controller, dual Gigabit Ethernet interfaces, dual Serial ATA
M
ODELS
ports, two serial ports, parallel port, speaker port and mouse/keyboard port on a single
ISA-size card. These single-slot high performance SBCs plug into PICMG
and PCI-X backplanes and provide full PC compatibility for the system expansion slots.
The MX8-NS models have all of the standard features of the MX8, except they do not
include the Adaptec SCSI controller or the Ultra160 SCSI port.
Model #
Model Name Speed
Intel® Pentium® 4 Processor - 800MHz FSB/1M cache:
S6240-409-xM
S6240-408-xM
S6240-407-xM
®
Intel
Pentium® 4 Processor - 533MHz FSB/512K cache:
S6240-108-xM
S6240-107-xM
S6240-106-xM
S6240-105-xM
S6240-104-xM
®
Intel
Celeron® Processor - 400MHz FSB/128K cache:
S6240-807-xM
S6240-806-xM
S6240-805-xM
S6240-804-xM
S6240-803-xM
S6240-802-xM
S6240-801-xM
S6240-800-xM
MX8/3.2G1
MX8/3.0G1
MX8/2.8G1
MX8/3.06EN
MX8/2.8EN
MX8/2.66EN
MX8/2.53EN
MX8/2.4EN
MX8/2.5C
MX8/2.4C
MX8/2.3C
MX8/2.2C
MX8/2.1C
MX8/2.0C
MX8/1.8C
MX8/1.7C
3.2GHz
3.0GHz
2.8GHz
3.06GHz
2.8GHz
2.66GHz
2.53GHz
2.4GHz
2.5GHz
2.4GHz
2.3GHz
2.2GHz
2.1GHz
2.0GHz
1.8GHz
1.7GHz
®
PCI/ISA
“No SCSI” Models:
®
Intel
Pentium® 4 Processor - 800MHz FSB/1M cache:
S6240-429-xM
S6240-428-xM
S6240-427-xM
®
Intel
Pentium® 4 Processor - 533MHz FSB/512K cache:
S6240-128-xM
S6240-127-xM
S6240-126-xM
S6240-125-xM
S6240-124-xM
Chassis Plans 1-1
MX8/3.2G1-NS
MX8/3.0G1-NS
MX8/2.8G1-NS
MX8/3.06EN-NS
MX8/2.8EN-NS
MX8/2.66EN-NS
MX8/2.53EN-NS
MX8/2.4EN-NS
3.2GHz
3.0GHz
2.8GHz
3.06GHz
2.8GHz
2.66GHz
2.53GHz
2.4GHz
Specifications MX8 Technical Reference
MODELS
(CONTINUED)
FEATURES • Intel® Pentium® 4 microprocessor
Model #
Model Name Speed
“No SCSI” Models (continued):
®
Intel
Celeron® Processor - 400MHz FSB/128K cache:
S6240-827-xM
S6240-826-xM
S6240-825-xM
S6240-824-xM
S6240-823-xM
S6240-822-xM
S6240-821-xM
S6240-820-xM
MX8/2.5C-NS
MX8/2.4C-NS
MX8/2.3C-NS
MX8/2.2C-NS
MX8/2.1C-NS
MX8/2.0C-NS
MX8/1.8C-NS
MX8/1.7C-NS
2.5GHz
2.4GHz
2.3GHz
2.2GHz
2.1GHz
2.0GHz
1.8GHz
1.7GHz
where xM indicates memory size (0M = 0MB memory,
64M =64MB memory, etc.)
• 3.2GHz, 3.0GHz or 2.8GHz with 1M cache and a 800MHz Front Side Bus
(FSB)
• 3.06GHz, 2.8GHz, 2.66GHz, 2.53GHz or 2.4GHz with 512K cache and a
533MHz FSB
®
or Intel
Celeron® microprocessor
• 2.5GHz, 2.4GHz, 2.3GHz, 2.2GHz, 2.1GHz, 2.0GHz, 1.8GHz or 1.7GHz
with 128K cache and a 400MHz FSB
• Intel 875P chipset with 400/533/800MHz system bus
• PCI Local Bus operating in 32-bit/33MHz mode
• Ultra XGA on-board video interface (ATI Technologies
®
)
• Supports off-board PCI option cards, dual PCI 10/100/1000Base-T Ethernet
controllers and optional on-board PCI Ultra160 SCSI controller - Adaptec
AIC-7892
• Dual Ethernet interfaces for use with 10/100/1000Base-T networks
• Dual Serial ATA ports support two independent SATA storage devices
• Memory error checking and correction (ECC) support
• Compatible with PCI Industrial Computer Manufacturers Group (PICMG) 1.0
Specification
• Supports up to 2GB of Double Data Rate (DDR) on-board memory
• Floppy drive and dual PCI EIDE Ultra ATA/100 drive interfaces
• Two serial ports and one parallel port
• Dual Universal Serial Bus (USB 2.0) support
• Automatic or manual peripheral configuration
Chassis Plans1-2
SpecificationsMX8 Technical Reference
FEATURES
(CONTINUED)
• Watchdog timer
• System hardware monitor
• Full PC compatibility
Chassis Plans 1-3
Specifications MX8 Technical Reference
SBC BLOCK
DIAGRAM
Chassis Plans1-4
SBC BOARD
LAYOUT
SpecificationsMX8 Technical Reference
Chassis Plans 1-5
Specifications MX8 Technical Reference
PROCESSOR • Intel® Pentium® 4 microprocessor
• 3.2GHz, 3.0GHz or 2.8GHz with 1M cache and a 800MHz Front Side Bus
(FSB)
• 3.06GHz, 2.8GHz, 2.66GHz, 2.53GHz or 2.4GHz with 512K cache and a
533MHz FSB
®
or Intel
• 2.5GHz, 2.4GHz, 2.3GHz, 2.2GHz, 2.1GHz, 2.0GHz, 1.8GHz or 1.7GHz
• Processor uses the mPGA 478 packaging
B
US INTERFACES ISA and PCI Local Bus compatible
DATA PATH DDR Memory - 64-bit (per channel)
PCI Bus - 32-bit or 64-bit
PCI-X Bus - 64-bit
Celeron® microprocessor
with 128K cache and a 400MHz FSB
BUS SPEED - PCI
AND PCI-X
BUS SPEED -
PCI - 33MHz or 66MHz
PCI-X - 33MHz or 66MHz
400/533/800MHz Front Side Bus
SYSTEM
MEMORY
INTERFACE
Dual Double Data Rate (DDR) memory channels for 2100MB/s, 2700MB/s or
3200MB/s memory bandwidth
SYSTEM BUS The Intel 875P chipset supports the system bus at 400MHz, 533MHz or 800MHz, which
provides a higher bandwidth path for transferring data between main memory/chipset
and the processor.
DMA CHANNELS The SBC is fully PC compatible with seven DMA channels, each supporting type F
transfers.
INTERRUPTS The SBC is fully PC compatible with interrupt steering for PCI plug and play compati-
bility.
BIOS (FLASH) The BIOS is an AMIBIOS with built-in advanced CMOS setup for system parameters,
peripheral management for configuring on-board peripherals and other system parameters. The Flash BIOS resides in the Intel 82802AC Firmware Hub (FWH). The BIOS
may be upgraded from floppy disk by pressing <Ctrl> + <Home> immediately after
reset or power-up with the floppy disk in drive A:. Custom BIOSs are available.
C
ACHE MEMORY The processor includes integrated on-die, 1MB 8-way set associative level two (L2)
cache, which implements the Advanced Transfer Cache architecture and runs at the full
speed of the processor core. Intel® Pentium® 4 processors provide either 512K or 1M of
L2 cache memory; Intel
®
Celeron® processors have a 128K L2 cache.
Chassis Plans1-6
SpecificationsMX8 Technical Reference
All processors include a 12K level 1 (L1) Execution Trace Cache. Processors which
have 1M of L2 cache memory have a 16K data cache; all other processors have an 8K
data cache.
NETBURST™
MICROARCHITECTURE
NetBurst micro-architecture defines the techniques Intel uses to enhance the processor’s
execution of the BIOS, operating system and application software. These techniques
include hyper-pipelined technology, a rapid execution engine, advanced dynamic
execution, enhanced floating point and multimedia unit and Streaming SIMD
Extensions 2 (SSE2). The processor’s system bus speed and memory cache are also part
of the NetBurst micro-architecture.
Hyper-pipelined technology doubles the pipeline depth inside the processor, which
enables more instructions to be loaded, resulting in higher core frequencies. Advanced
dynamic execution includes an improved speculative execution algorithm that minimizes
processor instruction misdirects and results in faster instruction execution.
The rapid execution engine enables the two arithmetic logic units (ALUs) of the
processor to operate at twice the core frequency. Many integer instructions can now
execute in half the internal core clock period, resulting in improved software execution
speeds.
NetBurst micro-architecture improvements in the floating point and multimedia unit
include making the registers 128 bits wide and adding a separate register for moving
data.
The SSE2 has 144 instructions which improve performance in secure transactions and
multimedia processing. These instructions are used for double-precision floating point,
SIMD integer and memory management improvements.
DDR M
EMORY The Double Data Rate (DDR) memory interface supports up to 2GB of memory and can
operate as either a single-channel (64-bit) or dual-channel (128-bit) DDR interface. Each
of the channels terminates in a dual in-line memory module (DIMM) socket. Installing
two DIMMs doubles the interface bandwidth. The System BIOS automatically detects
memory type, size and speed.
The SBC uses industry standard 72-bit wide ECC or 64-bit wide non-ECC gold finger
PC2100, PC2700 or PC3200 memory modules in two 184-pin sockets.
______________________________________________________________________
NOTE: Memory modules can be installed in one or both DIMM sockets. If two
modules of different speeds are used, the DIMMs will operate in dual-channel mode at
the speed of the slowest DIMM. If the modules are different sizes, they will operate in
single-channel mode. Registered DIMMs are not supported. All memory modules must
have gold contacts.
______________________________________________________________________
The SBC supports DIMMs which are PC2100/PC2700/PC3200 compliant and have the
following features:
• 184-pin with gold-plated contacts
• ECC (72-bit) or non-ECC (64-bit) DDR memory
• Unbuffered configuration
Chassis Plans 1-7
Specifications MX8 Technical Reference
The following DIMM sizes are supported:
DIMM
Size
DIMM Type ECC
64MB Unbuffered 8M x 72
128MB Unbuffered 16M x 72
256MB Unbuffered 32M x 72
512MB Unbuffered 64M x 72
1GB Unbuffered 128M x 72
E
RROR CHECKING
AND CORRECTION
The memory interface supports ECC modes via BIOS setting for multiple-bit error
detection and correction of all errors confined to a single nibble.
ISA BUS
INTERFACE
PCI-X/PCI L
OCAL
BUS INTERFACES
U
NIVERSAL SERIAL
BUS (USB)
U
LTRA XGA
INTERFACE
The ISA bus interface supports legacy ISA slots, but does not support ISA Bus
Mastering, 16-bit I/O and 16-bit memory accesses. When a 16-bit access is executed to
the ISA bus, the transfer is divided into two 8-bit accesses. If the ISA option card being
used only operates in word (16-bit) mode, transfer data will be missed. If the ISA option
card supports both byte (8-bit) mode and word mode, the data transfer will be correct,
but performance will be reduced.
The SBC is fully compliant with the PCI Local Bus 2.1 Specification. The PCI Local
Bus is 32 bits wide and runs at 33MHz. It interfaces to one of the on-board 10/100/
1000Base-T Ethernet controllers (Intel 82540) and optional Ultra160 SCSI controller.
The PCI-X/PCI bus interface connects the SBC’s I/O Controller Hub directly to the
backplane and is capable of running at a 33MHz or 66MHz bus speed. This interface is
compliant with the PCI Industrial Computer Manufacturers Group (PICMG) 1.0 Specification.
The SBC supports two high-speed USB 2.0 ports for data transfers up to 480Mbit/sec. It
also supports USB 1.1 devices for data transfers at 12 or 1.5Mbit/sec. The Universal
Serial Bus (USB) is an interface allowing for connectivity to many standard PC peripherals via an external port.
The ATI Technologies M6-C16H video controller enables 2D/3D video acceleration and
provides 16MB of integrated video DDR memory. The video controller’s DVI
compliant 165MHz TMDS transmitter supports pixel resolutions from VGA (640 x 480)
up to UXGA (1600 x 1200).
Software drivers are available for most popular operating systems.
SYSTEM
HARDWARE
The system hardware monitoring system monitors system voltages, temperature and fan
speeds.
MONITOR
The circuitry is based on Winbond’s W83783S hardware monitoring IC that is interfaced
via the system’s SMBus. System voltages of +12V, +5V, +3.3V, +2.5V, VCCORE
(processor voltage) and -12V are monitored. Each of these six voltages has programmable “high” and “low” watchdog limits. Also monitored are the processor die temperature and the fan speed associated with the processor’s active heatsink thermal solution.
Programmable watchdog limits are also associated with fan speed RPMs. When any of
these programmed limits are exceeded, monitor software can be used to report the outof-limit condition.
Chassis Plans1-8
SpecificationsMX8 Technical Reference
The System Hardware Monitor connector (P18) provides an external interface for user
functionality. Pin assignments for this connector are as follows:
Pin #/Definition
Pin 1 - GND System Ground
Pin 2 - GPO General Purpose Output
Pin 3 - CI Chassis Intrusion Input
Pin 4 - OVT Over Temperature
Description
Active low open drain output. This multifunction output is controlled by the W38383S’s
configuration register at offset 40(h) and the
control register at 4D(h). It can be used as a
general-purpose output or programmed to
provide a beep function that can be used as a
watchdog warning signal. This output is open
drain.
Active low input from an external circuit, which
can be used to indicate a chassis intrusion event.
This input line is connected directly to the
ICH’s System Management Interface’s
INTRUDER# input. It can be set to disable the
system if the chassis is open or can be used as a
general-purpose input if intruder detection is
not used.
PCI ETHERNET
INTERFACES
(DUAL)
This active low, open drain output can be used
to indicate that an over-temperature condition
exists.
The SBC supports two Ethernet interfaces. LAN 1 (P16) is implemented using an Intel
82547GI 10/100/1000Base-T Ethernet PHY and LAN 2 (P1) is implemented using an
Intel 82540 10/100/1000Base-T Ethernet controller. Both of these controllers support
Gigabit, 10Base-T and 100Base-TX Fast Ethernet modes and are compliant with IEEE
802.3.
The main components of each interface are:
• Intel 82547GI or Intel 82540 for 10/100/1000-Mb/s media access control
(MAC) with PHY, a serial ROM port and a PCI Bus Master interface
• Serial ROM for storing the Ethernet address and the interface configuration
and control data
• Integrated RJ-45/Magnetics module connector on the SBC's I/O bracket for
direct connection to the network. The connector requires a category 5
(CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network
connection or a category3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s
network connection. A category 5e (CAT5e) or higher UTP 2-pair cable is
recommended for a 1000-Mb/s (Gigabit) network connection.
Chassis Plans 1-9
Specifications MX8 Technical Reference
• Link status and activity LEDs on the I/O bracket for status indication (See
Ethernet LEDs and Connectors later in this chapter.)
Software drivers are supplied for most popular operating systems.
HUB INTERFACE The Intel 875P chipset utilizes a dedicated hub interface connection between the 875P
memory controller hub (MCH) and the I/O controller hub (ICH). The purpose of the hub
interface is to provide efficient, high-speed communication between chipset components
in order to support high-speed I/O applications. It is a parity-protected, 266MB/s pointto-point hub interface and uses an 8-bit 66MHz base clock running at 4x.
PCI SCSI
I
NTERFACE
(OPTIONAL)
S
ERIAL ATA/150
PORTS (DUAL)
PCI E
NHANCED
IDE INTERFACES
(DUAL)
The SCSI interface supports Ultra160 SCSI data transfer using Adaptec’s AIC-7892
SCSI controller, which supports SCSI data transfer up to 160MB per second. The
interface supports up to 15 SCSI devices, complies with the SPI-3 standard and is
compatible with both single-ended and Low Voltage Differential (LVD) SCSI I/O. The
Ultra160 features of this channel include double-edge clocking, domain validation and
cyclical redundancy checking.
Active termination is provided with terminator voltage protected by a self-resetting fuse.
A jumper (JU9) is provided to disable the termination (see the Configuration Jumpers
section later in this chapter). Software drivers are available for most popular operating
systems.
The Adaptec SCSISelect Configuration Utility allows you to view and/or change the
default configuration settings for the Ultra160 SCSI adapter. You may press <Ctrl> +
<A> to invoke the configuration utility.
The primary and secondary Serial ATA (SATA) ports on the MX8 comply with the SATA
1.0 specification and support two independent SATA storage devices such as hard disks
and CD-RW devices. SATA technology provides lower pin counts, reduced signaling
voltages, simplified cabling, CRC error detection and hot-plug support. SATA produces
higher performance interfacing by providing data transfer rates up to 150MB per second
on each port.
Dual high performance PCI Bus Master EIDE interfaces are capable of supporting two
IDE disk drives each in a master/slave configuration. The interfaces support Ultra
ATA/100 with synchronous ATA mode transfers up to 100MB per second. Ultra
ATA/100 cables must be used with Ultra ATA/100 drives.
FLOPPY DRIVE
INTERFACE
The SBC supports two floppy disk drives. Drives can be 360K to 2.88MB, in any
combination.
SERIAL INTERFACE Two high-speed FIFO (16C550) serial ports with independently programmable baud
rates are supported. The IRQ for each serial port has BIOS selectable addressing.
ENHANCED
PARALLEL
INTERFACE
The SBC provides a PC/AT compatible bidirectional parallel port and supports enhanced
parallel port (EPP) mode and extended capabilities port (ECP) mode. The ECP mode is
IEEE 1284 compliant. The IRQ for the parallel port has BIOS selectable addressing.
Chassis Plans1-10
SpecificationsMX8 Technical Reference
PS/2 MOUSE
INTERFACE
The SBC is compatible with a PS/2-type mouse. The mouse connection can be made by
using either the PS/2 mouse header or the bracket mounted mouse/keyboard mini DIN
connector. The mouse may be connected directly to the mini DIN connector or to the
"mouse" side of the "Y" adapter. Mouse voltage is protected by a self-resetting fuse.
KEYBOARD
INTERFACE
The SBC is compatible with an AT-type keyboard. The keyboard connection can be
made by using either the keyboard header or the "keyboard" side of the "Y" adapter
plugged into the bracket mounted mouse/keyboard mini DIN connector. Keyboard
voltage is protected by a self-resetting fuse.
W
ATCHDOG TIMER The watchdog timer is a hardware timer which resets the SBC if the timer is not
refreshed by software periodically. The timer is typically used to restart a system in
which an application becomes hung on an external event. When the application is hung,
it no longer refreshes the timer. The watchdog timer then times out and resets the SBC.
The watchdog timer (WDT) is integrated into the E6300ESB I/O Controller Hub (ICH)
and provides a resolution that ranges from 1 msecond to 10 minutes. The WDT provides
a two-stage timer implementation: the first stage can be used to generate an IRQ, SMI or
SCI interrupt after the programmed time interval has expired; the second stage can be
used to generate a hard system reset.
The WDT uses a 35-bit down-counter, which is loaded with the value from the first
preload register. The timer is then enabled and starts its down counting, which is the first
stage. When the host fails to reload the WDT before the 35-bit down-counter reaches
zero, the WDT generates an internal interrupt. After the interrupt is generated, the WDT
loads the value from the second preload register into the 35-bit down-counter and starts
counting down. The WDT is now in the second stage. If the host fails to reload the
WDT before the second stage times out, a system RESET is generated.
P
OWER FAIL
DETECTION
A hardware reset is issued when any of the monitored voltages drops below its specified
nominal low voltage limit.
The monitored voltages and their nominal low limits are listed below.
Monitored
Vo l t a g e
+5V
+3.3V
+1.2V
+1.25V
+2.5V
B
ATTERY A built-in lithium battery is provided, for ten years of data retention for CMOS memory.
Nominal
Low Limit
4.5 volts
2.97 volts
1.056 volts
1.1 volt
2.452 volts
Voltage Source
System Power Supply
System Power Supply
On-Board Regulator
On-Board Regulator
On-Board Regulator
______________________________________________________________________
CAUTION: There is a danger of explosion if the battery is incorrectly replaced.
Replace it only with the same or equivalent type recommended by the manufacturer.
Dispose of used batteries according to the manufacturer's instructions.
______________________________________________________________________
Chassis Plans 1-11
Specifications MX8 Technical Reference
POWER
REQUIREMENTS
The following are typical values:
Processor
Speed
+5V * +12V ** +3.3V * -12V *
Intel® Pentium® 4 Processor - 533MHz FSB/512K cache:
2.8GHz
2.4GHz
®
Intel
2.5GHz
2.0GHz
4.95 Amps
4.95 Amps
4.63 Amps
5.00 Amps
2.50 Amps
2.50 Amps
Celeron® Processor - 400MHz FSB/128K cache:
4.95 Amps
4.95 Amps
4.60 Amps
4.20 Amps
2.50 Amps
2.50 Amps
< 100 mAmps
< 100 mAmps
< 100 mAmps
< 100 mAmps
* From backplane via PICMG connector.
** From ATX12V power supply or equivalent via P24 connector.
______________________________________________________________________
NOTE: The MX8 requires an additional on-board power connector due to the power
requirements of the Intel
®
Pentium® 4 processor. This 4-pin connector (P24) requires
+12V from an external power supply that conforms to the ATX12V power specification.
The external power supply must have a wattage rating of 250W or higher.
The MX8 also requires that +3.3V must be applied to the backplane from the power
supply, as specified in the PCI Industrial Computer Manufacturers Group (PICMG
®
)1.0
Specification. When using a backplane which is not a Chassis Plans product, check with
your backplane manufacturer to ensure that the backplane provides +3.3V to the SBC.
______________________________________________________________________
TEMPERATURE/
ENVIRONMENT
Operating Temperature: 0º C. to 45º C.
0º C. to 45º C. with 250 LFM of airflow
(for processors with 800MHz FSB/1M cache and
3.06GHz processor with 533MHz FSB/512K cache)
Storage Temperature: - 40º C. to 70º C.
Humidity: 5% to 90% non-condensing
Chassis Plans1-12
SpecificationsMX8 Technical Reference
CONFIGURATION
JUMPERS
The setup of the configuration jumpers on the SBC is described below. * indicates the
default value of each jumper.
______________________________________________________________________
NOTE: For two-position jumpers (3-post), "TOP" is toward the memory sockets;
"BOTTOM" is toward the edge fingers.
______________________________________________________________________
Jumper
JU5/JU7 Speed LED - LAN 1/LAN 2
Description
These jumpers are used in conjunction with the Link/Speed
LEDs for LAN 1 (JU5) and LAN 2 (JU7). The LEDs are
located on the SBC’s LAN connectors. For further information, see the Ethernet LEDs and Connectors section below.
Install to use the Link/Speed LED to indicate that the Ethernet
interface has a valid link at either 1000-Mb/s or 100-Mb/s.
Green = valid link at 1000-Mb/s *
Orange = valid link at 100-Mb/s
Remove to use the Link/Speed LED to indicate that the
Ethernet interface has a valid link at either 100-Mb/s or
10-Mb/s.
Orange = valid link at 100-Mb/s
Green = valid link at 10-Mb/s
JU8 Password Clear
Install for one power-up cycle to reset the password to the
default (null password).
Remove for normal operation. *
JU9 SCSI Termination
This jumper may be used to enable or disable on-board active
termination for the Ultra160 SCSI interface.
Install on the TOP to enable active termination. *
Install on the BOTTOM to allow the AIC-7892 to control
termination.
Remove to disable active termination.
Chassis Plans 1-13
Specifications MX8 Technical Reference
CONFIGURATION
JUMPERS
(CONTINUED)
Jumper
Description
JU10/JU11 System Flash ROM Operational Modes
The Flash ROM has two programmable sections: the Boot
Block for “flashing” in the BIOS and the Main Block for the
executable BIOS and PnP parameters. Normally only the
Main Block is updated when a new BIOS is flashed into the
system.
ETHERNET LEDS
AND CONNECTORS
JU10
JU11
All Blocks Write Enabled Remove * Remove *
Boot Block Write Protected Install Remove
Block 2-16 Write Protected Remove Install
JU12 CMOS Clear
Install on the TOP to operate. *
Install on the BOTTOM to clear.
__________________________________________________
NOTE: The CMOS Clear jumper works on power-up. To
clear the CMOS, power down the system, install the jumper,
then turn the power back on. Wait for at least two seconds and
turn the power off. Then remove the jumper and turn the
power on. When AMIBIOS displays the "CMOS Settings
Wrong" message, press F1 to go into the BIOS Setup Utility,
where you may reenter your desired BIOS settings, load
optimal defaults or load failsafe defaults.
__________________________________________________
Each Ethernet interface has two LEDs for status indication and an RJ-45 network
connector.
LED/Connector
Activity LED Orange LED which indicates network activity. This is the
Off Indicates there is no current network transmit or receive
On (flashing) Indicates network transmit or receive activity.
Description
upper LED on the LAN connector (i.e., toward the
memory sockets).
activity.
Chassis Plans1-14
ETHERNET LEDS
AND CONNECTORS
(CONTINUED)
SpecificationsMX8 Technical Reference
LED/Connector
Link/Speed LED Bi-color (green/orange) LED which identifies the link
Green Indicates a valid link at either 1000-Mb/s or 10-Mb/s,
Orange Indicates a valid link at 100-Mb/s, regardless of the
Description
status and connection speed. This is the lower LED on the
LAN connector (i.e., toward the edge connectors).
depending on the setting of the associated Speed LED
jumper (JU5 or JU7).
setting of the associated Speed LED jumper (JU5 or JU7).
______________________________________________
NOTE: For further information on the Speed LED
jumpers, see the Configuration Jumpers section earlier in
this chapter.
______________________________________________
SYSTEM BIOS
SETUP UTILITY
RJ-45 Network
Connector
The RJ-45 network connector requires a category 5
(CAT5) unshielded twisted-pair (UTP) 2-pair cable for a
100-Mb/s network connection or a category 3 (CAT3) or
higher UTP 2-pair cable for a 10-Mb/s network
connection. A category 5e (CAT5e) or higher UTP 2-pair
cable is recommended for a 1000-Mb/s (Gigabit) network
connection.
The System BIOS is an AMIBIOS with a ROM-resident setup utility. The BIOS Setup
Utility allows you to select to the following categories of options:
• Main Menu
• Advanced Setup
• PCIPnP Setup
• Boot Setup
• Security Setup
• Chipset Setup
• Exit
Each of these options allows you to review and/or change various setup features of your
system. Details are provided in the following chapters of this manual.
Chassis Plans 1-15
Specifications MX8 Technical Reference
CONNECTORS ______________________________________________________________________
NOTE: Pin 1 on the connectors is indicated by the square pad on the PCB.
______________________________________________________________________
P1 - 10/100/1000Base-T Ethernet Connector - LAN 2
8 pin shielded RJ-45 connector, Belfuse #0826-1X1T-23
Signal
Pin
1
TRP1+
2
TRP1-
3
TRP2+
4
TRP3+
5
TRP3-
6
TRP2-
7
TRP4+
8
TRP4-
P3 - Floppy Drive Connector
34 pin dual row header, Amp #103308-7
Signal
Pin
1
Gnd
3
Gnd
5
Gnd
7
Gnd
9
Gnd
11
Gnd
13
Gnd
15
Gnd
17
Gnd
19
Gnd
21
Gnd
23
Gnd
25
Gnd
27
Gnd
29
Gnd
31
Gnd
33
Gnd
P4A - Keyboard Header
5 pin single row header, Amp #640456-5
Pin
Signal
1
Kbd Clock
2
Kbd Data
3
Key
4
Kbd Gnd
5
Kbd Power (+5V fused) with self-resetting fuse
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Signal
N-RPM
NC
D-Rate0
P-Index
N-Motoron 1
N-Drive Sel2
N-Drive Sel1
N-Motoron 2
N-Dir
N-Stop Step
N-Write Data
N-Write Gate
P-Track 0
P-Write Protect
N-Read Data
N-Side Select
Disk Chng
Chassis Plans1-16
CONNECTORS
(CONTINUED)
P5 - Speaker Port Connector
4 pin single row header, Amp #640456-4
Pin
Signal
1
Speaker Data
2
Key
3
Gnd
4
+5V
P6 - Serial Port 1 Connector
10 pin dual row header, Amp #103308-1
SpecificationsMX8 Technical Reference
Signal
Pin
1
Carrier Detect
3
Receive Data-I
5
Transmit Data-O
7
Data Terminal Ready-O
9
Signal Gnd
P7 - Serial Port 2 Connector
10 pin dual row header, Amp #103308-1
Pin
Signal
1
Carrier Detect
3
Receive Data-I
5
Transmit Data-O
7
Data Terminal Ready-O
9
Signal Gnd
P8 - Parallel Port Connector
26 pin dual row header, Amp #103308-6
Signal
Pin
1
Strobe
3
Data Bit 0
5
Data Bit 1
7
Data Bit 2
9
Data Bit 3
11
Data Bit 4
13
Data Bit 5
15
Data Bit 6
17
Data Bit 7
19
ACK
21
Busy
23
Paper End
25
Slct
Pin
Signal
2
Data Set Ready-I
4
Request to Send-O
6
Clear to Send-I
8
Ring Indicator-I
10
NC
Signal
Pin
2
Data Set Ready-I
4
Request to Send-O
6
Clear to Send-I
8
Ring Indicator-I
10
NC
Signal
Pin
2
Auto Feed XT
4
Error
6
Init
8
Slct In
10
Gnd
12
Gnd
14
Gnd
16
Gnd
18
Gnd
20
Gnd
22
Gnd
24
Gnd
26
NC
Chassis Plans 1-17
Specifications MX8 Technical Reference
CONNECTORS
(CONTINUED)
P9 - PS/2 Mouse and Keyboard Connector
6 pin mini DIN, Kycon #KMDG-6S-B4T
Signal
Pin
1
Ms Data
2
Kbd Data
3
Gnd
4
Power (+5V fused) with self-resetting fuse
5
Ms Clock
6
Kbd Clock
P9A - PS/2 Mouse Header
6 pin single row header, Amp #640456-6
Pin
Signal
1
Ms Data
2
Reserved
3
Gnd
4
Power (+5V fused) with self-resetting fuse
5
Ms Clock
6
Reserved
P10 - External Reset Connector
2 pin single row header, Amp #640456-2
Signal
Pin
1
External Reset In (Low Active)
2
Gnd
P11 - Primary IDE Hard Drive Connector
40 pin dual row header, 3M #30340-6002HB
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Signal
Reset
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Gnd
DRQ 0
IOW
IOR
IORDY
DACK 0
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Signal
Gnd
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
NC
Gnd
Gnd
Gnd
SELPDP
Gnd
Chassis Plans1-18
CONNECTORS
(CONTINUED)
SpecificationsMX8 Technical Reference
P11 - Primary IDE Hard Drive Connector (continued)
Pin
31
33
35
37
39
Signal
IRQ 14
Add 1
Add 0
CS 1P
IDEACTP
Pin
32
34
36
38
40
Signal
NC
PCBL DET *
Add 2
CS 3P
Gnd
P11A - Secondary IDE Hard Drive Connector
40 pin dual row header, 3M #30340-6002HB
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
Reset
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Gnd
DRQ 1
IOW
IOR
IORDY
DACK 1
IRQ 15
Add 1
Add 0
CS 1S
IDEACTS
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal
Gnd
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
NC
Gnd
Gnd
Gnd
SELPDS
Gnd
NC
SCBL DET *
Add 2
CS 3S
Gnd
* For ATA/66 and ATA/100 drives, which should be set for Cable Select for
proper speed operation. If other drives are detected, pin definition is Gnd.
P12 - Hard Drive LED Connector
Chassis Plans 1-19
4 pin single row header, Amp #640456-4
Signal
Pin
1
LED +
2
LED -
3
LED -
4
LED +
Specifications MX8 Technical Reference
CONNECTORS
(CONTINUED)
P13 - Ultra160 SCSI Connector
68 pin high density connector, Amp #749069-7
Signal
Pin
1
SCD12
2
SCD13
3
SCD14
4
SCD15
5
SCDPH
6
SCD0
7
SCD1
8
SCD2
9
SCD3
10
SCD4
SCD5
11
SCD6
12
SCD7
13
SCDPL
14
Gnd
15
DIFSENSE
16
TERMPWR
17
TERMPWR
18
NC
19
Gnd
20
SCATN
21
Gnd
22
SCBSY
23
SCACK
24
SCRST
25
SCMSG
26
SCSEL
27
SCCD
28
SCREQ
29
SCIO
30
SCD8
31
SCD9
32
SCD10
33
SCD11
34
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
SCD#12
SCD#13
SCD#14
SCD#15
SCDPH#
SCD#0
SCD#1
SCD#2
SCD#3
SCD#4
SCD#5
SCD#6
SCD#7
SCDPL#
Gnd
Gnd
TERMPWR
TERMPWR
NC
Gnd
SCATN#
Gnd
SCBSY#
SCACK#
SCRST#
SCMSG#
SCSEL#
SCCD#
SCREQ#
SCIO#
SCD#8
SCD#9
SCD#10
SCD#11
Chassis Plans1-20
CONNECTORS
(CONTINUED)
P15 - Video Interface Connector
15 pin connector, Amp #1-1470250-3
Pin
Signal
Pin
11
12
13
14
15
Signal
NC
EEDI
HSYNC
VSYNC
EECS
Pin Signal
6Gnd
1Red
7Gnd
2 Green
8Gnd
3Blue
9+5V
4NC
10 Gnd
5Gnd
P16 - 10/100/1000Base-T Ethernet Connector - LAN 1
8 pin shielded RJ-45 connector, Belfuse #0826-1X1T-23
Signal
Pin
1
TRP1+
2
TRP1-
3
TRP2+
4
TRP3+
5
TRP3-
6
TRP2-
7
TRP4+
8
TRP4-
SpecificationsMX8 Technical Reference
P17 - Universal Serial Bus (USB) Connector
8 pin dual row header, Molex #702-46-0821
(+5V fused with self-resetting fuses)
Pin
Signal
1
+5V-USB0
3
USB0-
5
USB0+
7
Gnd-USB0
P18 - System Hardware Monitor Connector
4 pin single row header, Amp #640456-4
Signal
Pin
1
Gnd
2
GPO (General Purpose Output)
3
CI (Chassis Intrusion Input)
4
OVT (Over Temperature)
Pin
2
4
6
8
Signal
+5V-USB1
USB1USB1+
Gnd-USB1
Chassis Plans 1-21
Specifications MX8 Technical Reference
CONNECTORS
(CONTINUED)
P19 - CPU Fan
3 pin single row header, Molex #22-23-2031
Pin
Signal
1
Gnd
2
+12V
3
FanTach
P21 - Power Good LED
2 pin single row header, Amp #640456-2
Signal
Pin
1
LED -
2
LED +
P22 - System Management Bus Connector
2 pin single row header, Amp #640456-2
Pin
Signal
1
SMB Clock
2
SMB Data
P24 - +12V VRM Power Input
4 pin header, Molex #39-29-3046
Signal
Pin
1
Gnd
2
Gnd
3
+12V
4
+12V
P27 - SATA Port 1
7 pin vertical connector, Molex #67491-0031
Pin
Signal
1
Gnd
2
TX+
3
TX-
4
Gnd
5
RX-
6
RX+
7
Gnd
Chassis Plans1-22
CONNECTORS
(CONTINUED)
P28 - SATA Port 2
7 pin vertical connector, Molex #67491-0031
Pin
Signal
1
Gnd
2
TX+
3
TX-
4
Gnd
5
RX-
6
RX+
7
Gnd
SpecificationsMX8 Technical Reference
Chassis Plans 1-23
Specifications MX8 Technical Reference
This page intentionally left blank.
Copyright 2004 by Trenton Technology Inc. All rights reserved.
Chassis Plans1-24
Chapter 2 ISA/PCI Reference
ISA BUS PIN
NUMBERING
62-pin ISA Bus
Connector
ISA/PCI ReferenceMX8 Technical Reference
Component Side
of Board
36-pin ISA Bus
Connector
Chassis Plans 2-1
ISA/PCI Reference MX8 Technical Reference
ISA BUS PIN
ASSIGNMENTS
The following tables summarize pin assignments for the Industry Standard Architecture
(ISA) Bus connectors.
I/O Pin Signal Name I/O I/O Pin Signal Name I/O
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
IOCHK#
D7
D6
D5
D4
D3
D2
D1
D0
CHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
Gnd
RESDRV
+5V
IRQ9
-5V
DRQ2
-12V
NOWS#
+12V
Gnd
SMWTC#
SMRDC#
IOWC#
IORC#
DAK3#
DRQ3
DAK1#
DRQ1
REFRESH#
BCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DAK2#
T-C
BALE
+5V
OSC
Gnd
Ground
O
Power
I
Power
I
Power
I
Power
Ground
O
O
I/O
I/O
O
I
O
I
I/O
O
I
I
I
I
I
O
O
O
Power
O
Ground
I/O Pin Signal Name I/O I/O Pin Signal Name I/O
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
SBHE#
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MRDC#
MWTC#
D8
D9
D10
D11
D12
D13
D14
D15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
M16#
IO16#
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DAK0#
DRQ0
DAK5#
DRQ5
DAK6#
DRQ6
DAK7#
DRQ7
+5V
Master16#
Gnd
I
I
I
I
I
I
I
O
I
O
I
O
I
O
I
Power
I
Ground
Chassis Plans2-2
ISA/PCI ReferenceMX8 Technical Reference
ISA BUS SIGNAL
DESCRIPTIONS
The following is a description of the ISA Bus signals. All signal lines are TTLcompatible.
AEN (O)
Address Enable (AEN) is used to degate the microprocessor and other devices from the I/O
channel to allow DMA transfers to take place. When this line is active, the DMA controller has
control of the address bus, the data-bus Read command lines (memory and I/O), and the Write
command lines (memory and I/O).
BALE (O) (Buffered)
Address Latch Enable (BALE) is provided by the bus controller and is used on the system board
to latch valid addresses and memory decodes from the microprocessor. It is available to the I/O
channel as an indicator of a valid microprocessor or DMA address (when used with AEN).
Microprocessor addresses SA[19::0] are latched with the falling edge of BALE. BALE is forced
high during DMA cycles.
BCLK (O)
BCLK is the system clock. The clock has a 50% duty cycle. This signal should only be used for
synchronization. It is not intended for uses requiring a fixed frequency.
CHRDY (I)
I/O Channel Ready (CHRDY) is pulled low (not ready) by a memory or I/O device to lengthen I/
O or memory cycles. Any slow device using this line should drive it low immediately upon
detecting its valid address and a Read or Write command. Machine cycles are extended by an
integral number of clock cycles. This signal should be held low for no more than 2.5 microseconds.
D[15::0] (I/O)
Data signals D[15::0] provide bus bits 15 through 0 for the microprocessor, memory, and I/O
devices. D15 is the most-significant bit and D0 is the least-significant bit. All 8-bit devices on
the I/O channel should use D[7::0] for communications to the microprocessor. The 16-bit
devices will use D[15::0]. To support 8-bit devices, the data on D[15::8] will be gated to D[7::0]
during 8-bit transfers to these devices. 16-bit microprocessor transfers to 8-bit devices will be
converted to two 8-bit transfers.
DAK[7::5]#, DAK[3::0]# (O)
DMA Acknowledge DAK[7::5]# and DAK[3::0]# are used to acknowledge DMA requests
DRQ[7::5] and DRQ[3::0]. They are active low.
DRQ[7::5], DRQ[3::0] (I)
DMA Requests DRQ[7::5] and DRQ[3::0] are asynchronous channel requests used by
peripheral devices and the I/O channel microprocessors to gain DMA service (or control of the
system). They are prioritized, with DRQ0 having the highest priority and DRQ7 having the
lowest. A request is generated by bringing a DRQ line to an active level. A DRQ line must be
held high until the corresponding DMA Request Acknowledge (DAK) line goes active.
DRQ[3::0] will perform 8-bit DMA transfers; DRQ[7::5] will perform 16-bit transfers.
Chassis Plans 2-3
ISA/PCI Reference MX8 Technical Reference
IO16# (I)
I/O 16-bit Chip Select (IO16#) signals the system board that the present data transfer is a 16-bit,
1 wait-state, I/O cycle. It is derived from an address decode. IO16# is active low and should be
driven with an open collector or tri-state driver capable of sinking 20 mAmps.
IOCHK# (I)
I/O Channel Check (IOCHK#) provides the system board with parity (error) information about
memory or devices on the I/O channel. When this signal is active, it indicates an uncorrectable
system error.
IORC# (I/O)
I/O Read (IORC#) instructs an I/O device to drive its data onto the data bus. It may be driven by
the system microprocessor or DMA controller, or by a microprocessor or DMA controller
resident on the I/O channel. This signal is active low.
IOWC# (I/O)
I/O Write (IOWC#) instructs an I/O device to read the data on the data bus. It may be driven by
any microprocessor or DMA controller in the system. This signal is active low.
IRQ[15::14], IRQ[12::9], IRQ[7::3] (I)
Interrupt Requests IRQ[15::14], IRQ[12::9] and IRQ[7::3] are used to signal the microprocessor
that an I/O device needs attention. The interrupt requests are prioritized, with IRQ[15::14] and
IRQ[12::9] having the highest priority (IRQ9 is the highest) and IRQ[7::3] having the lowest
priority (IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from
low to high. The line must be held high until the microprocessor acknowledges the interrupt
request (Interrupt Service routine).
LA[23::17] (I/O)
These signals (unlatched) are used to address memory and I/O devices within the system.
They give the system up to 16MB of addressability. These signals are valid when BALE is high.
LA[23::17] are not latched during microprocessor cycles and therefore do not stay valid for the
whole cycle. Their purpose is to generate memory decodes for 1 wait-state memory cycles.
These decodes should be latched by I/O adapters on the falling edge of BALE. These signals
also may be driven by other microprocessors or DMA controllers that reside on the I/O channel.
M16# (I)
M16# Chip Select signals the system board if the present data transfer is a 1<N>wait-state, 16bit, memory cycle. It must be derived from the decode of LA[23::17]. M16# should be driven
with an open collector or tri-state driver capable of sinking 20 mAmps.
Master16# (I)
Master16# is used with a DRQ line to gain control of the system. A processor or DMA controller
on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DAK#.
Upon receiving the DAK#, an I/O microprocessor may pull Master16# low, which will allow it to
control the system address, data, and control lines (a condition known as tri-state). After
Master16# is low, the I/O microprocessor must wait one system clock period before driving the
address and data lines, and two clock periods before issuing a Read or Write command. If this
signal is held low for more than 15<N>microseconds, system memory may be lost because of a
lack of refresh.
Chassis Plans2-4
ISA/PCI ReferenceMX8 Technical Reference
NOWS# (I)
The No Wait State (NOWS#) signal tells the microprocessor that it can complete the present bus
cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit
device without wait cycles, NOWS# is derived from an address decode gated with a Read or
Write command. In order to run a memory cycle to an 8-bit device with a minimum of two wait
states, NOWS# should be driven active on system clock after the Read or Write command is
active gated with the address decode for the device. Memory Read and Write commands to a
8-bit device are active on the falling edge of the system clock. NOWS# is active low and should
be driven with an open collector or tri-state driver capable of sinking 20 mAmps.
OSC (O)
Oscillator (OSC) is a high-speed clock with a 70-nanosecond period (14.31818 MHz). This
signal is not synchronous with the system clock. It has a 50% duty cycle.
REFRESH# (I/O)
The REFRESH# signal is used to indicate a refresh cycle and can be driven by a microprocessor on the I/O channel.
RESDRV (O)
Reset Drive (RESDRV) is used to reset or initialize system logic at power-up time or during a
low line-voltage outage. This signal is active high.
SA[19::0] (I/O)
Address bits SA[19::0] are used to address memory and I/O devices within the system. These
twenty address lines, in addition to LA[23::17], allow access of up to 16MB of memory.
SA[19::0] are gated on the system bus when BALE is high and are latched on the falling edge of
BALE. These signals are generated by the microprocessor or DMA Controller. They also may
be driven by other microprocessors or DMA controllers that reside on the I/O channel.
SBHE# (I/O)
System Bus High Enable (SBHE#) indicates a transfer of data on the upper byte of the data bus,
D[15::8]. 16-bit devices use SBHE# to condition data bus buffers tied to D[15::8].
SMRDC# (O), MRDC# (I/O)
These signals instruct the memory devices to drive data onto the data bus. SMRDC# is active
only when the memory decode is within the low 1MB of memory space. MRDC# is active on all
memory read cycles. MRDC# may be driven by any microprocessor or DMA controller in the
system. SMRDC is derived from MRDC# and the decode of the low 1MB of memory. When a
microprocessor on the I/O channel wishes to drive MRDC#, it must have the address lines valid
on the bus for one system clock period before driving MRDC# active. Both signals are active
low.
SMWTC# (O), MWTC# (I/O)
These signals instruct the memory devices to store the data present on the data bus. SMWTC#
is active only when the memory decode is within the low 1MB of the memory space. MWTC# is
active on all memory write cycles. MWTC# may be driven by any microprocessor or DMA
controller in the system. SMWTC# is derived from MWTC# and the decode of the low 1MB of
memory. When a microprocessor on the I/O channel wishes to drive MWTC#, it must have the
address lines valid on the bus for one system clock period before driving MWTC# active. Both
signals are active low.
Chassis Plans 2-5
ISA/PCI Reference MX8 Technical Reference
T-C (O)
Terminal Count (T-C) provides a pulse when the terminal count for any DMA channel is reached.
Chassis Plans2-6
I/O ADDRESS MAP*
ISA/PCI ReferenceMX8 Technical Reference
Hex Range Device
INTERRUPT
ASSIGNMENTS*
000-01F
020-03F
040-05F
060-06F
070-07F
080-09F
0A0-0BF
0C0-0DF
0F0
0F1
0F8-0FF
1F0-1F8
200-207
278-27F
2F8-2FF
300-31F
360-36F
378-37F
380-38F
3A0-3AF
3B0-3BF
3C0-3CF
3D0-3DF
3F0-3F7
3F8-3FF
Interrupt Description
DMA Controller 1
Interrupt Controller 1, Master
Timer
8042 (Keyboard)
Real-time Clock, NMI (non-maskable interrupt) Mask
DMA Page Register
Interrupt Controller 2
DMA Controller 2
Clear Math Coprocessor Busy
Reset Math Coprocessor
Math Coprocessor
Fixed Disk
Game I/O
Parallel Printer Port 2
Serial Port 2
Prototype Card
Reserved
Parallel Printer Port 1
SDLC, Bisynchronous 2
Bisynchronous 1
Monochrome Display and Printer Adapter
Reserved
Color/Graphics Monitor Adapter
Diskette Controller
Serial Port 1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
Timer Output 0
Keyboard (Output Buffer Full)
Interrupt 8 through 15
Serial Port 2
Serial Port 1
Parallel Port 2
Diskette Controller
Parallel Port 1
Real-time Clock Interrupt
Software Redirected to INT 0AH (IRQ2)
Unassigned
Unassigned
PS/2 Mouse
Coprocessor
Fixed Disk Controller
Unassigned (may be assigned by the system to the
secondary IDE)
* These are typical parameters, which may not reflect your current system.
Chassis Plans 2-7
ISA/PCI Reference MX8 Technical Reference
PCI LOCAL BUS
OVERVIEW
The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or
64-bit bus with multiplexed address and data lines. It is intended for use as an interconnect mechanism between highly integrated peripheral controller components,
peripheral add-in boards and processor/memory systems.
The "local bus" moves peripheral functions with high bandwidth requirements closer to
the system’s processor bus and can produce substantial performance gains with graphical
user interfaces (GUIs) and other high bandwidth functions (i.e., full motion video, SCSI,
LANs, etc.).
The PCI Local Bus accommodates future system requirements and is applicable across
multiple platforms and architectures.
The PCI component and add-in card interface is processor independent, enabling an
efficient transition to future processor generations, by bridges or by direct integration,
and use with multiple processor architectures. Processor independence allows the PCI
Local Bus to be optimized for I/O functions, enables concurrent operation of the local
bus with the processor/memory subsystem, and accommodates multiple high performance peripherals in addition to graphics. Movement to enhanced video and multimedia
displays and other high bandwidth I/O will continue to increase local bus bandwidth
requirements. A transparent 64-bit extension of the 32-bit data and address buses is
defined, doubling the bus bandwidth and offering forward and backward compatibility of
32-bit (132MB/s peak) and 64-bit (264MB/s peak) PCI Local Bus peripherals.
Chassis Plans2-8
ISA/PCI ReferenceMX8 Technical Reference
PCI LOCAL BUS
SIGNAL DEFINITION
The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for
a master to handle data and addressing, interface control, arbitration and system
functions. The diagram below shows the pins in functional groups, with required pins on
the left side and optional pins on the right side.
Required Pins:
Address & Data:
AD[31::00]
C/BE[3::0]#
PAR
Interface Control:
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
Error Reporting:
PERR#
SERR#
Arbitration
(masters only):
REQ#
GNT#
System:
CLK
RST#
PCI
COMPLIANT
DEVICE
Optional Pins:
64-bit Extension
AD[63::32]
C/BE[7::4]#
PAR 64
REQ64#
ACK64#
Interface Control:
LOCK#
INTA#
INTB#
INTC#
INTD#
Cache Support:
SBO#
SDONE
JTAG (IEEE 1149.1):
TDI
TDO
TCK
TMS
TRST#
Chassis Plans 2-9
PCI Pin List
ISA/PCI Reference MX8 Technical Reference
PCI LOCAL BUS
PIN NUMBERING
Component Side
of Board
5-volt/32-bit PCI Connector
Chassis Plans2-10
ISA/PCI ReferenceMX8 Technical Reference
PCI LOCAL BUS
PIN ASSIGNMENTS
The PCI Local Bus pin assignments shown below are for the PCI option slots on the
backplane.
The PCI Local Bus specifies both 5-volt and 3.3-volt signaling environments. The
following bus pin assignments are for the 5-volt connector. The 3.3-volt connector bus
pin assignments are the same with the following exceptions:
* The pins noted as +V (I/O) are +5 volts or +3.3 volts, depending on which
connector is being used.
† Pins B12, B13, A12 and A13 are Gnd (ground) on the 5-volt connector, but
are Connector Keys on the 3.3-volt connector.
†† Pin B49 is Gnd (ground) on the 5-volt connector, but is M66EN on the 3.3-
volt connector.
††† Pins B50, B51, A50 and A51 are Connectors Keys on the 5-volt connector,
but are Gnd (ground) on the 3.3-volt connector.
I/O Pin Signal Name I/O Pin Signal Name
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
-12V
TCK
Gnd
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
Gnd
†
Gnd †
Reserved
Gnd
CLK
Gnd
REQ#
+V (I/O) *
AD31
AD29
Gnd
AD27
AD25
+3.3V
C/BE3#
AD23
Gnd
AD21
AD19
+3.3V
AD17
C/BE2#
Gnd
IRDY#
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved
+V (I/O) *
Reserved
Gnd
†
Gnd †
Reserved
RST#
+V (I/O) *
GNT#
Gnd
Reserved
AD30
+3.3V
AD28
AD26
Gnd
AD24
IDSEL
+3.3V
AD22
AD20
Gnd
AD18
AD16
+3.3V
FRAME#
Gnd
32-bit connector start
Chassis Plans 2-11
ISA/PCI Reference MX8 Technical Reference
PCI LOCAL BUS
PIN ASSIGNMENTS
(CONTINUED)
I/O Pin Signal Name I/O Pin Signal Name
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
+3.3V
DEVSEL#
Gnd
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE1#
AD14
Gnd
AD12
AD10
Gnd
††
Connector Key
Connector Key †††
AD8
AD7
+3.3V
AD5
AD3
Gnd
AD1
+V (I/O) *
ACK64#
+5V
+5V
†††
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
TRDY#
Gnd
STOP#
+3.3V
SDONE
SBO#
Gnd
PAR
AD15
+3.3V
AD13
AD11
Gnd
AD9
Connector Key †††
Connector Key †††
C/BE0#
+3.3V
AD6
AD4
Gnd
AD2
AD0
+V (I/O) *
REQ64#
+5V
+5V 32-bit connector end
5-volt key
5-volt key
Chassis Plans2-12
ISA/PCI ReferenceMX8 Technical Reference
PCI LOCAL BUS
PIN ASSIGNMENTS
(CONTINUED)
The following pin assignments apply only to backplanes with 64-bit PCI option slots.
I/O Pin Signal Name I/O Pin Signal Name
Connector Key
Connector Key
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
Reserved
Gnd
C/BE6#
C/BE4#
Gnd
AD63
AD61
+V (I/O) *
AD59
AD57
Gnd
AD55
AD53
Gnd
AD51
AD49
+V (I/O) *
AD47
AD45
Gnd
AD43
AD41
Gnd
AD39
AD37
+V (I/O) *
AD35
AD33
Gnd
Reserved
Reserved
Gnd
Connector Key
Connector Key
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
Gnd
C/BE7#
C/BE5#
+V (I/O) *
PAR 64
AD62
Gnd
AD60
AD58
Gnd
AD56
AD54
+V (I/O) *
AD52
AD50
Gnd
AD48
AD46
Gnd
AD44
AD42
+V (I/O) *
AD40
AD38
Gnd
AD36
AD34
Gnd
AD32
Reserved
Gnd
Reserved
64-bit spacer
64-bit spacer
64-bit connector start
64-bit connector end
Chassis Plans 2-13
ISA/PCI Reference MX8 Technical Reference
PCI LOCAL BUS
SIGNAL
DESCRIPTIONS
The PCI Local Bus signals are described below and may be categorized into the
following functional groups:
• System Pins
• Address and Data Pins
• Interface Control Pins
• Arbitration Pins (Bus Masters Only)
• Error Reporting Pins
• Interrupt Pins (Optional)
• Cache Support Pins (Optional)
• 64-Bit Bus Extension Pins (Optional)
• JTAG/Boundary Scan Pins (Optional)
A # symbol at the end of a signal name indicates that the active state occurs when the
signal is at a low voltage. When the # symbol is absent, the signal is active at a high
voltage.
The following are descriptions of the PCI Local Bus signals.
ACK64# (optional)
Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded its
address as the target of the current access, indicates the target is willing to transfer data using
64bits. ACK64# has the same timing as DEVSEL#.
AD[31::00]
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases. During the address phase, AD[31::00]
contain a physical address (32 bits). During data phases, AD[07::00] contain the least significant byte (lsb) and AD[31::24] contain the most significant byte (msb).
AD[63::32] (optional)
Address and Data are multiplexed on the same pins and provide 32additional bits. During an
address phase (when using the DAC command and when REQ64# is asserted), the upper
32bits of a 64-bit address are transferred; otherwise, these bits are reserved but are stable and
indeterminate. During a data phase, an additional 32bits of data are transferred when REQ64#
and ACK64# are both asserted.
C/BE[3::0]#
Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address
phase of a transaction, these pins define the bus command; during the data phase they are
used as byte enables. The byte enables are valid for the entire data phase and determine
which byte lanes carry meaningful data. C/BE0# applies to byte0 (lsb) and C/BE3# applies to
byte 3 (msb).
Chassis Plans2-14
ISA/PCI ReferenceMX8 Technical Reference
C/BE[7::4]# (optional)
Bus Command and Byte Enables are multiplexed on the same pins. During an address phase
(when using the DAC command and when REQ64# is asserted), the actual bus command is
transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data
phase, C/BE[7::4]# are byte enables indicating which byte lanes carry meaningful data when
REQ64# and ACK64# are both asserted. C/BE4# applies to byte4 and C/BE7# applies to
byte7.
CLK
Clock provides timing for all transactions on PCI and is an input to every PCI device.
DEVSEL#
Device Select, when actively driven, indicates that the driving device has decoded its address
as the target of the current access. As an input, DEVSEL# indicates whether any device on the
bus has been selected.
FRAME#
Cycle Frame is an interface control pin which is driven by the current master to indicate the
beginning and duration of an access. When FRAME# is asserted, data transfers continue;
when it is deasserted, the transaction is in the final data phase.
GNT#
Grant indicates to the agent that access to the bus has been granted. This is a point to point
signal. Every master has its own GNT#.
IDSEL
Initialization Device Select is used as a chip select during configuration read and write transactions.
INTA#, INTB#, INTC#, INTD# (optional)
Interrupts on PCI are optional and defined as "level sensitive," asserted low (negative true),
using open drain output drivers. PCI defines one interrupt for a single function and up to four
interrupt lines for a multi-function device or connector.
Interrupt A is used to request an interrupt. For a single function device, only INTA# may be
used, while the other three interrupt lines have no meaning.
Interrupt B, Interrupt C and Interrupt D are used to request additional interrupts and only have
meaning on a multi-function device.
IRDY#
Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data
phase of the transaction. IRDY# is used in conjunction with TRDY#. During a write, IRDY#
indicates that valid data is present on AD[31::0]. During a read, it indicates that the master is
prepared to accept data.
LOCK#
Lock indicates an operation that may require multiple transactions to complete. When LOCK#
is asserted, non-exclusive transactions may proceed to an address that is not currently locked.
Chassis Plans 2-15
ISA/PCI Reference MX8 Technical Reference
PAR
Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI
agents. The master drives PAR for address and write data phases; the target drives PAR for
read data phases.
PAR64 (optional)
Parity Upper DWORD is the even parity bit that protects AD[63::32] and C/BE[7::4]#. The
master drives PAR64 for address and write data phases; the target drives PAR64 for read data
phases.
PERR#
Parity Error is for the reporting of data parity errors during all PCI transactions except a Special
Cycle. There are no special conditions when a data parity error may be lost or when reporting
of an error may be delayed.
PRSNT1# and PRSNT2#
PRSNT1# and PRSNT2# are related to the connector only, not to other PCI components. They
are used for two purposes: indicating that a board is physically present in the slot and providing
information about the total power requirements of the board.
REQ#
Request indicates to the arbiter that this agent desires use of the bus. This is a point to point
signal. Every master has its own REQ#.
REQ64# (optional)
Request 64-bit Transfer, when actively driven by the current bus master, indicates it desires to
transfer data using 64 bits. REQ64# has the same timing as FRAME#. REQ64# has meaning
at the end of reset.
RST#
Reset is used to bring PCI-specific registers, sequencers and signals to a consistent state.
SBO# (optional)
Snoop Backoff is an optional cache support pin which indicates a hit to a modified line when
asserted. When SBO# is deasserted and SDONE is asserted, it indicates a "clean" snoop
result.
SDONE (optional)
Snoop Done is an optional cache support pin which indicates the status of the snoop for the
current access. When deasserted, it indicates the result of the snoop is still pending. When
asserted, it indicates the snoop is complete.
SERR#
System Error is for reporting address parity errors, data parity errors on the Special Cycle
command, or any other system error where the result will be catastrophic. If an agent does not
want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is
required.
Chassis Plans2-16
ISA/PCI ReferenceMX8 Technical Reference
STOP#
Stop indicates that the current target is requesting the master to stop the current transaction.
TCK (optional)
Test Clock is used to clock state information and test data into and out of the device during
operation of the TAP (Test Access Port).
TDI (optional)
Test Data Input is used to serially shift test data and test instructions into the device during TAP
(Test Access Port) operation.
TDO (optional)
Test Data Output is used to serially shift test data and test instructions out of the device during
TAP (Test Access Port) operation.
TMS (optional)
Test Mode Select is used to control the state of the TAP (Test Access Port) controller in the
device.
TRDY#
Target Ready indicates the target agent’s (selected device’s) ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. During a read, TRDY#
indicates that valid data is present on AD[31::00]. During a write, it indicates that the target is
prepared to accept data.
TRST# (optional)
Test Reset provides an asynchronous initialization of the TAP controller. This signal is optional
in the IEEE Standard Test Access Port and Boundary Scan Architecture.
Chassis Plans 2-17
ISA/PCI Reference MX8 Technical Reference
PICMG EDGE
CONNECTOR PIN
ASSIGNMENTS
The pin assignments shown below are for the PICMG portion of the edge connector on
the processor board. These pin assignments match those of the PICMG connector of the
processor slot on the backplane.
I/O Pin Signal Name I/O Pin Signal Name
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V
NC
Gnd
NC
+5V
+5V
INTB#
INTD#
REQ3#
REQ1#
GNT3#
Gnd
Gnd
CLKS0
Gnd
CLKS1
Gnd
REQ0#
+5V
AD31
AD29
Gnd
AD27
AD25
BKPL3.3V
C/BE3#
AD23
Gnd
AD21
AD19
NC
AD17
C/BE2#
Gnd
IRDY#
NC
DEVSEL#
Gnd
LOCK#
PERR#
NC
SERR#
NC
C/BE1#
AD14
Gnd
AD12
AD10
M66EN
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
NC
+12V
NC
NC
+5V
INTA#
INTC#
+5V
CLKS2
+5V
CLKS3
Gnd
Gnd
GNT1#
RST#
+5V
GNT0#
Gnd
REQ2#
AD30
NC
AD28
AD26
Gnd
AD24
GNT2#
NC
AD22
AD20
Gnd
AD18
AD16
NC
FRAME#
Gnd
TRDY#
Gnd
STOP#
NC
SDONE
SBO#
Gnd
PAR
AD15
NC
AD13
AD11
Gnd
AD9
32-bit connector start
Chassis Plans2-18
PICMG EDGE
CONNECTOR PIN
ASSIGNMENTS
(CONTINUED)
ISA/PCI ReferenceMX8 Technical Reference
I/O Pin Signal Name I/O Pin Signal Name
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
Connector Key
Connector Key
AD8
AD7
NC
AD5
AD3
Gnd
AD1
+5V
ACK64#
+5V
+5V
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
Connector Key
Connector Key
C/BE0#
NC
AD6
AD4
Gnd
AD2
AD0
+5V
REQ64#
+5V
+5V 32-bit connector end
Chassis Plans 2-19
ISA/PCI Reference MX8 Technical Reference
PICMG EDGE
CONNECTOR PIN
ASSIGNMENTS
(CONTINUED)
The following pin assignments apply only to SBCs with 64-bit PICMG connectors.
I/O Pin Signal Name I/O Pin Signal Name
Connector Key
Connector Key
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
NC
Gnd
C/BE6#
C/BE4#
Gnd
AD63
AD61
+5V
AD59
AD57
Gnd
AD55
AD53
Gnd
AD51
AD49
+5V
AD47
AD45
Gnd
AD43
AD41
Gnd
AD39
AD37
+5V
AD35
AD33
Gnd
NC
NC
Gnd
Connector Key
Connector Key
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
Gnd
C/BE7#
C/BE5#
+5V
PAR 64
AD62
Gnd
AD60
AD58
Gnd
AD56
AD54
+5V
AD52
AD50
Gnd
AD48
AD46
Gnd
AD44
AD42
+5V
AD40
AD38
Gnd
AD36
AD34
Gnd
AD32
NC
Gnd
NC
64-bit spacer
64-bit spacer
64-bit connector start
64-bit connector end
Copyright 2004 by Trenton Technology Inc. All rights reserved.
Chassis Plans2-20
System BIOSMX8 Technical Reference
Chapter 3 System BIOS
BIOS OPERATION Sections 3 through 7 of this manual describe the operation of the American Megatrends
AMIBIOS and the BIOS Setup Utility. Refer to Running AMIBIOS Setup later in this
chapter for standard Setup screens, options and defaults. The available Setup screens,
options and defaults may vary if you have a custom BIOS.
When the system is powered on, AMIBIOS performs the Power-On Self Test (POST)
routines. These routines are divided into two phases:
1) System Test and Initialization. Test and initialize system boards for
normal operations.
2) System Configuration Verification. Compare defined configuration with
hardware actually installed.
If an error is encountered during the diagnostic tests, the error is reported in one of two
different ways. If the error occurs before the display device is initialized, a series of
beeps is transmitted. If the error occurs after the display device is initialized, the error
message is displayed on the screen. See BIOS Errors later in this section for more information on error handling.
The following are some of the Power-On Self Tests (POSTs) which are performed when
the system is powered on:
• CMOS Checksum Calculation
• Keyboard Controller Test
• CMOS Shutdown Register Test
• 8254 Timer Test
• Memory Refresh Test
• Display Memory Read/Write Test
• Display Type Verification
• Entering Protected Mode
• Memory Size Calculation
• Conventional and Extended Memory Test
• DMA Controller Tests
• Keyboard Test
• System Configuration Verification and Setup
AMIBIOS checks system memory and reports it on both the initial AMIBIOS screen and
the AMIBIOS System Configuration screen which appears after POST is completed.
AMIBIOS attempts to initialize the peripheral devices and if it detects a fault, the screen
displays the error condition(s) which has/have been detected. If no errors are detected,
AMIBIOS attempts to load the system from a bootable device, such as a floppy disk or
hard disk. Boot order may be specified by the Boot Device Priority option on the Boot
Setup Menu as described in the Boot Setup chapter later in this manual.
Chassis Plans 3-1
System BIOS MX8 Technical Reference
Normally, the only POST routine visible on the screen is the memory test. The following
screen displays when the system is powered on:
AMIBIOS (C)2002 American Megatrends, Inc.
TRENTON Technology Inc.
Press DEL to run Setup
Initial Power-On Screen
You have two options:
• Press <Del> to access the BIOS Setup Utility.
This option allows you to change various system parameters such as date
and time, disk drives, etc. The Running AMIBIOS Setup section of this
manual describes the options available.
You may be requested to enter a password before gaining access to the BIOS
Setup Utility. (See Password Entry later in this section.)
If you enter the correct password or no password is required, the BIOS
Setup Utility Main Menu displays. (See Running AMIBIOS Setup later in
this section.)
• Allow the bootup process to continue without invoking the BIOS Setup
Utility.
In this case, after AMIBIOS loads the system, you may be requested to enter
a password. (See Password Entry later in this section.)
Once the POST routines complete successfully, a screen displays showing the current
configuration of your system, including processor type, base and extended memory
amounts, floppy and hard drive types, display type and peripheral ports.
Password Entry
The system may be configured so that the user is required to enter a password each time
the system boots or whenever an attempt is made to enter the BIOS Setup Utility. The
password function may also be disabled so that the password prompt does not appear
under any circumstances.
The Password Check option in the Security Menu allows you to specify when the
password prompt displays: Always or only when Setup is attempted. This option is
available only if the supervisor and/or user password(s) have been established. The
supervisor and user passwords may be changed using the Change Supervisor Password
and Change User Password options on the Security Menu. If the passwords are null,
the password prompt does not display at any time. See the Security Setup section of this
chapter for details on setting up passwords.
When password checking is enabled, the following password prompt displays:
Chassis Plans3-2
System BIOSMX8 Technical Reference
Enter CURRENT Password:
Type the password and press <Enter>.
_______________________________________________________________________
NOTE: The null password is the system default and is in effect if a password has not
been assigned or if the CMOS has been corrupted. In this case, the password prompt
does not display. To set up passwords, you may use the Change Supervisor Password
and Change User Password options on the Security Menu of the BIOS Setup Utility.
(See the Security Setup section later in this chapter.)
_______________________________________________________________________
If an incorrect password is entered, the following screen displays:
Enter CURRENT Password: X
Enter CURRENT Password:
You may try again to enter the correct password. If you enter the password incorrectly
three times, the system responds in one of two different ways, depending on the value
specified in the Password Check option on the Security Menu:
1) If the Password Check option is set to Setup, the system does not let you
enter Setup, but does continue the booting process. You must reboot the
system manually to retry entering the password.
2) If the Password Check option is set to Always, the system locks and you
must reboot. After rebooting, you will be requested to enter the password.
Once the password has been entered correctly, you are allowed to continue.
Chassis Plans 3-3
System BIOS MX8 Technical Reference
BIOS Errors
If an error is encountered during the diagnostic checks performed when the system is
powered on, the error is reported in one of two different ways:
1) If the error occurs before the display device is initialized, a series of beeps is
transmitted.
2) If the error occurs after the display device is initialized, the screen displays
the error message. In the case of a non-fatal error, a prompt to press the
<F1> key may also appear on the screen.
Explanations of the beep codes and BIOS error messages may be found in Appendix A -
BIOS Messages.
As the POST routines are performed, test codes are presented on Port 80H. These codes
may be helpful as a diagnostic tool and are listed in Appendix A - BIOS Messages.
If certain non-fatal error conditions occur, you are requested to run the BIOS Setup
Utility. The error messages are followed by this screen:
AMIBIOS (C)2002 American Megatrends, Inc.
TRENTON Technology Inc.
Press F1 to Run SETUP
Press F2 to load default values and continue
Press <F1>. You may be requested to enter a password before gaining access to the
BIOS Setup Utility. (See Password Entry earlier in this section.)
If you enter the correct password or no password is required, the BIOS Setup Utility
Main Menu displays.
Chassis Plans3-4
System BIOSMX8 Technical Reference
RUNNING
AMIBIOS SETUP
AMIBIOS Setup keeps a record of system parameters, such as date and time, disk drives
and other user-defined parameters. The Setup parameters reside in the Read Only
Memory Basic Input/Output System (ROM BIOS) so that they are available each time
the system is turned on. The BIOS Setup Utility stores the information in the complementary metal oxide semiconductor (CMOS) memory. When the system is turned off, a
backup battery retains system parameters in the CMOS memory.
Each time the system is powered on, it is configured with these values, unless the CMOS
has been corrupted or is faulty. The BIOS Setup Utility is resident in the ROM BIOS so
that it is available each time the computer is turned on. If, for some reason, the CMOS
becomes corrupted, the system is configured with the default values stored in this ROM
file.
As soon as the system is turned on, the power-on diagnostic routines check memory,
attempt to prepare peripheral devices for action, and offer you the option of pressing
<Del> to run the BIOS Setup Utility.
If certain non-fatal errors occur during the Power-On Self Test (POST) routines which
are run when the system is turned on, you may be prompted to run the BIOS Setup
Utility by pressing <F1>.
Chassis Plans 3-5
System BIOS MX8 Technical Reference
BIOS SETUP
UTILITY MAIN
MENU
When you press <F1> in response to an error message received during the POST
routines or when you press the <Del> key to enter the BIOS Setup Utility, the following
screen displays:
BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset Exit
System Overview
_________________________________________________
AMIBIOS Version: 08.00.xx
BIOS Build Date: 12/05/03
BIOS ID : 0ABEG005
Processor
Type : Intel(R) Pentium(R) 4 CPU 3.20GHz
Speed : 3200MHz
Count : 1
System Memory
Size : 1024MB
System Time [00:00:00]
System Date [Mon 01/01/2001]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Use [ENTER], {TAB]
or [SHIFT-TAB] to
select a field.
Use [+] or [-] to
configure System
Time.
←→ Select Screen
↑↓ Select Item
+- Change Field
Tab Select Field
F1 General Help
F10 Save and Exit
ESC Exit
BIOS SETUP
UTILITY MAIN
MENU OPTIONS
BIOS Setup Utility Main Menu
When you display the BIOS Setup Utility Main Menu, the format is similar to the sample
shown above. The data displayed on the top portion of the screen details parameters
detected by AMIBIOS for your processor board and may not be modified. The system
time and date displayed on the bottom portion of the screen may be modified.
The descriptions for the system options listed below show the values as they appear if
you have not changed them yet. Once values have been defined, they display each time
the BIOS Setup Utility is run.
System Time/System Date
These options allow you to set the correct system time and date. If you do not set these
parameters the first time you enter the BIOS Setup Utility, you will receive a "Run
SETUP" error message when you boot the system until you set the correct parameters.
The Setup screen displays the system options:
System Time [00:00:00]
System Date [Mon 01/01/2001]
There are three fields for entering the time or date. Use the <Tab> key or the <Enter>
key to move from one field to another and type in the correct value for the field.
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System BIOSMX8 Technical Reference
If you enter an invalid value in any field, the screen will revert to the previous value
when you move to the next field. When you change the value for the month, day or year
field, the day of the week changes automatically when you move to the next field.
BIOS SETUP
UTILITY OPTIONS
The BIOS Setup Utility allows you to change system parameters to tailor your system to
your requirements. Various options which may be changed are listed below. Further
explanations of these options and available values may be found in later chapters of this
manual, as noted below.
_______________________________________________________________________
NOTE: Do not change the values for any option unless you understand the impact on
system operation. Depending on your system configuration, selection of other values
may cause unreliable system operation.
_______________________________________________________________________
Use the Right Arrow key to display the desired menu. The following menus are
available:
• Select Advanced to make changes to Advanced Setup parameters as
described in the Advanced Setup chapter of this manual. The following
options may be modified:
• CPU Configuration
• Max CPUID Value Limit
• Hyper Threading Technology
• IDE Configuration
• IDE Configuration
• S-ATA Running Enhanced Mode
• P-ATA Channel Selection
• Combined Mode Option
• S-ATA Ports Definition
• Configure S-ATA as RAID
• Primary IDE Master/Primary IDE Slave
Secondary IDE Master/Secondary IDE Slave
• Type
• LBA/Large Mode
• Block (Multi-Sector Transfer)
• PIO Mode
• DMA Mode
• S.M.A.R.T.
• 32Bit Data Transfer
• Third IDE Master/Fourth IDE Master
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• Hard Disk Write Protect
• IDE Detect Time Out (Sec)
• ATA(PI) 80Pin Cable Detection
• Floppy Configuration
• Floppy A/Floppy B
• SuperIO Configuration
• OnBoard Floppy Controller
• Serial Port1 Address/Serial Port2 Address
• Parallel Port Address
• Parallel Port Mode
• Parallel Port IRQ
• Remote Access Configuration
• Remote Access
• Serial Port Number
• Serial Port Mode
• Post-Boot Support
• USB Configuration
• USB Function
• Legacy USB Support
• USB 2.0 Controller
• USB 2.0 Controller Mode
• Select PCIPnP to make changes to PCI Plug and Play Setup parameters as
described in the PCI Plug and Play Setup chapter of this manual. The
following options may be modified:
• Plug & Play O/S
• PCI Latency Timer
• Allocate IRQ to PCI VGA
• Palette Snooping
• PCI IDE BusMaster
• OffBoard PCI/ISA IDE Card
• OffBoard PCI IDE Primary IRQ
• OffBoard PCI IDE Secondary
• Onboard 82547GI Gbe LAN
• Onboard 82540 LAN
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• Onboard Adaptec SCSI
• Onboard ATI Radeon Video
• IRQs 3, 4, 5, 7, 9, 10, 11, 14 and 15
• DMA Channels 0, 1, 3 5, 6 and 7
• Reserved Memory Size
• Reserved Memory Address
• Select Boot to make changes to Boot Setup parameters as described in the
Boot Setup chapter of this manual. The following options may be modified:
• Boot Settings Configuration
• Quick Boot
• Quiet Boot
• AddOn ROM Display Mode
• Bootup Num-Lock
• PS/2 Mouse Support
• Wait For ‘F1’ If Error
• Hit ‘DEL’ Message Display
• Interrupt 19 Capture
• Boot Device Priority
• Hard Disk Drives
• Removable Drives
• CD/DVD Drives
• Select Security to establish or change the supervisor or user password or to
enable boot sector virus protection. These functions are described later in
this chapter. The following options may be modified:
• Change Supervisor Password
• User Access Level
• Password Check
• Change User Password
• Unattended Start
• Password Check
• Clear User Password
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• Boot Sector Virus Protection
System BIOS MX8 Technical Reference
• Select Chipset to make changes to Chipset Setup parameters as described in
the Chipset Setup chapter of this manual. The following options may be
modified:
• NorthBridge Configuration
• DRAM Frequency
• Configure DRAM Timing by SPD
• DRAM CAS# Latency
• DRAM RAS# Precharge
• DRAM RAS# to CAS# Delay
• DRAM Precharge Delay
• DRAM Burst Length
• DRAM Integrity Mode
• Memory Hole
• Primary Graphics Adapter
• Graphics Aperture Size
• C.S.A. Gigabit Ethernet
• SouthBridge Configuration
• CPU BIST Enable
• MPS Revision
• Select Exit to save or discard changes you have made to AMIBIOS param-
eters or to load the Optimal or Failsafe default settings. These functions are
described later in this chapter. The following options are available:
• Save Changes and Exit
• Discard Changes and Exit
• Discard Changes
• Load Optimal Defaults
• Load Failsafe Defaults
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SECURITY SETUP When you select Security from the BIOS Setup Utility Main Menu, the following Setup
screen displays:
BIOS SETUP UTILITY
Main Advanced PCIPnP Boot |Security| Chipset Exit
Security Settings
_____________________________________________
Supervisor Password :Not Installed
User Password :Not Installed
Change Supervisor Password
Change User Password
Clear User Password
Boot Sector Virus Protection [Disabled]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Install or Change the
password.
←→ Select Screen
↑↓ Select Item
Enter Change
F1 General Help
F10 Save and Exit
ESC Exit
Security Setup Screen
When you display the Security Setup screen, the format is similar to the sample shown
above. Highlight the option you wish to change and press <Enter>.
_______________________________________________________________________
NOTE: The values on this screen do not necessarily reflect the values appropriate for
your SBC. Refer to the explanations below for specific instructions about entering
correct information.
_______________________________________________________________________
SECURITY SETUP
OPTIONS
The Security Setup options allow you to establish, change or clear the supervisor or user
password and to enable boot sector virus protection.
The descriptions for the system options listed below show the values as they appear if
you have not changed them yet. Once values have been defined, they display each time
the BIOS Setup Utility is run.
C
HANGE
S
UPERVISOR
PASSWORD
This option allows you to establish a supervisor password, change the current password
or disable the password prompt by entering a null password. The password is stored in
CMOS RAM.
If you have signed on under the user password, this option is not available.
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The Change Supervisor Password feature can be configured so that a password must be
entered each time the system boots or just when a user attempts to enter the BIOS Setup
Utility.
_______________________________________________________________________
NOTE: The null password is the system default and is in effect if a password has not
been assigned or if the CMOS has been corrupted. In this case, the "Enter CURRENT
Password" prompt is bypassed when you boot the system, and you must establish a new
password.
_______________________________________________________________________
If you select the Change Supervisor Password option, the following window displays:
Enter New Password
This is the message which displays before you have established a password, or if the last
password entered was the null password. If a password has already been established, you
are asked to enter the current password before being prompted to enter the new
password.
Type the new password and press <Enter>. The password cannot exceed six (6)
characters in length. The screen displays an asterisk (*) for each character you type.
After you have entered the new password, the following window displays:
Confirm New Password
Re-key the new password as described above.
If the password confirmation is miskeyed, AMIBIOS Setup displays the following
message:
Passwords do not match!
[Ok]
No retries are permitted; you must restart the procedure.
If the password confirmation is entered correctly, the following message displays:
Password installed.
[Ok]
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System BIOSMX8 Technical Reference
Press the <Enter> key to return to the Security screen. Installed displays on the screen
next to the Supervisor Password option, indicating the password has been accepted.
This setting will remain in effect until the supervisor password is either disabled or
discarded upon exiting the BIOS Setup Utility.
If you have created a new password, be sure to select Exit, then Save Changes and Exit
to save the password. The password is then stored in CMOS RAM. The next time the
system boots, you are prompted for the password.
_______________________________________________________________________
NOTE: Be sure to keep a record of the new password each time it is changed. If you
forget it, use the Password Clear jumper to reset it to the default (null password). See the
Specifications chapter of this manual for details.
_______________________________________________________________________
If a password has been established, the following options and their default values are
added to the screen:
User Access Level [Full Access]
Password Check [Setup]
User Access Level
This option allows you to define the level of access the user will have to the system.
The Setup screen displays the system option:
User Access Level [Full Access]
Four options are available:
• Select No Access to prevent user access to the BIOS Setup Utility.
• Select View Only to allow access to the BIOS Setup Utility for viewing, but
to prevent the user from changing any of the fields.
• Select Limited to allow the user to change only a limited number of options,
such as Date and Time.
• Select Full Access to allow the user full access to change any option in the
BIOS Setup Utility.
Password Check
This option determines when a password is required for access to the system.
The Setup screen displays the system option:
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Password Check [Setup]
System BIOS MX8 Technical Reference
Two options are available:
• Select Setup to have the password prompt appear only when an attempt is
made to enter the BIOS Setup Utility program.
• Select Always to have the password prompt appear each time the system is
powered on.
D
ISABLING THE
SUPERVISOR
PASSWORD
C
HANGE USER
PASSWORD
To disable password checking so that the password prompt does not appear, you may
create a null password by selecting the Change Supervisor Password function and
pressing <Enter> without typing in a new password. You will be asked to enter the
current password before being allowed to enter the null password. After you press
<Enter> at the Enter New Password prompt, the following message displays:
Password uninstalled.
[Ok]
The Change User Password option is similar in functionality to the Change Supervisor
Password and displays the same messages. If you have signed on under the user
password, the Change Supervisor Password function is not available for modification.
CLEAR USER
PASSWORD
BOOT SECTOR
VIRUS PROTECTION
If a user password has been established, the Password Check option and its default
value is added to the screen. This option determines when a user password is required
for access to the system. For details, refer to the description for Password Check under
the Change Supervisor Password heading earlier in this section.
This option allows you to clear the user password. It disables the user password by
entering a null password.
If you select the Clear User Password option, the following window displays:
Clear User Password?
[Ok] [Cancel]
You have two options:
• Select Ok to clear the user password.
• Select Cancel to leave the current user password in effect.
This option allows you to request AMIBIOS to issue a warning when any program or
virus issues a Disk Format command or attempts to write to the boot sector of the hard
disk drive.
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System BIOSMX8 Technical Reference
The Setup screen displays the system option:
Boot Sector Virus Protection [Disabled]
Available options are:
Disabled
Enabled
_______________________________________________________________________
NOTE: You should not enable boot sector virus protection when formatting a hard
drive.
_______________________________________________________________________
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EXIT MENU When you select Exit from the BIOS Setup Utility Main Menu, the following screen
displays:
BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset |Exit|
Exit Options
_____________________________________________
Save Changes and Exit
Discard Changes and Exit
Discard Changes
Load Optimal Defaults
Load Failsafe Defaults
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Exit system setup
after saving the
changes.
F10 key can be used
for this operation.
←→ Select Screen
↑↓ Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Exit Menu Screen
When you display the Exit Menu screen, the format is similar to the sample shown
above. Highlight the option you wish to select and press <Enter>.
EXIT MENU
OPTIONS
When you are running the BIOS Setup Utility program, you may either save or discard
changes you have made to AMIBIOS parameters, or you may load the Optimal or
Failsafe default settings.
Save Changes and Exit
The features selected and configured in the Setup screens are stored in the CMOS when
this option is selected. The CMOS checksum is calculated and written to the CMOS.
Control is then passed back to the AMIBIOS and the booting process continues, using
the new CMOS values.
If you select the Save Changes and Exit option, the following window displays:
Save configuration changes and exit setup?
[Ok] [Cancel]
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System BIOS MX8 Technical Reference
You have two options:
• Select Ok to save the system parameters and continue with the booting
process.
• Select Cancel to return to the BIOS Setup Utility screen.
Discard Changes and Exit
When the Discard Changes and Exit option is selected, the BIOS Setup Utility exits
without saving the changes in the CMOS. Control is then passed back to AMIBIOS and
the booting process continues, using the previous CMOS values.
If you select the Discard Changes and Exit option, the following window displays:
Discard changes and exit setup?
[Ok] [Cancel]
You have two options:
• Select Ok to continue the booting process without writing any changes to
the CMOS.
• Select Cancel to return to the BIOS Setup Utility screen.
Discard Changes
When the Discard Changes option is selected, the BIOS Setup Utility resets any parameters you have changed back to the values at which they were set when you entered the
Setup Utility. Control is then passed back to the BIOS Setup Utility screen.
If you select the Discard Changes option, the following window displays:
Discard changes?
[Ok] [Cancel]
You have two options:
• Select Ok to reset any parameters you have changed back to the values at
which they were set when you entered the BIOS Setup Utility. This option
then returns you to the BIOS Setup Utility screen.
• Select Cancel to return to the BIOS Setup Utility screen without discarding
any changes you have made.
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System BIOSMX8 Technical Reference
Load Optimal or Failsafe Defaults
Each AMIBIOS Setup option has two default settings (Optimal and Failsafe). These
settings can be applied to all AMIBIOS Setup options when you select the appropriate
configuration option from the BIOS Setup Utility Main Menu.
You can use these configuration options to quickly set the system configuration parameters which should provide the best performance characteristics, or you can select a
group of settings which have a better chance of working when the system is having
configuration-related problems.
Load Optimal Defaults
This option allows you to load the Optimal default settings. These settings are best-case
values which should provide the best performance characteristics. If CMOS RAM is
corrupted, the Optimal settings are loaded automatically.
If you select the Load Optimal Defaults option, the following window displays:
Load Optimal Defaults?
[Ok] [Cancel]
You have two options:
• Select Ok to load the Optimal default settings.
• Select Cancel to leave the current values in effect.
Load Failsafe Defaults
This option allows you to load the Failsafe default settings when you cannot boot your
computer successfully. These settings are more likely to configure a workable computer.
They may not provide optimal performance, but are the most stable settings. You may
use this option as a diagnostic aid if your system is behaving erratically. Select the
Failsafe settings and then try to diagnose the problem after the computer boots.
If you select the Load Failsafe Defaults option, the following window displays:
Load Failsafe Defaults?
[Ok] [Cancel]
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System BIOS MX8 Technical Reference
You have two options:
• Select Ok to load the Failsafe default settings.
• Select Cancel to leave the current values in effect.
Copyright 2004 by Trenton Technology Inc. All rights reserved.
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Advanced SetupMX8 Technical Reference
Chapter 4 Advanced Setup
ADVANCED SETUP When you select Advanced from the BIOS Setup Utility Main Menu, the following
Setup screen displays:
BIOS SETUP UTILITY
Main |Advanced| PCIPnP Boot Security Chipset Exit
Advanced Settings
______________________________________________
WARNING: Setting wrong values in below sections
may cause system to malfunction.
> CPU Configuration
> IDE Configuration
> Floppy Configuration
> SuperIO Configuration
> Remote Access Configuration
> USB Configuration
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Configure CPU.
←→ Select Screen
↑↓ Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Advanced Setup Screen
When you display the Advanced Setup screen, the format is similar to the sample shown
above, allowing you to continue to subscreens designed to change parameters for each of
the Advanced Setup options. Highlight the option you wish to change and press
<Enter> to proceed to the appropriate subscreen.
_______________________________________________________________________
NOTE: The values on the Advanced Setup subscreens do not necessarily reflect the
values appropriate for your SBC. Refer to the explanations following each screen for
specific instructions about entering correct information.
_______________________________________________________________________
A
DVANCED SETUP
OPTIONS
_______________________________________________________________________
NOTE:Do not change the values for any Advanced Setup option unless you understand
the impact on system operation. Depending on your system configuration, selection of
other values may cause unreliable system operation.
_______________________________________________________________________
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Advanced Setup MX8 Technical Reference
CPU Configuration
The CPU Configuration subscreen provides you with information about the processor
in your system. The following option is displayed:
• Max CPUID Value Limit
• Hyper Threading Technology
IDE Configuration
The options on the IDE Configuration subscreens allow you to set up or modify parameters for your IDE controller and hard disk drive(s). The following options may be
modified:
• IDE Configuration
• S-ATA Running Enhanced Mode
• P-ATA Channel Selection
• Combined Mode Option
• S-ATA Ports Definition
• Configure S-ATA as RAID
• Primary IDE Master/Primary IDE Slave
• Type
• LBA/Large Mode
• Block (Multi-Sector Transfer)
• PIO Mode
• DMA Mode
• S.M.A.R.T.
• 32Bit Data Transfer
• Secondary IDE Master/Secondary IDE Slave
• (see options above)
• Third IDE Master/Fourth IDE Master
• Hard Disk Write Protect
• IDE Detect Time Out (Sec)
• ATA(PI) 80Pin Cable Detection
Floppy Configuration
The options on the Floppy Configuration subscreen allow you to set up or modify
parameters for your floppy disk drive(s). The following options may be modified:
• Floppy A/Floppy B
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Advanced SetupMX8 Technical Reference
SuperIO Configuration
The options on the SuperIO Configuration subscreen allow you to set up or modify
parameters for your on-board peripherals. The following options may be modified:
• OnBoard Floppy Controller
• Serial Port1 Address/Serial Port2 Address
• Parallel Port Address
• Parallel Port Mode
• Parallel Port IRQ
Remote Access Configuration
The options on the Remote Access Configuration subscreen allow you to set up or
modify parameters for configuring remote access type and parameters. The following
options may be modified:
• Remote Access
• Serial Port Number
• Serial Port Mode
• Post-Boot Support
USB Configuration
The options on the USB Configuration subscreen allow you to set up or modify parameters for your on-board peripherals. The following options may be modified:
• USB Configuration
• USB Function
• Legacy USB Support
• USB 2.0 Controller
• USB 2.0 Controller Mode
Saving and Exiting
When you have made all desired changes to Advanced Setup, you may make changes to
other Setup options by using the right and left arrow keys to access other menus. When
you have made all of your changes, you may save them by selecting the Exit menu, or
you may press <Esc> at any time to exit the BIOS Setup Utility without saving the
changes.
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CPU
CONFIGURATION
SETUP
When you select CPU Configuration from the Advanced Setup Screen, the following
Setup screen displays:
BIOS SETUP UTILITY
|Advanced|
Configure advanced CPU settings
Manufacturer: Intel
Brand String: Intel(R) Pentium(R) 4 CPU 3.20GHz
Frequency : 3.20GHz
FSB Speed : 800MHz
Cache L1 : 8 KB
Cache L2 : 512 KB
Ratio Status : Locked
Ratio Actual Value: 20
Ratio CMOS Setting: [ 16]
VID CMOS Setting : [ 62]
Max CPUID Value Limit: [Enabled]
Hyper Threading Technology [Disabled]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
This should be enabled
in order to boot legacy
OSes that cannot
support CPUs with
extended CPUID
functions.
←→ Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
CPU
CONFIGURATION
SETUP OPTIONS
CPU Configuration Screen
When you display the CPU Configuration screen, the format is similar to the sample
shown above. Highlight the option you wish to change and press <Enter> to display the
available settings. Select the appropriate setting and press <Enter> again to accept the
highlighted value.
The description for the system options listed below show the values as they appear if you
have not yet run Advanced Setup. Once you change the settings, the new settings
display each time Advanced Setup is run.
Max CPUID Value Limit
The Setup screen displays the system option:
Max CPUID Value Limit [Enabled]
Available options are:
Disabled
Enabled
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Hyper Threading
Hyper-Threading is a feature which can be used to maximize the processor’s efficiency
and execution speed by using the single processor as two logical processors. The two
logical processors have separate architectural and local APIC states, but unlike separate
physical processors, these logical processors share common execution resources.
Hyper-Threading improves overall performance in many systems designed for multiprocessing, high-demand multi-tasking and multi-threaded applications. If you are using
a system which can take advantage of Hyper-Threading technology, you may change the
setting of the Hyper Threading option to Enabled.
®
Intel
recommends enabling Hyper-Threading on systems that use Microsoft®
Windows® XP® or Linux® 2.4.x operating systems.
The factory setting of the Hyper Threading option in the system BIOS is Disabled. For
systems which use applications and operating systems which cannot take advantage of
Hyper-Threading technology, the Hyper Threading option should remain Disabled.
Intel recommends disabling Hyper-Threading when using the following operating
systems: Microsoft Windows 98
IBM® OS/2® and any version of Linux before revision 2.4.x. These operating systems
are not optimized for Hyper-Threading technology and some applications may actually
experience some performance degradation.
®
, Windows NT®, Windows 2000®, Windows ME®,
The Setup screen displays the system option:
Hyper Threading [Disabled]
Available options are:
Disabled
Enabled
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IDE
CONFIGURATION
When you select IDE Configuration from the Advanced Setup Menu, a Setup screen
similar to the following displays:
BIOS SETUP UTILITY
|Advanced|
IDE Configuration
________________________________________________
IDE Configuration [P-ATA Only]
S-ATA Running Enhanced Mode [Yes]
P-ATA Channel Selection [Both]
S-ATA Ports Definition [P0-3rd/P1-4th]
Configure S-ATA as RAID [No]
> Primary IDE Master : [Hard Disk]
> Primary IDE Slave : [Hard Disk]
> Secondary IDE Master: [ATAPI CDROM]
> Secondary IDE Slave : [Not Detected]
> Third IDE Master : [Not Detected]
> Fourth IDE Master : [Not Detected]
Hard Disk Write Protect [Disabled]
IDE Detect Time Out (Sec) [35]
ATA(PI) 80Pin Cable Detection [Host & Device]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
←→ Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
IDE
CONFIGURATION
OPTIONS
IDE Configuration Screen
When you display the IDE Configuration screen, the format is similar to the sample
shown above. Highlight the option you wish to change and press <Enter> to display the
available settings. Select the appropriate setting and press <Enter> again to accept the
highlighted value.
Some of the options on this screen allow you to continue to subscreens designed to
change parameters for that particular option. Highlight the option you wish to change
and press <Enter> to proceed to the appropriate subscreen.
The descriptions for the system options listed below show the values as they appear if
you have not run the BIOS Setup Utility program yet. Once values have been defined,
they display each time the BIOS Setup Utility is run.
IDE Configuration
This option specifies which IDE ports are available for use. The line items which display
below the IDE Configuration option vary depending on the setting of this option.
The Setup screen displays the system option:
IDE Configuration [P-ATA Only]
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Four options are available:
• Select Disabled to disable all IDE ports.
• Select P-ATA Only to allow up to six devices, four parallel and two serial.
The number of devices available depends on the setting of the S-ATA
Running Enhanced Mode option described below.
• Select S-ATA Only if only serial ATA devices are to be used. Two serial
devices will be available.
• Select P- ATA & S-ATA if parallel and serial ATA devices are to be used.
Four devices will be available, two parallel and two serial.
S-ATA Running Enhanced Mode
This option allows you to enable up to six devices, four parallel and two serial. It is
available only when the IDE Configuration option described above is set to P-ATA
Only.
The Setup screen displays the system option:
S-ATA Running Enhanced Mode [Yes]
Two options are available:
• Select Ye s to enable six devices (four parallel devices, two serial devices).
• Select No to enable only four devices (parallel devices only, no serial
devices).
If this option is set to No, only the P-ATA Channel Selection option is available.
P-ATA Channel Selection
This option allows you to specify which parallel devices will be available when the IDE
Configuration option is set to P-ATA Only. A total of four parallel devices will
available as described below.
The Setup screen displays the system option:
P-ATA Channel Selection [Both]
Three options are available:
• Select Primary to enable the primary parallel IDE channel (P11) for use.
This enables only two parallel devices, primary master and primary slave.
• Select Secondary to enable the secondary parallel IDE channel (P11A) for
use. This enables only two parallel devices, secondary master and
secondary slave.
• Select Both to enable both the primary and secondary parallel IDE channels
for use. Four parallel devices are available as primary master/slave (P11)
and secondary master/slave (P11A).
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Advanced SetupMX8 Technical Reference
Combined Mode Option
This option allows you to specify the configuration of the parallel and serial devices
when the IDE Configuration option is set to P - ATA & S - ATA . A total of two parallel
and two serial ATA devices will be available as described below.
The Setup screen displays the system option:
Combined Mode Option [P-ATA 1st Channel]
Two options are available:
• Select P-ATA 1st Channel to enable the primary parallel IDE channel for
use. The two devices on the primary IDE channel (P11) are then defined as
primary master/slave, serial ATA devices (P27 and P28) are secondary
master/slave, and the secondary IDE channel (P11A) is disabled.
• Select S-ATA 1st Channel to enable the secondary parallel IDE channel for
use. The serial ATA devices (P27 and P28) are then defined as primary
master/slave, the devices on the secondary IDE channel (P11A) are
secondary master/slave, and the primary IDE channel (P11) is disabled.
S-ATA Ports Definition
This option specifies the definitions of the two serial ATA ports (P27 and P28).
If the S-ATA Running Enhanced Mode option is set to No, this option is not available.
The Setup screen displays the system option:
S-ATA Ports Definition [P0-3rd/P1-4th]
Three sets of options are available:
• If the IDE Configuration is set to P-ATA Only, the serial ATA ports are
defined as 3rd master and 4th master, but the order of these definitions may
change as follows:
P0-3rd/P1-4th (P27 = 3rd master/P28 = 4th master)
P0-4th/P1-3rd (P27 = 4th master/P28 = 3rd master)
• If the IDE Configuration is set to S-ATA Only, the serial ATA ports
become 1st master and 2nd master, since they are the only ports available,
but the order of these definitions may change as follows:
P0-1st/P1-2nd (P27 = 1st master/P28 = 2nd master)
P0-2nd/P1-1st (P27 = 2nd master/P28 = 1st master)
• If the IDE Configuration is set to P- ATA & S - ATA , the serial ATA ports
are defined as master and slave. They will be defined as either primary or
secondary master and slave, depending on the setting of the Combined
Mode Option described above. The available options are:
Chassis Plans 4-9
P0-Master/P1-Slave (P27 = master/P28 = slave)
P0-Slave/P1-Master (P27 = slave/P28 = master)
Advanced Setup MX8 Technical Reference
Configure S-ATA as RAID
If the S-ATA Running Enhanced Mode option is set to No, this option is not available.
The Setup screen displays the system option:
Configure S-ATA as RAID [No]
Available options are:
No
Ye s
Primary IDE Master/Primary IDE Slave
Secondary IDE Master/Secondary IDE Slave
Third IDE Master/Fourth IDE Master
The SBC has an enhanced IDE (EIDE) interface which can support up to four IDE disk
drives through a primary and secondary controller in a master/slave configuration, P11
and P11A. Each of the four drives may be a different type. Two serial ATA devices can
also be supported (P27 and P28).
Devices attached to the primary and secondary controllers and the serial ATA ports are
detected automatically by AMIBIOS and displayed on the IDE Configuration screen.
The number of line items which display depends on the settings of the IDE Configu-
ration options described above.
The Setup screen displays the system options:
Primary IDE Master [Hard Disk]
Primary IDE Slave [Hard Disk]
Secondary IDE Master [ATAPI CDROM]
Secondary IDE Slave [Not Detected]
Third IDE Master [Not Detected]
Fourth IDE Master [Not Detected]
To view and/or change parameters for any IDE device, press <Enter> to proceed to the
IDE Device Setup screen, which is described later in this section.
Hard Disk Write Protect
This option allows you to disable or enable device write protection. Write protection will
be effective only if the device is accessed through the BIOS.
The Setup screen displays the system option:
Hard Disk Write Protect [Disabled]
Available options are:
Disabled
Enabled
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Advanced SetupMX8 Technical Reference
IDE Detect Time Out (Sec)
This option allows you to select the time-out value (in seconds) for detecting an ATA/
ATAPI device.
The Setup screen displays the system option:
IDE Detect Time Out (Sec) [35]
Available options are:
0
5
10
15
20
25
30
35
ATA(PI) 80Pin Cable Detection
This option allows you to select the mechanism for detecting an 80-pin ATA(PI) cable.
The Setup screen displays the system option:
ATA(PI) 80Pin Cable Detection [Host & Device]
Available options are:
Host & Device
Host
Device
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Advanced Setup MX8 Technical Reference
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Advanced SetupMX8 Technical Reference
IDE DEVICE SETUP When you select one of the IDE devices from the IDE Configuration screen, a Setup
screen similar to the following displays:
BIOS SETUP UTILITY
|Advanced|
Primary IDE Master
_____________________________________________
Device :Hard Disk
Vendor :ST380823-A
Size :840.0GB
LBA Mode :Supported
Block Mode:16Sectors
PIO Mode :4
Async DMA :MultiWord DMA-2
Ultra DMA :Ultra DMA-5
S.M.A.R.T.:Supported
_____________________________________________
Type [Auto}
LBA/Large Mode [Auto]
Block (Multi-Sector Transfer) [Auto]
PIO Mode [Auto]
DMA Mode [Auto]
S.M.A.R.T. [Auto]
32Bit Data Transfer [Disabled]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Select the type
of device connected
to the system.
←→ Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
IDE Device Screen
When you display the IDE Device subscreen, the format is similar to the sample shown
above. The data displayed on the top portion of the screen details the parameters
detected by AMIBIOS for the specified device and may not be modified. The data
displayed on the bottom portion of the screen may be modified.
The drive information which displays the first time the BIOS Setup Utility is run
indicates the drive(s) on your system which AMIBIOS detected upon initial bootup.
IDE D
EVICE SETUP
OPTIONS
The following options are available for each of the IDE devices on the primary and
secondary IDE controllers:
Type
This option allows you to specify what type of device is on the IDE controller.
The Setup screen displays the system option:
Type [Auto]
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Advanced Setup MX8 Technical Reference
Available options are:
Not Installed
Auto
CDROM
ARMD
If Not Installed is selected, the other options on the bottom portion of this screen do not
display.
LBA/Large Mode
This option allows you to enable IDE LBA (Logical Block Addressing) Mode for the
specified IDE drive. Data is accessed by block addresses rather than by the traditional
cylinder-head-sector format. This allows you to use drives larger than 528MB.
The Setup screen displays the system option:
LBA/Large Mode [Auto]
Two options are available:
• Select Disabled to have AMIBIOS use the physical parameters of the hard
disk and do no translation to logical parameters. The operating system
which uses the parameter table will then see only 528MB of hard disk space
even if the drive contains more than 528MB.
• Select Auto to enable LBA mode and translate the physical parameters of
the drive to logical parameters. LBA Mode must be supported by the drive
and the drive must have been formatted with LBA Mode enabled.
Block (Multi-Sector Transfer) Mode
This option supports transfer of multiple sectors to and from the specified IDE drive.
Block mode boosts IDE drive performance by increasing the amount of data transferred
during an interrupt.
If Block Mode is set to Disabled, data transfers to and from the device occur one sector
at a time.
The Setup screen displays the system option:
Block (Multi-Sector Transfer) [Auto]
Available options are:
Disabled
Auto
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Advanced SetupMX8 Technical Reference
PIO Mode
IDE Programmed I/O (PIO) Mode programs timing cycles between the IDE drive and
the programmable IDE controller. As the PIO mode increases, the cycle time decreases.
Set the PIO Mode option to Auto to have AMIBIOS select the PIO mode used by the
IDE drive being configured. If you select a specific value for the PIO mode, you must
make absolutely certain that you are selecting the PIO mode supported by the IDE drive
being configured.
The Setup screen displays the system option:
PIO Mode [Auto]
Available options are:
Auto
0
1
2
3
4
DMA Mode
This option allows you to select DMA Mode for the device.
The Setup screen displays the system option:
DMA Mode [Auto]
Available options are:
Auto
SWDMA0 (SingleWord DMA 0 - 2)
SWDMA1
SWDMA2
MWDMA0 (MultiWord DMA 0 - 2)
MWDMA1
MWDMA2
UDMA0 (UltraDMA 0 - 5)
UDMA1
UDMA2
UDMA3
UDMA4
UDMA5
S.M.A.R.T.
This option allows AMIBIOS to use the SMART (Self-Monitoring Analysis and
Reporting Technology) protocol for reporting server system information over a network.
Chassis Plans 4-15
Advanced Setup MX8 Technical Reference
The Setup screen displays the system option:
S.M.A.R.T. [Auto]
Available options are:
Auto
Disabled
Enabled
32Bit Data Transfer
If the 32Bit Data Transfer parameter is set to Enabled, AMIBIOS enables 32-bit data
transfers. If the host controller does not support 32-bit transfer, this feature must be set to
Disabled.
The Setup screen displays the system option:
32Bit Data Transfer [Disabled]
Available options are:
Disabled
Enabled
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Advanced SetupMX8 Technical Reference
FLOPPY
CONFIGURATION
When you select Floppy Configuration from the Advanced Setup Menu, the following
Setup screen displays:
BIOS SETUP UTILITY
|Advanced|
Floppy Configuration
_____________________________________________
Floppy A [1.44 MB 3½]
Floppy B [Disabled]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Select the type of
floppy drive
connected to the
system.
←→ Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
F
LOPPY
CONFIGURATION
OPTIONS
Floppy Configuration Screen
When you display the Floppy Configuration screen, the format is similar to the sample
shown above. Highlight the option you wish to change and press <Enter> to display the
available settings. Select the appropriate setting and press <Enter> again to accept the
highlighted value.
The drive information which displays the first time the BIOS Setup Utility is run
indicates the drive(s) on your system which AMIBIOS detected upon initial bootup.
The descriptions for the system options listed below show the values as they appear if
you have not run the BIOS Setup Utility program yet. Once values have been defined,
they display each time the BIOS Setup Utility is run.
Floppy A/Floppy B
The floppy drive(s) in your system can be configured using these options. The Disabled
option can be used for diskless workstations.
The Setup screen displays the system options:
Floppy A [1.44 MB 3½"]
Floppy B [Disabled]
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Advanced Setup MX8 Technical Reference
Available options are:
Disabled
360 KB 5¼"
1.2 MB 5¼"
720 KB 3½"
1.44MB 3½"
2.88MB 3½"
Chassis Plans4-18
Advanced SetupMX8 Technical Reference
SUPERIO
CONFIGURATION
When you select SuperIO Configuration from the Advanced Setup Menu, the
following Setup screen displays:
SuperIO Chipset Smc27X
|Advanced|
Configure Smc27X Super IO Chipset
_______________________________________________
OnBoard Floppy Controller [Enabled]
Serial Port1 Address [3F8/IRQ4]
Serial Port2 Address [2F8/IRQ3]
Parallel Port Address [378]
Parallel Port Mode [Normal]
Parallel Port IRQ [IRQ7]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Allows BIOS to enable
or disable floppy
controller.
←→ Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
S
UPERIO
CONFIGURATION
OPTIONS
SuperIO Configuration Screen
When you display the SuperIO Configuration screen, the format is similar to the sample
shown above. Highlight the option you wish to change and press <Enter> to display the
available settings. Select the appropriate setting and press <Enter> again to accept the
highlighted value.
The descriptions for the system options listed below show the values as they appear if
you have not run the BIOS Setup Utility program yet. Once values have been defined,
they display each time the BIOS Setup Utility is run.
OnBoard Floppy Controller
The on-board floppy drive controller may be enabled or disabled using this option.
The Setup screen displays the system option:
OnBoard Floppy Controller [Enabled]
Available options are:
Disabled
Enabled
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Advanced Setup MX8 Technical Reference
Serial Port1 Address/Serial Port2 Address
Each of these options enables the specified serial port on the SBC and establishes the
base I/O address and the number of the interrupt request for the port.
The Setup screen displays the system option:
Serial Port1 Address [3F8/IRQ4]
Serial Port2 Address [2F8/IRQ3]
Available options are:
Disabled
3F8/IRQ4
3E8/IRQ4
2F8/IRQ3
2E8/IRQ3
_______________________________________________________________________
NOTE: The values available for each on-board serial port may vary, depending on the
setting previously selected for the other on-board serial port and any off-board serial
ports. If an I/O address is assigned to another serial port, AMIBIOS automatically omits
that address from the values available.
_______________________________________________________________________
If the system has off-board serial ports which are configured to specific starting I/O ports
via jumper settings, AMIBIOS configures the on-board serial ports to avoid conflicts.
When AMIBIOS checks serial ports, any off-board serial ports found are left at their
assigned addresses. Serial Port1, the first on-board serial port, is configured with the
first available address and Serial Port2, the second on-board serial port, is configured
with the next available address. The default address assignment order is 3F8H, 2F8H,
3E8H, 2E8H. Note that this same assignment order is used by AMIBIOS to place the
active serial port addresses in lower memory (BIOS data area) for configuration as
logical COM devices.
For example, if there is one off-board serial port and its address is set to 2F8H, Serial
Port1 is assigned address 3F8H and Serial Port2 is assigned address 3E8H. Configuration is then as follows:
COM1 - Serial Port1 (at 3F8H)
COM2 - off-board serial port (at 2F8H)
COM3 - Serial Port2 (at 3E8H)
Parallel Port Address
This option enables the parallel port on the SBC and establishes the base I/O address for
the port.
The Setup screen displays the system option:
Parallel Port Address [378]
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Advanced SetupMX8 Technical Reference
Available options are:
Disabled
378
278
3BC
When AMIBIOS checks for parallel ports, any off-board parallel ports found are left at
their assigned addresses. The on-board Parallel Port is automatically configured with the
first available address not used by an off-board parallel port.
If this option is set to Disabled, the Parallel Port Mode and Parallel Port IRQ options
are not available.
Parallel Port Mode
This option specifies the parallel port mode. ECP and EPP are both bidirectional data
transfer schemes which adhere to the IEEE P1284 specifications.
If the Parallel Port Address option is set to Disabled, this option is not available for
modification.
The Setup screen displays the system option:
Parallel Port Mode [Normal]
Four options are available:
• Select Normal to use normal parallel port mode.
• Select Bi-Directional to use bi-directional parallel port mode.
• Select EPP to allow the parallel port to be used with devices which adhere
to the Enhanced Parallel Port (EPP) specification. EPP uses the existing
parallel port signals to provide asymmetric bidirectional data transfer driven
by the host device.
• Select ECP to allow the parallel port to be used with devices which adhere
to the Extended Capabilities Port (ECP) specification. ECP uses the DMA
protocol to achieve transfer rates of approximately 2.5MB/second. ECP
provides symmetric bidirectional communication.
Parallel Port IRQ
This option specifies the interrupt request (IRQ) which is used by the parallel port.
If the Parallel Port Address option is set to Disabled, this option is not available for
modification.
The Setup screen displays the system option:
Chassis Plans 4-21
Parallel Port IRQ [IRQ7]
Advanced Setup MX8 Technical Reference
Available options are:
IRQ5
IRQ7
Chassis Plans4-22
Advanced SetupMX8 Technical Reference
REMOTE ACCESS
CONFIGURATION
When you select Remote Access Configuration from the Advanced Setup Menu, the
following Setup screen displays:
BIOS SETUP UTILITY
|Advanced|
Configure Remote Access Type and Parameters
_____________________________________________
Remote Access [Serial]
Serial Port Number [COM1]
Serial Port Mode [57600 8,n,1]
Post-Boot Support [Disabled]
vxx.xx (C)Copyright 1985-2002, American Megatrends, Inc.
Select Remote access
type
←→ Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
R
EMOTE ACCESS
CONFIGURATION
OPTIONS
Remote Access Configuration Screen
When you display the Remote Access Configuration screen, the format is similar to the
sample shown above if you have enabled Remote Access. Highlight the option you wish
to change and press <Enter> to display the available settings. Select the appropriate
setting and press <Enter> again to accept the highlighted value.
The descriptions for the system options listed below show the values as they appear if
you have not run the BIOS Setup Utility program yet. Once values have been defined,
they display each time the BIOS Setup Utility is run.
Remote Access
This option allows you to use a terminal connected to the serial port of the SBC to
control changes to the BIOS settings.
If this option is set to Disabled, the Serial Port Number, Serial Port Mode and Post-
Boot Support options are not available.
The Setup screen displays the system option:
Remote Access [Disabled]
Chassis Plans 4-23
Advanced Setup MX8 Technical Reference
Available options are:
Disabled
Serial
Serial Port Number
This option specifies the serial port on which remote access is to be enabled.
If the Remote Access option is set to Disabled, this option is not available.
The Setup screen displays the system option:
Serial Port Number [COM1]
Available options are:
COM1
COM2
Serial Port Mode
This option specifies settings for the serial port on which remote access is enabled. The
settings indicate baud rate, eight bits per character, no parity and one stop bit.
If the Remote Access option is set to Disabled, this option is not available.
The Setup screen displays the system option:
Serial Port Mode [57600 8,n,1]
Available options are:
115200 8,n,1
57600 8,n,1
19200 8,n,1
Post-Boot Support
This option specifies whether or not to keep redirection active after booting to DOS.
If the Remote Access option is set to Disabled, this option is not available.
The Setup screen displays the system option:
Post-Boot Support [Disabled]
Two options are available:
• Select Disabled to deactivate redirection.
• Select Enabled to keep redirection active.
Chassis Plans4-24
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