Chassis Plans JXT6966, JXTS6966 Hardware Technical Reference

JXT6966 / JXTS6966

S6966-xxx

Revision

HARDWARE

TECHNICAL REFERENCE

Intel® Xeon® C5500-series

Quad Core

PROCESSOR-BASED

A

SHB

WARRANTY

The following is an abbreviated version of Chassis Plans’ warranty policy for PICMG 1.3 products. For a
complete warranty statement, contact Chassis Plans or visit our website at www.Chassis-Plans.com.

Chassis Plans PICMG 1.3 products are warranted against material and manufacturing defects for five
years from date of delivery to the original purchaser. Buyer agrees that if this product proves defective
Chassis Plans is only obligated to repair, replace or refund the purchase price of this product at Chassis
Plans’ discretion. The warranty is void if the product has been subjected to alteration, neglect, misuse or
abuse; if any repairs have been attempted by anyone other than Chassis Plans; or if failure is caused by
accident, acts of God, or other causes beyond the control of Chassis Plans. Chassis Plans reserves the right
to make changes or improvements in any product without incurring any obligation to similarly alter
products previously purchased.

In no event shall Chassis Plans be liable for any defect in hardware or software or loss or inadequacy of
data of any kind, or for any direct, indirect, incidental or consequential damages arising out of or in
connection with the performance or use of the product or information provided. Chassis Plans liability
shall in no event exceed the purchase price of the product purchased hereunder. The foregoing limitation
of liability shall be equally applicable to any service provided by Chassis Plans

RETURN POLICY

Products returned for repair must be accompanied by a Return Material Authorization (RMA) number,
obtained from Chassis Plans prior to return. Freight on all returned items must be prepaid by the customer,
and the customer is responsible for any loss or damage caused by common carrier in transit. Items will be
returned from Chassis Plans via Ground, unless prior arrangements are made by the customer for an alter­native shipping method

To obtain an RMA number, call us at [phone]. We will need the following information:

Return company address and contact
Model name and model # from the label on the back of the product
Serial number from the label on the back of the product
Description of the failure

An RMA number will be issued. Mark the RMA number clearly on the outside of each box, include a
failure report for each board and return the product(s) to our San Diego, CA facility:

Chassis Plans
10123 Carroll Canyon Rd.
San Diego, CA 92131
Attn: Repair Department

Contact Chassis Plans for our complete service and repair policy.

TRADEMARKS

IBM, PC/AT, VGA, EGA, OS/2 and PS/2 are trademarks or registered trademarks
of International Business Machines Corp.
AMI and AMIBIOS are trademarks of American Megatrends Inc.
Intel, Xeon, Intel Quick Path Interconnect, Intel Hyper-Threading Technology and Intel Virtualization
Technology are trademarks or registered trademarks of Intel Corporation.
MS-DOS and Microsoft are registered trademarks of Microsoft Corp.
PICMG, SHB Express and the PICMG logo are trademarks or registered trademarks
of the PCI Industrial Computer Manufacturers Group.
PCI Express is a trademark of the PCI-SIG
All other brand and product names may be trademarks or registered trademarks
of their respective companies.

LIABILITY DISCLAIMER

This manual is as complete and factual as possible at the time of printing; however, the information in this
manual may have been updated since that time. Chassis Plans reserves the right to change the functions,
features or specifications of their products at any time, without notice.

Copyright © 2010 by Chassis Plans. All rights reserved.

E-mail: [e-mail]
Web: www.Chassis-Plans.com

Chassis Plans
10123 Carroll Canyon Road • San Diego, CA 92131
Sales: [phone] • Fax: [phone] • Web: www.Chassis-Plans.com

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Table of Contents

CHAPTER 1 SPECIFICATIONS ........................................................................................................... 1-1

Introduction ....................................................................................................................................................... 1-1

Dual-Processor Models .................................................................................................................................... 1-1

Single-Processor Models ................................................................................................................................. 1-2

Features ............................................................................................................................................................. 1-2

JXT6966 (S6966-xxx) – Dual-Processor SHB Block Diagram ....................................................................... 1-3

JXT6966 (S6966-xxx) – Dual-Processor SHB Layout Diagram ..................................................................... 1-4

JXTS6966 (S6966-xxx) – Single-Processor SHB Block Diagram ................................................................. 1-5

JXTS6966 (S6966-xxx) – Single-Processor SHB Layout Diagram ............................................................... 1-6

Processor .......................................................................................................................................................... 1-7

Serial Interconnect Interface ........................................................................................................................... 1-7

Data Path ........................................................................................................................................................... 1-7

Serial Interconnect Speeds ............................................................................................................................. 1-7

Intel® Quick Path Iinterconnect Supported Speeds Between CPUs ........................................................... 1-7

Intel® Direct Media Iinterface (DMI)Speed Between Processor and Intel® 3420 PCH ............................... 1-7

Memory Interface .............................................................................................................................................. 1-7

DMA Channels .................................................................................................................................................. 1-7

Interrupts ........................................................................................................................................................... 1-7

Bios (Flash) ....................................................................................................................................................... 1-7

Cache Memory .................................................................................................................................................. 1-7

DDR3-1333 Memory .......................................................................................................................................... 1-8

Universal Serial Bus (USB) .............................................................................................................................. 1-8

Video Interface .................................................................................................................................................. 1-8

PCI Express Interfaces ..................................................................................................................................... 1-9

Ethernet Interfaces ........................................................................................................................................... 1-9

Serial ATA/300 Ports ........................................................................................................................................ 1-9

Power Fail Detection ...................................................................................................................................... 1-10

Battery ............................................................................................................................................................. 1-10

Power Requirements ...................................................................................................................................... 1-10

Temperature/Environment ............................................................................................................................. 1-11

Mechanical ...................................................................................................................................................... 1-11

Board Stiffener Bars ....................................................................................................................................... 1-11

UL Recognition ............................................................................................................................................... 1-11

Configuration Jumpers .................................................................................................................................. 1-12

P4A/P4B Ethernet LEDs and Connectors .................................................................................................... 1-13

Status LEDs ..................................................................................................................................................... 1-13

System BIOS Setup Utility ............................................................................................................................. 1-14

Connectors ...................................................................................................................................................... 1-15

CHAPTER 2 PCI EXPRESS® REFERENCE ........................................................................................ 2-1

Introduction ....................................................................................................................................................... 2-1

PCI Express Links ............................................................................................................................................ 2-1

SHB Configurations .......................................................................................................................................... 2-2

PCI Express Edge Connector Pin Assignments ............................................................................................ 2-3

PCI Express Signals Overview ........................................................................................................................ 2-6

Optional PCI Express Link Expansion ........................................................................................................... 2-7

CHAPTER 3 JXT6966 / JXTS6966 SYSTEM POWER CONNECTIONS ............................................. 3-1

Introduction ....................................................................................................................................................... 3-1

Power Supply and SHB Interaction ................................................................................................................ 3-1

Electrical Connection Configurations ............................................................................................................ 3-2

CHAPTER 4 PCI EXPRESS BACKPLANE USAGE ............................................................................ 4-1

Introduction ....................................................................................................................................................... 4-1

SHB Edge Connectors ..................................................................................................................................... 4-1

Off-Board Video Card Usage ........................................................................................................................... 4-3

JXT6966 & JXTS6966 and Compatible Chassis Plans Backplanes ............................................................. 4-3

2U Butterfly Backplanes .................................................................................................................................. 4-3

Multi-Segment Backplanes .............................................................................................................................. 4-3

Combo Backplanes .......................................................................................................................................... 4-3

Server-Class Backplanes ................................................................................................................................. 4-3

Graphics-Class Backplanes ............................................................................................................................ 4-3

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JXT6966 / JXTS6966 Technical Reference

CHAPTER 5 I/O EXPANSION BOARDS – IOB33 & PEX10 ................................................................ 5-1

IOB33 Overview ................................................................................................................................................ 5-1

IOB33 Models .................................................................................................................................................... 5-1

Model # Model Name Description .............................................................................................................. 5-1

IOB33 Features ................................................................................................................................................. 5-2

IOB33 Temperature/Environment ................................................................................................................... 5-2

IOB33 (S7015-xxx) Block Diagram .................................................................................................................. 5-2

IOB33 (S7015-xxx) Layout Diagram ................................................................................................................ 5-3

IOB33 (S7015-xxx) I/O Plate Diagram ............................................................................................................. 5-3

IOB33 Connectors ............................................................................................................................................ 5-4

IOB33 Connectors (continued) ........................................................................................................................ 5-5

PEX10 Overview................................................................................................................................................ 5-7

APPENDIX A BIOS MESSAGES ........................................................................................................... A-1

Introduction ....................................................................................................................................................... A-1

Aptio Boot Flow ................................................................................................................................................ A-1

BIOS Beep Codes ............................................................................................................................................. A-1

PEI Beep Codes ................................................................................................................................................ A-1

DXE Beep Codes............................................................................................................................................... A-2

BIOS Status Codes ........................................................................................................................................... A-3

BIOS Status POST Code LEDs ........................................................................................................................ A-3

Status Code Ranges ......................................................................................................................................... A-4

SEC Status Codes ............................................................................................................................................ A-4

SEC Beep Codes............................................................................................................................................... A-4

PEI Beep Codes ................................................................................................................................................ A-7

DXE Status Codes ............................................................................................................................................ A-7

DXE Beep Codes............................................................................................................................................... A-9

ACPI/ASL Status Codes ................................................................................................................................. A-10

OEM-Reserved Status Code Ranges ............................................................................................................ A-10

ii CHASSIS PLANS

JXT6966 / JXTS6966 Technical Reference

HANDLING PRECAUTIONS

WARNING: This product has components which may be damaged by electrostatic discharge.

To protect your system host board (SHB) from electrostatic damage, be sure to observe the following
precautions when handling or storing the board:

 Keep the SHB in its static-shielded bag until you are ready to perform your installation.

 Handle the SHB by its edges.

 Do not touch the I/O connector pins.

 Do not apply pressure or attach labels to the SHB.

 Use a grounded wrist strap at your workstation or ground yourself frequently by touching the

metal chassis of the system before handling any components. The system must be plugged into an
outlet that is connected to an earth ground.

 Use antistatic padding on all work surfaces.

 Avoid static-inducing carpeted areas.

RECOMMENDED BOARD HANDLING PRECAUTIONS

This SHB has components on both sides of the PCB. Some of these components are extremely small and
subject to damage if the board is not handled properly.

It is important for you to observe the following

precautions when handling or storing the board to prevent components from being damaged or broken off:

 Handle the board only by its edges.

 Store the board in padded shipping material or in an anti-static board rack.

 Do not place an unprotected board on a flat surface.

CHASSIS PLANS iii

JXT6966 / JXTS6966 Technical Reference

Population order

CPU1

CPU2*

1

BK00

BK10

2

BK01

BK11

3

BK02

BK12

Before You Begin

INTRODUCTION

It is important to be aware of the system considerations listed below before installing your JXT6966 or
JXTS6966 (S6966-xxx) SHB. Overall system performance may be affected by incorrect usage of these
features.

MOUSE/KEYBOARD “Y” CABLE

If you have an IOB33 I/O board in your system and you are using a “Y” cable attached to the bracket

mounted mouse/keyboard mini Din connector, be sure to use Chassis Plans’ “Y” cable, part number 5886-

000. Using a non-Chassis Plans cable may result in improper SHB operation.

DDR3-1333 MEMORY

Chassis Plans recommends ECC registered DDR3 memory modules for use on the JXT6966/JXTS6966
SHBs and these ECC registered (72-bit) DDR3 Mini-DIMMs must be PC3-10600 or PC3-8500 compliant.
Unbuffered ECC DDR3 Mini-DIMMs are also supported on the JXT boards, but you cannot mix the two
different memory types on the same SHB.

NOTES:

 To maximize system performance and reliability, Chassis Plans recommends populating

each memory channel with DDR3 Mini-DIMMs with the same interface speed.

 All memory modules must have gold contacts.
 Low voltage (DDR3L) Mini-DIMMs are not supported.
 The SHB supports the following memory module memory latency timings:

o 6-6-6 for 800MHz DDR3 Mini-DIMMs
o 7-7-7 and 8-8-8 for 1066MHz DDR3 Mini-DIMMs
o 9-9-9 for 1333MHz DDR3 Mini-DIMMs

 Populating the memory sockets with Mini-DIMMs having different speeds is supported

on the SHB; however, the overall memory interface speed will run at the speed of the
slowest Mini-DIMM.

 Populate the memory sockets starting with the Mini-DIMM socket closest to the CPU

and work your way toward the edges of the SHB as illustrated in the chart below:

*CPU2 is available on the JXT6966 dual-processor board version only

*Using a balanced memory population approach ensures maximum memory interface
performance. A “balance approach” means using an equal number of Mini-DMMs
for each processor on a dual-processor JXT6966 SHB whenever possible.

The memory DIMMs on the SHB connect directly to the CPU and at least one memory module must be
installed on the board. The JXTS6966 SHB versions feature one processor; however, memory sockets
BK10, BK11 and BK12 are installed on the SHB but are not active in this single-processor board version.

SATA RAID OPERATION

The Intel® 3420 Platform Controller Hub (PCH) used on the SHB features Intel® Rapid Storage
Technology (Intel® RST), which allows the PCH’s SATA controller to be configured as a RAID controller
supporting RAID 0, 1, 5 and 10 implementations. To configure the SATA ports as RAID drives or to use
advanced features of the PCH, you must install the Intel® RST driver software. A link to the software is
also located on Chassis Plans’ website by accessing the Downloads tab of the JXT6966 product detail page
or the RAID Drivers section of the Technical Support page.

iv CHASSIS PLANS

JXT6966 / JXTS6966 Technical Reference

POWER CONNECTION

The PICMG® 1.3 specification supports soft power control signals via the Advanced Configuration and
Power Interface (ACPI). The JXT6966/JXTS6966 supports these signals, controlled by the ACPI and are
used to implement various sleep modes. When control signals are implemented, the type of ATX or EPS
power supply used and the operating system software will dictate how system power should connect to the

SHB. It is critical that the correct method be used. Refer to - Power Connection section in the JXT manual
to determine the method that will work with your specific system design. The Advanced Setup chapter in

the manual contains the ACPI BIOS settings.

PCI EXPRESS 2.0 LINKS AND PICMG® 1.3 BACKPLANES

The PCI Express® links on the JXT6966 connect directly to the processors. These links can operate as
either PCI Express 2.0 or PCI Express 1.1 links based on the end-point devices on the backplane that are
connected to the SHB. In addition to automatically configuring themselves for either PCIe 2.0 or PCIe 1.1
operations, the links also configure themselves for either graphics or server-class operations. In other
words, the multiple x4 links from the processors (links A0, A1, A2 and A3) can be combined into a single
x16 PCIe electrical link or multiple x8 links on a backplane. The CPU’s x4 links can train down to x1
links, but cannot bifurcate into multiple x1 links. The PCIe link (B0) from the board’s PCH has a x4
default configuration and can be made to bifurcate into four, x1 PCIe links with a factory modification to
the JXT board. Contact Chassis Plans if you require this B0 link configuration change. An optional
PEX10 module connected to a dual-processor JXT6966 provides more backplane links than are currently
supported in the PICMG 1.3 specification. This JXT6966 capability provides additional PCI Express

bandwidth and option card support in the system design. Refer to the PCI Express® Reference chapter and
to Appendix C - PCI Express Backplane Usage of this manual for more information.

PICMG 1.3 BACKPLANE I/O

The JXT6966 and JXTS6966 enable the following PICMG 1.3 backplane I/O connectivity via the SBC’s
edge connector C:

 Four USB 2.0 interfaces
 One 10/100Base-T Ethernet interface

PICMG 1.3 BACKPLANE CLASSIFICATION

The JXT6966 and JXTS6966 are system host boards that can operate as either a Server or Graphics-Class
PICMG 1.3 SHB. The JXT SHBs are essentially combo-class boards because of the capabilities of the PCI
Express links built into the SHB’s processors. Chassis Plans recommends using a combo-class PICMG 1.3
backplane such as the Chassis Plans BPC7009 or BPC7041 with the SHBs in order to ensure the use of all

available backplane option card slots. See Appendix C, PCI Express Backplane Usage for more details.

OFF-BOARD VIDEO CARD USAGE

If the system design requires an off-board video card, then the card must be placed in a backplane slot
driven with PCI Express links from the JXT6966’s first processor. This is an Aptio® 4.x BIOS limitation
that may be corrected in future software revisions. Listed below are the acceptable BPC7009 and BPC7041
backplane slots for use with an off-board video card:
BPC7009 - Card slot PCIe1, PCIe2 or PCIe3
BPC7041 - Card slot PCIe6, PCIe7, PCIe8, PCIe9 or PCIe10

BIOS

The JXT6966 and JXTS6966 feature the Aptio® 4.x BIOS from American Megatrends, Inc. (AMI) with a
ROM-resident setup utility called the Aptio Text Setup Environment or TSE. Details of the Aptio TSE are

provided in the separate JXT6966 / JXTS6966 BIOS Technical Reference manual.

FOR MORE INFORMATION

For more information on any of these features, refer to the appropriate sections JXT6966 / JXTS6966
Hardware Technical Reference Manual. The BIOS and hardware technical reference manuals are available

under the Downloads tab on the JXT6966 or JXTS6966 web pages.

CHASSIS PLANS v

JXT6966 / JXTS6966 Technical Reference

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vi CHASSIS PLANS

JXT6966 / JXTS6966 Technical Reference Specifications

Model #

Model Name

Speed

Intel CPU Number

S6966-053

JXT/2.0QMR

2.0GHz

EC5509

S6966-125

JXT/2.53QN

2.53GHz

EC5549

S6966-224

JXT/2.13QM

2.13GHz

LC5528

S6966-222

JXT/1.73QM

1.73GHz

LC5518

S6966-425

JXT/2.27DNR

2.27GHz

EC5539

Chapter 1 Specifications

Introduction

The JXT6966 and JXTS6966 are combo-class, PICMG® 1.3 system host boards that support the Intel®
Xeon® C5500 processors. These CPUs feature the Nehalem micro-architecture and were developed under
the codename Jasper Forest. The processors have a DDR3 integrated memory controller that supports three
DDR3-1333 memory interface channels per processor resulting in six direct access memory interfaces on
the JXT6966 board version. The six interfaces connect to six DDR3 Mini-DIMM sockets. With 4GB
DDR3 Mini-DIMMs the total system memory capacity for a JXT6966 is 24GB and will double to 48GB
once 8GB DDR3 Mini-DIMMs come on the market. The maximum theoretical system memory capacity
for the JXT6966 is 192GB. The system memory capacities are cut in half for the single processor
JXTS6966 board version.

PCI Express 2.0/1.1 links are built into the processors and the Intel® Quick Path Interface (Intel® QPI)
between processors on the JXT6966 enables CPU resource sharing for an additional system throughput
speed boost. All of the PCI Express interface links needed for a PICMG 1.3 compliant backplane are
provided by the PCIe links out of CPU1 and the additional link out of the Intel® 3420 Platform Controller
Hub (PCH). CPU2 on the JXT6966 provides four additional x4 PCI Express 2.0 or 1.1 links to a backplane
via an optional plug-in card called the Chassis Plans PEX10. These extra links provide added bandwidth to
systems equipped with a backplane such as the Chassis Plans BPC7009 or BPC7041. An optional IOB33
module provides an extra x1 PCIe 1.1 link to a backplane equipped with a PCIe expansion slot.

Video and I/O features on the JXT boards include:

 A Graphics Processing Unit (GPU) driven with an internal x1 PCIe link and capable of

supporting pixel resolutions up to 1920 x 1200 (WUXGA) with a 64k color depth

 Three Gigabit Ethernet interfaces with two on the I/O plate and one available for use on a

PICMG 1.3 compliant backplane

 Six SATA/300 ports that can support independent drives or RAID drive arrays
 Eight USB 2.0 interfaces

The listing below summarizes the available versions of the JXT6966 and JXTS6966 system host boards.

Dual-Processor Models

Dual Intel Xeon Processors (Jasper Forest) - Quad Core, 4.8GT/s QPI, 8MB cache, No H-T*:

* H-T = Intel Hyper-Threading

Dual Intel Xeon Processors (Jasper Forest) - Quad Core, 5.86GT/s QPI, 8MB cache, With H-T:

Dual Intel Xeon Processors (Jasper Forest) - Quad Core, 4.8GT/s QPI, 8MB cache, With H-T:

Dual Intel Xeon Processors (Jasper Forest) - Dual Core, 5.86GT/s QPI, 4MB cache, No H-T:

1-1 CHASSIS PLANS

Specifications JXT6966 / JXTS6966 Technical Reference

Model #

Model Name

Speed

Intel CPU Number

S6966-093

JXTS/2.0QMR

2.0GHz

EC5509

S6966-165

JXTS/2.53QN

2.53GHz

EC5549

S6966-264

JXTS/2.13QM

2.13GHz

LC5528

S6966-262

JXTS/1.73QM

1.73GHz

LC5518

S6966-465

JXTS/2.27DNR

2.27GHz

EC5539

Single-Processor Models

Single Intel Xeon Processor (Jasper Forest) - Quad Core, 4.8GT/s QPI, 8MB cache, No H-T*:

* H-T = Intel Hyper-Threading

Single Intel Xeon Processor (Jasper Forest) - Quad Core, 5.86GT/s QPI, 8MB cache, With H-T:

Single Intel Xeon Processor (Jasper Forest) - Quad Core, 4.8GT/s QPI, 8MB cache, With H-T:

Single Intel Xeon Processor (Jasper Forest) - Dual Core, 5.86GT/s QPI, 4MB cache, No H-T:

Features

 Intel® Xeon® C5500 Processors (Jasper Forest)
 Intel® 3420 Platform Controller Hub
 Direct PCI Express® 2.0 links into the Intel® Xeon® C5500 Processors
 A Combo-class SHB that is compatible with PCI Industrial Computer Manufacturers Group

(PICMG) 1.3 Specifiction

 Direct PCI Express® 2.0 links into the Intel® Xeon® C5500 Processors
 JXT6966 provides a total of 37 lanes of PCI Express for off-board system integration
 Direct DDR3-1333 Memory Interfaces into the Intel® Xeon® C5500 Processors
 Six DDR3 Mini-DIMM sockets capable of supporting up to 192GB of system memory on a dual-

processor JXT6966, 24GB maximum capacity with readily available 4GB DDR3 Mini-DIMMs

 Video interface utilizing XGI® Volari™ Z11M Graphice Processing Unit
 Two 10/100/1000Base-T Ethernet interfaces available on the SHB’s I/O plate
 Six Serial on-board ATA/300 ports support four independent SATA storage devices

 SATA/300 ports may be configured to support RAID 0, 1, 5 or 10 implementations

 Eight Universal Serial Bus (USB 2.0) interfaces
 Off-board I/O support provided for one 10/100Base-T Ethernet interface and four USB 2.0 port

connections on a PICMG 1.3 backplane

 Legacy I/O, dual serial port and x1 PCIe link expansion available via Chassis Plans IOB33

expansion board

 An additional 16 PCI Express 2.0 lanes are available when using an optional PEX10 board on a

JXT6966 connected to a Chassis Plans BPC7009 or BPC7041 PICMG 1.3 backplane

 Full-length stiffner bars on the rear of the SHB enhances the rugged nature on the board by

maximizing component protection and simplifying mechanical system integration

 Full PC compatibility

CHASSIS PLANS 1-2

JXT6966 / JXTS6966 Technical Reference Specifications

JXT6966 (S6966-xxx) – Dual-Processor SHB Block Diagram

1-3 CHASSIS PLANS

Specifications JXT6966 / JXTS6966 Technical Reference

JXT6966 (S6966-xxx) – Dual-Processor SHB Layout Diagram

CHASSIS PLANS 1-4

JXT6966 / JXTS6966 Technical Reference Specifications

JXTS6966 (S6966-xxx) – Single-Processor SHB Block Diagram

1-5 CHASSIS PLANS

Specifications JXT6966 / JXTS6966 Technical Reference

JXTS6966 (S6966-xxx) – Single-Processor SHB Layout Diagram

CHASSIS PLANS 1-6

JXT6966 / JXTS6966 Technical Reference Specifications

Processor

 Intel® Xeon® C5500 Series Processor – Nehalem-EP micro-architecture (Jasper Forest)r
 Processor plugs into an LGA1366 socket

Serial Interconnect Interface

PCI Express® 2.0 and 1.1 compatible

Data Path

DDR3-1333 Memory - 72-bit (per channel)

Serial Interconnect Speeds

PCI Express 2.0 – 5.0GHz per lane
PCI Express 1.1 - 2.5GHz per lane

Intel® Quick Path Interconnect Supported Speeds Between CPUs

The Intel® 3420 PCH supports 4.8GT/s or 5.86GT/s between processors. The speed of the Intel® QPI
depends on the type of CPU installed. The Quick Path Interconnect enables both processor-to-processor
resource sharing and fast data transfers between CPUs and the Intel® 3420 PCH.

Intel® Direct Media Interface (DMI)Speed Between Processor and Intel® 3420 PCH

This full duplex interface operates at 10Gb/s in each direction and provides data communications between
the PCH and processor. On a dual-processor, JXT6966 the first CPU connects to the PCH and the second
CPU feeds its information to the PCH via the first CPU’s DMI link.

Memory Interface

Three DDR3-1333MHz memory channels per processor; peak memory interface bandwidth is 32GB/s
when using PC3-10600 Mini-DIMMs.

DMA Channels

The SHB is fully PC compatible with seven DMA channels, each supporting type F transfers.

Interrupts

The SHB is fully PC compatible with interrupt steering for PCI plug and play compatibility.

Bios (Flash)

The JXT boards use an Aptio® 4.x BIOS from American Megatrends Inc. (AMI). The BIOS features built­in advanced CMOS setup for system parameters, peripheral management for configuring on-board
peripherals and other system parameters. The BIOS resides in a 32Mb Atmel® AT25DF321SU SPI Serial
EEPROM (SPI Flash). The BIOS may be upgraded from a USB thumb drive storage device by pressing
<Ctrl> + <Home> immediately after reset or power-up with the USB device installed in drive A:. Custom
BIOSs are available.

Cache Memory

The processors include either a 4MB or 8MB last-level cache (LLC) memory capacity that is equally
shared between all of the processor cores on the die.

1-7 CHASSIS PLANS

Specifications JXT6966 / JXTS6966 Technical Reference

Population order

CPU1

CPU2*

1

BK00

BK10

2

BK01

BK11

3

BK02

BK12

DDR3-1333 Memory

Each processor on the SHB supports three separate DDR3-1333 memory interfaces. There are six active
Mini-DIMM sockets on the JXT6966 models and each one can support up to 32GB DIMMs for a total
possible DDR3 system memory capacity of 192GB. The single processor models support three active Mini-

DIMM sockets and each socket can support up to 32GB DIMMs for a total possible DDR3 system memory capacity of
96GB on a JXTS6966. However, currently available DDR3 Mini-DIMM memory capacities of 2GB, 4GB

and 8GB are more common in today’s market; thereby, making the maximum practical limit of system
memory supported 48GB on dual-processor SHBs and 24GB on single processor models. The peak
memory interface bandwidth per channel is 32/GB/s when using PC3-10600 (i.e. DDR3-1333) Mini­DIMMs. Each of the direct CPU memory channel (BK##) terminates with a single in-line Mini-DIMM
memory module socket. The System BIOS automatically detects memory type, size and speed.

Chassis Plans recommends ECC registered DDR3 memory modules for use on the JXT6966/JXTS6966
SHBs and these ECC registered (72-bit) DDR3 Mini-DIMMs must be PC3-10600 or PC3-8500 compliant.
Unbuffered ECC DDR3 Mini-DIMMs are also supported on the JXT boards, but you cannot mix the two
different memory types on the same SHB.

NOTES:

 To maximize system performance and reliability, Chassis Plans recommends populating

each memory channel with DDR3 Mini-DIMMs with the same interface speed.

 All memory modules must have gold contacts.
 Low voltage (DDR3L) Mini-DIMMs are not supported.
 The SHB supports the following memory module memory latency timings:

o 6-6-6 for 800MHz DDR3 Mini-DIMMs
o 7-7-7 and 8-8-8 for 1066MHz DDR3 Mini-DIMMs
o 9-9-9 for 1333MHz DDR3 Mini-DIMMs

 Populating the memory sockets with Mini-DIMMs having different speeds is supported

on the SHB; however, the overall memory interface speed will run at the speed of the
slowest Mini-DIMM.

 Populate the memory sockets starting with the Mini-DIMM socket closest to the CPU

and work your way toward the edges of the SHB as illustrated in the chart below:

*CPU2 is available on the JXT6966 dual-processor board version only

The memory DIMMs on the SHB connect directly to the CPU and at least one memory module must be
installed on the board. The JXTS6966 SHB versions feature one processor; however, memory slots BK10,
BK11 and BK12 are installed on the SHB but are not active in this single-processor board version.

Universal Serial Bus (USB)

The SHB support eight high-speed USB 2.0 ports. Connectors for two of the USB ports (0 and 1) are on the
I/O bracket and USB ports 2 and 3 are available via headers on the SHB. USB ports 4, 5, 6 and 7 are
routed directly to edge connector C of the SHB for use on a PICMG 1.3 backplane.

Video Interface

The SHB features a Graphics Processing Unit (GPU) with 8MB of video memory, and the GPU is driven
by a x1 PCIe link from the SHB’s Intel® 3420 PCH. This combination of features enables the SHB’s
video port; located on the board’s I/O plate, to support pixel resolutions up to 1920 x 1200 (WUXGA) with
a 64k color depth.

CHASSIS PLANS 1-8

JXT6966 / JXTS6966 Technical Reference Specifications

PCI Express Interfaces

The PCI Express® links on the JXT6966 connect directly to the processors. These links can operate as
either PCI Express 2.0 or PCI Express 1.1 links based on the end-point devices on the backplane that are
connected to the SHB. In addition to automatically configuring themselves for either PCIe 2.0 or PCIe 1.1
operations, the links also configure themselves for either graphics or server-class operations. In other
words, the multiple x4 links from the processors (links A0, A1, A2 and A3) can be combined into a single
x16 PCIe electrical link or multiple x8 links on a backplane. The CPU’s x4 links can train down to x1
links, but cannot bifurcate into multiple x1 links. The PCIe link (B0) from the board’s PCH has a x4
default configuration and can be made to bifurcate into four, x1 PCIe links with a factory modification to
the JXT board. Contact Chassis Plans if you require this B0 link configuration change. An optional
PEX10 module connected to a dual-processor JXT6966 provides more backplane links than are currently
supported in the PICMG 1.3 specification. This JXT6966 capability provides additional PCI Express
bandwidth and option card support in the system design. The single processor JXTS6966 supports the
PICMG 1.3 PCI Express specification. The single processor on the JXTS6966 configures the PCIe links
for either server or graphics-class link operations based on the backplane type and the end-point devices on
the backplane. The JXTS6966 does not support the optional PEX10 link expansion module, but both SHB
models support the optional IOB33 and the IOB’s x1 PCI Express expansion link down to a backplane with

a PCIe Expansion slot. Refer to the PCI Express® Reference chapter and to Appendix C - PCI Express
Backplane Usage of this manual for more information.

Ethernet Interfaces

The JXT6966/JXTS6966 SHBs support three Ethernet interfaces. The first two interfaces are on-board
10/100/1000Base-T Ethernet interfaces located on the board's I/O bracket and implemented using an Intel®
82575EB Gigabit Ethernet Controller. These I/O bracket interfaces support Gigabit, 10Base-T and
100Base-TX Fast Ethernet modes and are compliant with the IEEE 802.3 Specification.

The main components of the I/O bracket Ethernet interfaces are:

 Intel® 82575EB for 10/100/1000-Mb/s media access control (MAC) with SYM, a serial ROM port

and a PCIe interface

 Serial ROM for storing the Ethernet address and the interface configuration and control data
 Integrated RJ-45/Magnetics module connectors on the SHB's I/O bracket for direct connection to

the network. The connectors require category 5 (CAT5) unshielded twisted-pair (UTP) 2-pair
cables for a 100-Mb/s network connection or category3 (CAT3) or higher UTP 2-pair cables for a
10-Mb/s network connection. Category 5e (CAT5e) or higher UTP 2-pair cables are recommended
for a 1000-Mb/s (Gigabit) network connection.

 Link status and activity LEDs on the I/O bracket for status indication (See Ethernet LEDs and

Connectors later in this chapter.)

The third LAN is supported by the Intel® 3420 and the Intel® 82578 Gigabit Ethernet PHY. This
10/100/1000Base-T Ethernet interface is routed to the PICMG 1.3 backplane via edge connector C of the
SHB.

Software drivers are supplied for most popular operating systems.

Serial ATA/300 Ports

The six Serial ATA (SATA) ports on the SHB are driven with a built-in SATA controller from the Intel®
3420 Platform Controller Hub (PCH). The board’s SATA/300 interfaces comply with the SATA 1.0
specification and can support six independent SATA storage devices such as hard disks and CD-RW
devices at data transfer rates up to 300MB per second on each port. The SATA controller has two BIOS
selectable modes of operation with a legacy (i.e. IDE) mode using I/O space, and an AHCI mode using

memory space. Software that uses legacy mode will not have AHCI capabilities. The board’s PCH

features Intel® Rapid Storage Technology, which allows a third BIOS-selectable SATA controller
configuration that enables a RAID configuration capable of supporting RAID 0, 1, 5 and 10 storage array
implementations.

1-9 CHASSIS PLANS

Specifications JXT6966 / JXTS6966 Technical Reference

Monitored Voltage

Nominal Low Limit

Voltage Source

+5V
+3.3V
Vcc_DDR(+1.5V)
Vtt_CPU(1.2V)
+1.05V(Chipset)
+1.80V(Chipset)

4.75 volts

2.97 volts

1.15 volts

0.85 volt

0.945 volt

1.62 volts

System Power Supply
System Power Supply
On-Board Regulator
On-Board Regulator
On-Board Regulator
On-Board Regulator

Processor Type

SHB Type

Processor
Speed

+5V

+12V

+3.3V
CPU Idle State:

Intel Xeon C5500
Quad-Core (EC5549)

JXT6966
(Dual CPU)

2.53GHz

1.07A

6.48A

4.44A

Intel Xeon C5500
Quad-Core (EC5549)

JXTS6966
(Single CPU)

2.53GHz

0.71A

3.28A

2.10A

Intel Xeon C5500
Dual-Core (EC5539)

JXT6966
(Dual CPU)

2.27GHz

0.90A

6.29A

4.48A

Intel Xeon C5500
Dual-Core (EC5539)

JXTS6966
(Single CPU)

2.27GHz

0.71A

3.02A

2.08A

Intel Xeon C5500
Quad-Core (EC5509)

JXT6966
(Dual CPU)

2.00GHz

0.90A

5.96A

4.91A

Intel Xeon LV C5500
Quad-Core (LC5528)

JXT6966
(Dual CPU)

2.13GHz

1.06A

4.87A

4.91A

Intel Xeon LV C5500
Quad-Core (LC5528)

JXTS6966
(Single CPU)

2.13GHz

0.71A

2.90A

2.06A

100% CPU Stress State:

Intel Xeon C5500
Quad-Core (EC5549)

JXT6966
(Dual CPU)

2.53GHz

1.09A

12.20A

4.48A

Intel Xeon C5500
Quad-Core (EC5549)

JXTS6966
(Single CPU)

2.53GHz

0.72A

7.99A

2.12A

Intel Xeon C5500
Dual-Core (EC5539)

JXT6966
(Dual CPU)

2.27GHz

0.92A

9.78A

4.48A

Intel Xeon C5500
Dual-Core (EC5539)

JXTS6966
(Single CPU)

2.27GHz

0.72A

5.15A

2.09A

Intel Xeon C5500
Quad-Core (EC5509)

JXT6966
(Dual CPU)

2.00GHz

0.90A

10.39A

4.93A

Intel Xeon LV C5500
Quad-Core (LC5528)

JXT6966
(Dual CPU)

2.13GHz

1.06A

10.57A

4.94A

Intel Xeon LV C5500
Quad-Core (LC5528)

JXTS6966
(Single CPU)

2.13GHz

0.72A

6.33A

2.07A

Power Fail Detection

A hardware reset is issued when any of the monitored voltages drops below its specified nominal low
voltage limit. The monitored voltages and their nominal low limits are listed below.

Battery

A built-in lithium battery is provided, for ten years of data retention for CMOS memory.

CAUTION: There is a danger of explosion if the battery is incorrectly replaced. Replace it only with the
same or equivalent type recommended by the manufacturer. Dispose of used batteries according to the
manufacturer's instructions.

Power Requirements

The following are nominal values with 12GB and 6GB of system memory installed*.

Tolerance for all voltages is +/- 5%
*12GB (6, 2GB DDR3 Mini-DIMMs) for a dual-processor JXT6966 and 6GB (3, 2GB DDR3 Mini­DIMMs) for a single-processor JXTS6966

CHASSIS PLANS 1-10