Champion CM6800GIP, CM6800GIS, CM6800XIP, CM6800XIS Schematics

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

μ

GENERAL DESCRIPTION

The CM6800 is a controller for power factor corrected,

switched mode power suppliers. Power Factor Correction

(PFC) allows the use of smaller, lower cost bulk

capacitors, reduces power line loading and stress on the

switching FETs, and results in a power supply that fully

compiles with IEC-1000-3-2 specifications. Intended as a

BiCMOS version of the industry-standard ML4824,

CM6800 includes circuits for the implementation of leading

edge, average current, “boost” type power factor

correction and a trailing edge, pulse width modulator

(PWM). Gate-driver with 1A capabilities minimizes the

need for external driver circuits. Low power requirements

improve efficiency and reduce component costs.

An over-voltage comparator shuts down the PFC section

in the event of a sudden decrease in load. The PFC

section also includes peak current limiting and input

voltage brownout protection. The PWM section can be

operated in current or voltage mode, at up to 250kHz, and

includes an accurate 50% duty cycle limit to prevent

transformer saturation.

CM6800 includes an additional folded-back current limit

for PWM section to provide short circuit protection

function.

FEATURES

 Patent Number #5,565,761, #5,747,977, #5,742,151,

#5,804,950, #5,798,635

 Pin to pin compatible with ML4800 and FAN4800

 Additional folded-back current limit for PWM section.

 23V Bi-CMOS process

 VIN OK turn on PWM at 2.5V instead of 1.5V

 Internally synchronized leading edge PFC and trailing

edge PWM in one IC

 Slew rate enhanced transconductance error amplifier for

ultra-fast PFC response

 Low start-up current (100

A typ.)

 Low operating current (3.0mA type.)

 Low total harmonic distortion, high PF

 Reduces ripple current in the storage capacitor between

the PFC and PWM sections

 Average current, continuous or discontinuous boost

leading edge PFC

 VCC OVP Comparator, Low Power Detect Comparator

 PWM configurable for current mode or voltage mode

operation

 Current fed gain modulator for improved noise immunity

 Brown-out control, over-voltage protection, UVLO, and

soft start, and Reference OK

CM6800

APPLICATIONS

PIN CONFIGURATION

 Desktop PC Power Supply

 Internet Server Power Supply

 IPC Power Supply

 UPS

 Battery Charger

 DC Motor Power Supply

 Monitor Power Supply

 Telecom System Power Supply

 Distributed Power

SOP-16 (S16) / PDIP-16 (P16)

Top View

1

2

3

4

5

6

7

8

IEAO

IAC

ISENSE

VRMS

SS

VDC

RAMP1

RAMP2

PFC OUT

PWM OUT

DC ILIMIT

VEAO

VFB

VREF

VCC

GND

16

15

14

13

12

11

10

9

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 1

CM6800

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

PIN DESCRIPTION

Pin No. Symbol Description

1 IEAO PFC transconductance current error amplifier output 0 4.25 V

2 IAC PFC gain control reference input 0 1 mA

Operating Voltage

Min. Typ. Max. Unit

3 I

4 V

5 SS Connection point for the PWM soft start capacitor 0 8 V

6

7

8 RAMP 2

9 DC I

10 GND Ground

11 PWM OUT PWM driver output 0 VCC V

Current sense input to the PFC current limit comparator -5 0.7 V

SENSE

Input for PFC RMS line voltage compensation 0 6 V

RMS

VDC

RAMP 1

(RTCT)

(PWM RAMP)

LIMIT

PWM voltage feedback input 0 8 V

Oscillator timing node; timing set by RT CT 1.2 3.9 V

When in current mode, this pin functions as the current sense
input; when in voltage mode, it is the PWM input from PFC
output (feed forward ramp).

PWM current limit comparator input 0 1 V

0 6 V

12 PFC OUT PFC driver output 0 VCC V

13 VCC Positive supply 10 15 18 V

14 V

15 VFB PFC transconductance voltage error amplifier input 0 2.5 3 V

16 VEAO

Buffered output for the internal 7.5V reference 7.5 V

REF

PFC transconductance voltage error amplifier output

0 6 V

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 2

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

BLOCK DIAGRAM (CM6800)

16

3.5K

GMi

+

-

IEAO

.

OSCILLATOR

15

2

4

3

7

8

VFB

IAC

VRMS

ISENSE

RAMP1

RAMP2

2.5V

GMv

-

+

VEAO

0.3V

.

GAIN

MODULATOR

350

SW SPST

-

+

LOW POWER
DETECT

3.5K

1

VCC

17.9V

0.5V

PFC CMP

+

-

VCC OVP

+

-

TRI-FAULT

-

+

DUTY CYCLE

2.75V

LIMIT

-1V

PFC OVP

+

.

-

+

-

PFC ILIMIT

PWM
DUTY

SRQ

SRQ

REFERENCE

Q

Q

CM6800

13

VCC

7.5V

CLK

PFCOUT

PWMOUT

VREF

POWER
FACTOR
CORRECTOR

MPPFC

VCC

PFC OUT

MNPFC

GND

14

12

PWM

-

CMP

+

SS CMP

-

+

VDC

6

SS

5

DC ILIMIT

9

Vcc

20uA

VREF

350

1.5V

SW SPST

SW SPST SW SPST

ORDERING INFORMATION

Part Number Temperature Range Package

CM6800GIP

CM6800GIS

CM6800XIP*

CM6800XIS*

*Note:

G : Suffix for Pb Free Product

X : Suffix for Halogen Free Product

VFB

-

2.45V

+

VIN OK

-40℃ to 125℃

-40℃ to 125℃

-40℃ to 125℃

-40℃ to 125℃

VCC

MPPWM

SRQ

.

1.0V

-

+

DC ILIMIT

SRQ

VCC

Q

UVLO

PWM OUT

MNPWM

GND

PULSE
WIDTH
MODULATOR

GND

11

10

16-Pin PDIP (P16)

16-Pin Wide SOP (S16)

16-Pin PDIP (P16)

16-Pin Wide SOP (S16)

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 3

CM6800

μ

μ

μ

μ

μ

μ

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum ratings are those values beyond which the device could be permanently damaged.

Parameter Min. Max. Units

VCC 20 V
IEAO 0 7.5 V
I

Voltage -5 0.7 V

SENSE

PFC OUT

PWMOUT

Voltage on Any Other Pin
I

10 mA

REF

IAC Input Current 1 mA
Peak PFC OUT Current, Source or Sink 1 A
Peak PWM OUT Current, Source or Sink 1 A

PFC OUT, PWM OUT Energy Per Cycle 1.5

Junction Temperature 150

Storage Temperature Range -65 150

Operating Temperature Range -40 125

Lead Temperature (Soldering, 10 sec) 260

Thermal Resistance (θJA)
Plastic DIP
Plastic SOIC

Power Dissipation (PD) TA<50℃

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=+15V, R

= 30.16kΩ, C

Symbol Parameter Test Conditions

Input Voltage Range 0 6 V

Transconductance

Feedback Reference Voltage 2.45 2.5 2.55 V

Input Bias Current Note 2 -1.0 -0.05

Output High Voltage 5.8 6.0 V

Output Low Voltage 0.1 0.4 V

Sink Current VFB = 3V, VEAO = 6V -35 -20

Source Current VFB = 1.5V, VEAO = 1.5V 30 40

Open Loop Gain 50 60 dB

Power Supply Rejection Ratio 11V < VCC < 16.5V 50 60 dB

Input Voltage Range -1.5 0.7 V

Transconductance

Output High Voltage 4.0 4.25 V

Output Low Voltage 1.0 1.2 V

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 4

=1000pF, TA=Operating Temperature Range (Note 1)

T

Voltage Error Amplifier (gmv)

V

= V

NONINV

Current Error Amplifier (gmi)

V

NONINV

Input Offset Voltage -25 25 mV

INV

at room temp

= V

INV

at room temp

GND – 0.3 VCC + 0.3 V
GND – 0.3 VCC + 0.3 V

GND – 0.3 VCC + 0.3 V

800 mW

, VEAO = 3.75V

, VEAO = 3.75V

80

105

CM6800

Min. Typ. Max.

50 70 90

50 85 100

J

℃

℃

℃

℃

℃/W

℃/W

Unit

mho

A

A

A

mho

T

CM6800

μ

μ

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply

Vcc=+15V, RT = 30.16kΩ, CT =1000pF, TA=Operating Temperature Range (Note 1)

Symbol Parameter Test Conditions

Sink Current I

Source Current I

= +0.5V, IEAO = 4.0V -65 -35

SENSE

= -0.5V, IEAO = 1.5V 35 75

SENSE

Min. Typ. Max.

Open Loop Gain 60 70 dB

Power Supply Rejection Ratio 11V < VCC < 16.5V 60 75 dB

PFC OVP Comparator

Threshold Voltage 2.70 2.77 2.85 V

Hysteresis 230 290 mV

Low Power Detect Comparator

Threshold Voltage 0.2 0.3 0.4 V

VCC OVP Comparator

Threshold Voltage 17.5 17.9 18.5 V

Hysteresis 1.40 1.5 1.65 V

Tri-Fault Detect

Fault Detect HIGH 2.65 2.75 2.85 V

Time to Fault Detect HIGH VFB=V

FAULT DETECT LOW

V

=OPEN.470pF from VFB to GND

FB

to

2 4 ms

Fault Detect LOW 0.4 0.5 0.6 V

PFC I

Comparator

LIMIT

Threshold Voltage -1.10 -1.00 -0.90 V

(PFC I

LIMIT VTH

Output)

– Gain Modulator

20 100 mV

Delay to Output (Note 4) Overdrive Voltage = -100mV 250 ns

DC I

Comparator

LIMIT

Threshold Voltage 0.95 1.0 1.05 V

Delay to Output (Note 4) Overdrive Voltage = 100mV 250 ns

VIN OK Comparator

OK Threshold Voltage 2.35 2.45 2.55 V

Hysteresis 0.95 1.2 1.4 V

GAIN Modulator

Gain (Note 3)

Bandwidth

Output Voltage =

3.5K*(I

SENSE-IOFFSET

= 100μA, V

I

AC

at room temp

= 100μA, V

I

AC

at room temp

= 150μA, V

I

AC

at room temp

= 300μA, V

I

AC

at room temp
I

AC

I

= 250μA, V

AC

)

=0, VFB = 1V

RMS

= 1.1V, VFB = 1V

RMS

= 1.8V, VFB = 1V

RMS

= 3.3V, VFB = 1V

RMS

= 100μA

= 1.1V, VFB = 1V

RMS

0.70 0.84 0.95

1.80 2.00 2.20

0.90 1.00 1.10

0.25 0.32 0.40

0.84 0.90 0.95 V

CM6800

10 MHz

Unit

A

A

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 5

CM6800

μ

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply

Vcc=+15V, RT = 30.16kΩ, CT =1000pF, TA=Operating Temperature Range (Note 1)

Symbol Parameter Test Conditions

Min. Typ. Max.

Oscillator

Initial Accuracy

A

60 70 kHz

= 25℃

T

Voltage Stability 11V < VCC < 16.5V 1 %

Temperature Stability 2 %

Total Variation Line, Temp 52 74 kHz

Ramp Valley to Peak Voltage 2.5 V

PFC Dead Time (Note 4) 360 640 ns

CT Discharge Current V

RAMP2

= 0V, V

= 2.5V 6.5 15 mA

RAMP1

Reference

Output Voltage

= 25℃, I(V

T

A

) = 1mA

REF

7.4 7.5 7.6 V

Line Regulation 11V < VCC < 16.5V 10 25 mV

Load Regulation

0mA < I(V

0mA < I(V

) < 7mA; TA = 0℃~70℃

REF

) < 5mA; TA = -40℃~85℃

REF

Temperature Stability 0.4 %

Total Variation Line, Load, Temp 7.35 7.65 V

= 125℃, 1000HRs

T

Long Term Stability

J

PFC

Minimum Duty Cycle V

Maximum Duty Cycle V

I

Output Low Rdson

I

I

Output High Rdson

I

OUT

= -20mA at room temp 15 ohm

OUT

= -100mA at room temp 15 ohm

OUT

= 10mA, VCC = 9V at room temp 0.4 0.8 V

= 20mA at room temp 15 20 ohm

OUT

I

= 100mA at room temp 15 20 ohm

OUT

> 4.0V 0 %

IEAO

< 1.2V 92 95 %

IEAO

Rise/Fall Time (Note 4) CL = 1000pF 50 ns

PWM

Duty Cycle Range 0-43 0-47 0-49 %

I

Output Low Rdson

I

I

Output High Rdson

= -20mA at room temp 15 ohm

OUT

= -100mA at room temp 15 ohm

OUT

I

= 10mA, VCC = 9V 0.4 0.8 V

OUT

= 20mA at room temp 15 20 ohm

OUT

I

= 100mA at room temp 15 20 ohm

OUT

Rise/Fall Time (Note 4) CL = 1000pF 50 ns

PWM Comparator Level Shift 1.4 1.55 1.7 V

Supply

Start-Up Current VCC = 12V, CL = 0 at room temp 100 150

Operating Current 14V, CL = 0 3.0 7.0 mA

Undervoltage Lockout Threshold CM6800 12.74 13 13.26 V

Undervoltage Lockout Hysteresis CM6800 2.85 3.0 3.15 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Includes all bias currents to other circuits connected to the V

Note 3: Gain = K x 5.375V; K = (I

SENSE

– I

) x [IAC (VEAO – 0.625)]-1; VEAO

OFFSET

FB

pin.

MAX

= 6V

Note 4: Guaranteed by design, not 100% production test.

CM6800

Unit

10 20 mV

10 20 mV

5 25 mV

A

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 6

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

TYPICAL PERFORMANCE CHARACTERISTIC

CM6800

127

120

113

106

99

92

85

78

71

Transconductance (umho)

64

57

2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3

VFB (V)

Voltage Error Amplifier (gmv) Transconductance

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

Variable Gain Block Constant (K)

0

00.511.522.533.544.55

VRMS (V)

Gain Modulator Transfer Characteristic (K)

OFFSETGAINMOD

K−=

AC

II

0.625)-(6 x I

1-

mV

100

90

80

70

60

50

40

30

20

Transconductance (umho)

10

0

-500 0 500

ISENSE(mV)

Current Error Amplifier (g

2.2

2

1.8

1.6

1.4

1.2

Gain

1

0.8

0.6

0.4

0.2

0

00.511.522.533.544.55

) Transconductance

mi

VRMS (V)

Gain

II

Gain−=

OFFSETSENSE

AC

I

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 7

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

Functional Description

The CM6800 consists of an average current controlled,
continuous boost Power Factor Correction (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM’s line regulation. In
either mode, the PWM stage uses conventional trailing
edge duty cycle modulation, while the PFC uses leading
edge modulation. This patented leading/trailing edge
modulation technique results in a higher usable PFC error
amplifier bandwidth, and can significantly reduce the size of
the PFC DC buss capacitor.

The synchronized of the PWM with the PFC simplifies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor). The PWM
section of the CM6800 runs at the same frequency as the
PFC.

In addition to power factor correction, a number of
protection features have been built into the CM6800. These
include soft-start, PFC overvoltage protection, peak current
limiting, brownout protection, duty cycle limiting, and
under-voltage lockout.

Power Factor Correction

Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to the
line voltage, so the power factor is unity (one). A common
class of nonlinear load is the input of most power supplies,
which use a bridge rectifier and capacitive input filter fed
from the line. The peak-charging effect, which occurs on
the input filter capacitor in these supplies, causes brief
high-amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line
voltage. Such supplies present a power factor to the line of
less than one (i.e. they cause significant current harmonics
of the power line frequency to appear at their input). If the
input current drawn by such a supply (or any other
nonlinear load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous
line voltage. The PFC section of the CM6800 uses a
boost-mode DC-DC converter to accomplish this. The input
to the converter is the full wave rectified AC line voltage. No
bulk filtering is applied following the bridge rectifier, so the
input voltage to the boost converter ranges (at twice line
frequency) from zero volts to the peak value of the AC input
and back to zero. By forcing the boost converter to meet
two simultaneous conditions, it is possible to ensure that
the current drawn from the power line is proportional to the
input

CM6800

line voltage. One of these conditions is that the output
voltage of the boost converter must be set higher than the
peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VAC
condition is that the current drawn from the line at any given
instant must be proportional to the line voltage. Establishing
a suitable voltage control loop for the converter, which in turn
drives a current error amplifier and switching output driver
satisfies the first of these requirements. The second
requirement is met by using the rectified AC line voltage to
modulate the output of the voltage control loop. Such
modulation causes the current error amplifier to command a
power stage current that varies directly with the input voltage.
In order to prevent ripple, which will necessarily appear at the
output of boost circuit (typically about 10VP-P ripple at low
frequency on a 385V DC level), from introducing distortion
back through the voltage error amplifier, the bandwidth of the
voltage loop is deliberately kept low. A final refinement is to
adjust the overall gain of the PFC such to be proportional to
1/VIN^2, which linearizes the transfer function of the system
as the AC input to voltage varies.

Since the boost converter topology in the CM6800 PFC is of
the current-averaging type, no slope compensation is
required.

. The other

rms

PFC Section

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
CM6800. The gain modulator is the heart of the PFC, as it is
this circuit block which controls the response of the current
loop to line voltage waveform and frequency, rms line
voltage, and PFC output voltages. There are three inputs to
the gain modulator. These are:

1. A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current via a

RMS

AC

and

.

resistor and is then fed into the gain modulator at I
Sampling current in this way minimizes ground noise, as is
required in high power switching power conversion
environments. The gain modulator responds linearly to this
current.

2. A voltage proportional to the long-term RMS AC line
voltage, derived from the rectified line voltage after scaling
and filtering. This signal is presented to the gain modulator
at VRMS. The gain modulator’s output is inversely
proportional to V
V

where special gain contouring takes over, to limit

RMS

power dissipation of the circuit components under heavy
brownout conditions). The relationship between V
gain is called K, and is illustrated in the Typical
Performance Characteristics.

3. The output of the voltage error amplifier, VEAO. The gain
modulator responds linearly to variations in this voltage.

2

(except at unusually low values of

RMS

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 8

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way the
gain modulator forms the reference for the current error
loop, and ultimately controls the instantaneous current draw
of the PFC form the power line. The general for of the
output of the gain modulator is:

VEAOI ×

AC

GAINMOD

=

V

RMS

I

More exactly, the output current of the gain modulator is
given by:

I

= K x (VEAO – 0.625V) x IAC

GAINMOD

Where K is in units of V

Note that the output current of the gain modulator is limited

μ

around 228.47

A and the maximum output voltage of the

gain modulator is limited to 228.47uA x 3.5K=0.8V. This

0.8V also will determine the maximum input power.

However, I
I

= I

SENSE

GAINMOD-IOFFSET

cannot be measured directly from I

GAINMOD

when VEAO is less than 0.5V and I

is around 60uA.

I

OFFSET

Selecting R

for IAC pin

AC

IAC pin is the input of the gain modulator. IAC also is a
current mirror input and it requires current input. By
selecting a proper resistor R
wave current derived from the line voltage and it also helps
program the maximum input power and minimum input line
voltage.

=Vin peak x 7.9K. For example, if the minimum line

R

AC

voltage is 80VAC, the R

Current Error Amplifier, IEAO

The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the inverting
input to the current error amplifier, the output current of the
gain modulator is summed with a current which results from
a negative voltage being impressed upon the I
The negative voltage on I
currents flowing in the PFC circuit, and is typically derived
from a current sense resistor in series with the negative
terminal of the input bridge rectifier.

x 1V (1)

2

-1

and I

=80 x 1.414 x 7.9K=894Kohm.

AC

SENSE

can only be measured

OFFSET

GAINMOD

, it will provide a good sine

AC

is 0A. Typical

SENSE

represents the sum of all

SENSE

pin.

.

CM6800

In higher power applications, two current transformers are
sometimes used, one to monitor the IF of the boost diode. As
stated above, the inverting input of the current error amplifier
is a virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC, an
increase in positive current from the gain modulator will
cause the output stage to increase its duty cycle until the
voltage on I

is adequately negative to cancel this

SENSE

increased current. Similarly, if the gain modulator’s output
decreases, the output duty cycle will decrease, to achieve a
less negative voltage on the I

SENSE

pin.

Cycle-By-Cycle Current Limiter and Selecting RS

The I

pin, as well as being a part of the current feedback

SENSE

loop, is a direct input to the cycle-by-cycle current limiter for
the PFC section. Should the input voltage at this pin ever be
more negative than –1V, the output of the PFC will be
disabled until the protection flip-flop is reset by the clock
pulse at the start of the next PFC power cycle.

is the sensing resistor of the PFC boost converter. During

R

S

the steady state, line input current x RS = I

GAINMOD

x 3.5K.
Since the maximum output voltage of the gain modulator is
I

max x 3.5K= 0.8V during the steady state, RSx line

GAINMOD

input current will be limited below 0.8V as well. Therefore, to
choose RS, we use the following equation:

=0.8V x Vinpeak/(2x Line Input power)

R

S

For example, if the minimum input voltage is 80VAC, and the
maximum input rms power is 200Watt, R

= (0.8V x 80V x

S

1.414)/(2 x 200) = 0.226 ohm.

PFC OVP

In the CM6800, PFC OVP comparator serves to protect the
power circuit from being subjected to excessive voltages if
the load should suddenly change. A resistor divider from the
high voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.75V, the PFC output driver is shut
down. The PWM section will continue to operate. The OVP
comparator has 250mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below 2.50V. The VFB
power components and the CM6800 are within their safe
operating voltages, but not so low as to interfere with the
boost voltage regulation loop. Also, VCC OVP can be served
as a redundant PFCOVP protection. VCC OVP threshold is

17.9V with 1.5V hysteresis.

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 9

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

ΔΔΔΔΔ

ΔΔΔΔΔ

GMi

1

IEAO

.

OSCILLATOR

VCC

17.9V

0.5V

PFC CMP

+

-

VCC OVP

+

-

TRI-FAULT

-

+

16

VEAO

-

0.3V

VFB

18

IAC

2

VRMS

4

ISENSE

3

RAMP1

7

2.5V

-

+

GMv

.

GAIN

MODULATOR

+

LOW POWER
DETECT

3.5K

3.5K

+

-

Figure 1. PFC Section Block Diagram

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the types
of compensation networks most commonly used for the
voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V

to produce a soft-start characteristic on the

REF

PFC: as the reference voltage comes up from zero volts, it
creates a differentiated voltage on I

which prevents the

EAO

PFC from immediately demanding a full duty cycle on its
boost converter.

PFC Voltage Loop

There are two major concerns when compensating the
voltage loop error amplifier, V

; stability and transient

EAO

response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest anticipated
international power frequency). The gain vs. input voltage
of the CM6800’s voltage error amplifier, V

has a

EAO

specially shaped non-linearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbation in line or
load conditions will cause the input to the voltage error
amplifier (V

) to deviate from its 2.5V (nominal) value. If

FB

this happens, the transconductance of the voltage error
amplifier will increase significantly, as shown in the Typical
Performance Characteristics. This raises the
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristics.

CM6800

PFC OVP

+

-

+

-

PFC ILIMIT

.

SRQ

SRQ

2.75V

-1V

The Voltage Loop Gain (S)

FB

EAO

V

EAO

*

Δ

FB

V

V5.2*P

DCEAO

C*S*V*V

compensation is similar to that of

EAO

EAO

I

OFF

EAO

**

SENSE

I

Δ

CII

ZGM

**

V

OUT

=

EAO

V

≈

OUTDC

V

*

OUT

V

IN

2

Δ

: Compensation Net Work for the Voltage Loop

Z

CV

GMv: Transconductance of VEAO
PIN: Average PFC Input Power

: PFC Boost Output Voltage; typical designed value is

V

OUTDC

380V.
CDC: PFC Boost Output Capacitor

PFC Current Loop

The current amplifier, I
the voltage error amplifier, V
of crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage loop.
It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.

The Current Loop Gain (S)

V

ISENSE

=

OFF

D

≈

D

I

SOUTDC

RV

*

VLS

5.2**

13

VCC

7.5V

REFERENCE

Q

Q

CLK

POWER
FACTOR
CORRECTOR

MPPFC

MNPFC

CVV

Z*GM*

with exception of the choice

VREF

VCC

PFC OUT

GND

14

12

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 10

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

ZCI: Compensation Net Work for the Current Loop

: Transconductance of IEAO

GM

I

V

: PFC Boost Output Voltage; typical designed value

OUTDC

is 380V and we use the worst condition to calculate the Z
RS: The Sensing Resistor of the Boost Converter

2.5V: The Amplitude of the PFC Leading Modulation Ramp
L: The Boost Inductor

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

CI

CM6800

Filter, the RC filter between RS and I

I

SENSE

There are 2 purposes to add a filter at I

SENSE

1.) Protection: During start up or inrush current
conditions, it will have a large voltage cross Rs
which is the sensing resistor of the PFC boost
converter. It requires the I

SENSE

the energy.

2.) To reduce L, the Boost Inductor: The I
also can reduce the Boost Inductor value since the

Filter behaves like an integrator before going

I

SENSE

I

which is the input of the current error

SENSE

amplifier, IEAO.

The I

Filter is a RC filter. The resistor value of the I

SENSE

Filter is between 100 ohm and 50 ohm because I
resistor can generate an offset voltage of IEAO. By selecting
R

equal to 50 ohm will keep the offset of the IEAO less

FILTER

than 5mV. Usually, we design the pole of I
fpfc/6, one sixth of the PFC switching frequency. Therefore,
the boost inductor can be reduced 6 times without disturbing
the stability. Therefore, the capacitor of the I

, will be around 283nF.

C

FILTER

:

SENSE

pin:

Filter to attenuate

Filter

SENSE

SENSE

x the

OFFSET

Filter at

SENSE

Filter,

SENSE

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

Figure 3. External Component Connections to V

CC

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 11

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

μ

μ

Oscillator (RAMP1)

The oscillator frequency is determined by the values of R
and CT, which determine the ramp and off-time of the
oscillator output clock:

f

OSC

=

1

DEADTIMERAMP tt

+

The dead time of the oscillator is derived from the following
equation:

REF

1.25V

t

= CT x R

RAMP

at V

= 7.5V:

REF

t

= CT x RT x 0.51

RAMP

x In

T

REF

−

3.75V

−

The dead time of the oscillator may be determined using:

t

DEADTIME

=

2.5V

2.65mA

x CT = 943 x CT

The dead time is so small (t

RAMP

>> t

DEADTIME

) that the

operating frequency can typically be approximately by:

=

1

RAMPt

f

OSC

EXAMPLE:
For the application circuit shown in the datasheet, with the
oscillator running at:

f

= 67.5kHz =

OSC

1

RAMPt

Solving for C
components values, C

x RT yields 2.9 x 10-5. Selecting standard

T

= 470pF, and RT = 61.9kΩ

T

The dead time of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator dead time, the Maximum PWM Duty Cycle is
typically 45%. In many applications, care should be taken

not be made so large as to extend the Maximum

that C

T

Duty Cycle beyond 50%. This can be accomplished by
using a stable 390pF capacitor for CT.

T

PWM Section

Pulse Width Modulator

The PWM section of the CM6800 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or
voltage-mode operation. In current-mode applications, the
PWM ramp (RAMP2) is usually derived directly from a
current sensing resistor or current transformer in the
primary of the output stage, and is thereby representative

CM6800

of the current flowing in the converter’s output stage.
DCI

, which provides cycle-by-cycle current limiting, is

LIMIT

typically connected to RAMP2 in such applications. For
voltage-mode, operation or certain specialized applications,
RAMP2 can be connected to a separate RC timing network
to generate a voltage ramp against which V

DC

will be
compared. Under these conditions, the use of voltage
feedforward from the PFC buss can assist in line regulation
accuracy and response. As in current mode operation, the
DC I

input is used for output stage overcurrent protection.

LIMIT

No voltage error amplifier is included in the PWM stage of
the CM6800, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate the
design of optocoupler feedback circuitry, an offset has been
built into the PWM’s RAMP2 input which allows V

DC

to

command a zero percent duty cycle for input voltages below

1.25V.

PWM Current Limit

The DC I

pin is a direct input to the cycle-by-cycle current

LIMIT

limiter for the PWM section. Should the input voltage at this
pin ever exceed 1V, the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle. Beside, the
cycle-by-cycle current, when the DC ILIMIT triggered the
cycle-by-cycle current, it also softly discharge the voltage of
soft start capacitor. It will limit PWM duty cycle mode.
Therefore, the power dissipation will be reduced during the
dead short condition.

OK Comparator

V

IN

The V

OK comparator monitors the DC output of the PFC

IN

and inhibits the PWM if this voltage on VFB is less than its
nominal 2.45V. Once this voltage reaches 2.45V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start begins.

PWM Control (RAMP2)

When the PWM section is used in current mode, RAMP2 is
generally used as the sampling point for a voltage
representing the current on the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer. In voltage mode, it is the input for a
ramp voltage generated by a second set of timing
components (R

RAMP2

, C

),that will have a minimum value

RAMP2

of zero volts and should have a peak value of approximately
5V. In voltage mode operation, feedforward from the PFC
output buss is an excellent way to derive the timing ramp for
the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 20

A supplies

the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation:

= t

C

SS

DELAY

x

A20

1.25V

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 12

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

μ

+

−

+

−

μ

μ

where CSS is the required soft start capacitance, and the

is the desired start-up delay.

t

DEALY

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

Solving for the minimum value of C

= 5ms x

C

SS

A20

= 80nF

1.25V

Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the
SS capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the VIN OK comparator at
start-up. The magnitude of VFB at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a

μ F soft start capacitor will allow time for V

1.0

out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.

Generating V

After turning on CM6800 at 13V, the operating voltage can
vary from 10V to 17.9V. The threshold voltage of VCC OVP
comparator is 17.9V. The hysteresis of VCC OVP is 1.5V.
When VCC see 17.9V, PFCOUT will be low, and PWM
section will not be disturbed. That’s the two ways to
generate VCC. One way is to use auxiliary power supply
around 15V, and the other way is to use bootstrap winding
to self-bias CM6800 system. The bootstrap winding can be
either taped from PFC boost choke or from the transformer
of the DC to DC stage.

CC

SS

:

and PFC

FB

CM6800

The ratio of winding transformer for the bootstrap should be
set between 18V and 15V. A filter network is recommended
between VCC (pin 13) and bootstrap winding. The resistor of
the filter can be set as following.

x I

R

FILTER

VCC

~ 2V, I

= IOP + (Q

VCC

PFCFET

+ Q

PWMFET

) x fsw

IOP = 3mA (typ.)

If anything goes wrong, and VCC goes beyond 17.9V, the
PFC gate (pin 12) drive goes low and the PWM gate drive
(pin 11) remains function. The resistor’s value must be
chosen to meet the operating current requirement of the
CM6800 itself (5mA, max.) plus the current required by the
two gate driver outputs.

EXAMPLE:
With a wanting voltage called, V

,of 18V, a VCC of 15V

BIAS

and the CM6800 driving a total gate charge of 90nC at
100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET),
the gate driver current required is:

I

GATEDRIVE

= 100kHz x 90nC = 9mA

CCBIAS

=

R

BIAS

VV

GCC

II

BIAS

15V18V
9mA 5mA

= 214Ω

F

F and 220 μ F is also required

R

=

BIAS

Choose R

The CM6800 should be locally bypassed with a 1.0

ceramic capacitor. In most applications, an electrolytic
capacitor of between 47

across the part, both for filtering and as part of the start-up
bootstrap circuitry.

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 13

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

Leading/Trailing Modulation

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn
on right after the trailing edge of the system clock. The error
amplifier output is then compared with the modulating ramp
up. The effective duty cycle of the trailing edge modulation
is determined during the ON time of the switch. Figure 4
shows a typical trailing edge control scheme.

In case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When
the modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during OFF time of the switch. Figure 5 shows a leading
edge control scheme.

CM6800

One of the advantages of this control technique is that it
required only one system clock. Switch 1(SW1) turns off and
switch 2 (SW2) turns on at the same instant to minimize the
momentary “no-load” period, thus lowering ripple voltage
generated by the switching action. With such synchronized
switching, the ripple voltage of the first stage is reduced.
Calculation and evaluation have shown that the 120Hz
component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 14

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

APPLICATION CIRCUIT (Voltage Mode)

R5 R3

IVIN_EMC

VIN

AC

EMC FILTER

L2 IL1L3

R2

IVIN

RT1

R1

C8C3

D6

1N4002

PFC_VIN

D4

IAC

IBOOT

C2

R18

D7

1N4002

R59

C46

R12

R10

R15

R13

R11

C30

R64

R60

R66

C44

C45

VRMS

C47

VREF

R56

C48

ISENSE

R57

C49

VCC

VDC

SS

R62

C50

C33R14

100n

Q1
Q2N2222

Q2
Q2N904

C41

R58

IEAO

U2 CM6800/01/24

1

IEAO

2

IAC

3

I-SENSE

4

VRMS

5

SS

PFC-OUT

6

VDC

PWM-OUT

7

RAMP1

8 9

RAMP2 ILIMIT

ILIMIT

L1

C43

VEAO

VFB

VREF

VCC

GND

CM6800

D5

D5PFC_VIN PFC_VoutIVIN

D12

R22

PFC_DC

22

1N4148

R23

R24

75

22

R25
10k

VCC

PWM_OUT

C51

ILIMIT

VREF

VEAO

C52

1u 100n

ZD2

16

15

14

13

12

11

10

R61

470

Q4Q3

D10
R26
18k

C23

470p

VFB

VREF

C54

VCC

C53

MUR1100

R63

C56

C55A

C57

R16A

R17A

R65A

PFC_Vout

IC10

C10

VCC

PWM_OUT

PFC_Vout

C34

100n

Q6
Q2N2222

PWM_DC

Q7
Q2N904

R44

C4

ISO1

T1

T 2:3

C14

R34

10n

4.7

D9A

IBIAS

D9B

D16

1N4148

R32A

IL4

L4

R35

4.7

C22

10n

C31

L5

IC18

IC17

C18

C17 PWM_Rload

R32

R33

VCC

PWM_Vout

C19

500m

ILOAD

R45

R48

C38

R49

R46

C39

C40

U1

CM431

R43

PWM_IN

C7

10n

R28

22

C22

R27

10n

100k

D13

MUR1100

Q3
R29
10k

R31

D8

MUR1100

C15

10n

ILIMIT

ZD1

6.8V

VDC

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 15

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

APPLICATION CIRCUIT (Current Mode)

R5 R3

IVIN_EMC

VIN

AC

EMC FILTER

L2 IL1L3

R2 R1

IVIN

RT1

C8C3

D6

1N4002

PFC_VIN

D4

IVIN

C2

R10

R18

D7

1N4002

R11

R64

R59

R60

C46

C44

PFC_VIN

IAC

IBOOT

R12

R15

R13

C30

VRMS

C47

VREF

R66

C45

R56

R67

C48

ISENSE

CM6800

L1

Q1
Q2N2222

Q2
Q2N904

C43

VEAO

VFB

VREF

VCC

GND

R61 470

R68

16

15

14

13

12

11

10

D12

1N4148

R23

75

VCC

PWM_OUT

C51

PFC_DC

R25
10k

VREF

ILIMIT

R22

22

R24

22

VEAO

C52

1u 100n

ZD2

VCC

C53

C33R14

100n

C41

R58

IEAO

U2 CM6800/01/24

1

IEAO

2

IAC

3

I-SENSE

4

VRMS

SS

5

SS

PFC-OUT

VDC

6

VDC

PWM-OUT

7

RAMP1

8 9

R57

C49

ILIMIT

R62

C50

RAMP2 ILIMIT

ILIMIT

D5

Q4Q3

D10

R26

MUR1100

18k

C23

470p

VFB

VREF

C54

C55A

R63

C57

C56

PFC_Vout

D5

R16A

R17A

R65A

PFC_Vout

IC10

C10

VCC

PWM_OUT

PFC_Vout

C34

100n

Q6
Q2N2222

PWM_DC

Q7
Q2N904

R44

C4

ISO1

T1

T 2:3

C14

R34

10n

4.7

D9A

IBIAS

D9B

D16

1N4148

R32A

IL4

L4

R35

4.7

C22

10n

C31

L5

IC18

IC17

C18

C17 PWM_Rload

R32

R33

VCC

PWM_Vout

C19

500m

ILOAD

R45

R48

C38

R49

R46

C39

C40

U1

CM431

R43

PWM_IN

C7

10n

R28

22

C22

R27

10n

100k

D13

MUR1100

Q3
R29
10k

R31

D8

MUR1100

C15

10n

ILIMIT

ZD1

6.8V

VDC

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 16

PACKAGE DIMENSION

PIN 1 ID

CM6800

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

16-PIN PDIP (P16)

θ

θ

16-PIN SOP (S16), 0.300” Wide Body

PIN 1 ID

θ

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 17

CM6800

LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO

IMPORTANT NOTICE

Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to

discontinue any integrated circuit product or service without notice, and advises its customers to obtain
the latest version of relevant information to verify, before placing orders, that the information being relied

on is current.

A few applications using integrated circuit products may involve potential risks of death, personal injury, or

severe property or environmental damage. CMC integrated circuit products are not designed, intended,

authorized, or warranted to be suitable for use in life-support applications, devices or systems or other
critical applications. Use of CMC products in such applications is understood to be fully at the risk of the

customer. In order to minimize risks associated with the customer’s applications, the customer should

provide adequate design and operating safeguards.

HsinChu Headquarter Sales & Marketing

5F, No. 11, Park Avenue II,
Science-Based Industrial Park,
HsinChu City, Taiwan

7F-6, No.32, Sec. 1, Chenggong Rd.,
Nangang District, Taipei City 115, Taiwan

T E L : [phone] T E L : [phone]
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http://www.champion-micro.com

2008/10/23 Rev. 2.1 Champion Microelectronic Corporation Page 18