Chaintech 325S, 333S, 333SC, 340SC User Manual

325S/333S/333SC/340SC

U

S

E

R

'

S

HANDBOOK

325S/333S/333SC/340SC

V04

1991

TRADEMARKS:

PC, XT,

tion.

Microsoft,

trademarks

UNIX

is

AutoCad

Wordstar

ternational

WordPerfect

ration.

Lotus

1-2-3

opment

dB

Tate.

Weitek

Intel

80386,80387

ASE

is

a

Corporation.

AT,

PEII

MS-DOS,

of

Microsoft

a

trademark

is

a

registered

is

a

registered

Corporation.

is

a

is

a

registered

III

Plus

is

is

a

trademark

trademark

are

SEP.

are

trademarks

OS/2,

Corporation.

of

Bell

trademark

trademark

trademark

a

registered

of

of

Intel.

trademarks

XENIX,

Laboratories.

of

WordPerfect

trademark

trademark

Weitek

Co.

of

Intel

Co.

of

IBM

Windows

of

Autodesk

of

MicroPro

of

Lotus

Co.

Corpora

of

Inc.

Corpo

Devel

Ashton

are

In











PREFACE

We,

the

manufacturers,

you

on,

what

we

think

purchase

No

340SC

not

none.

We

mation

However,

tion,

to

matter

only

hope

assist

the

will

value

that

that

please

you.

325S/333S/333SC/34OSC

what

walk

perform

for

money

this

manual

you

will

should

you

contact

was

of

life,

beyond

need

require

your

would

a

very

the

the

but

performance

will

to

operate

dealer

like

to

congratulate

wise

decision

main

325S/333S/333SC/

call

of

duty

giving

second

provide

any

who

your

further

will

all

be

the

PC/AT.

informa

pleased

board

infor

you

to

.

to





TABLE

OF

CONTENTS

CHAPTER

CHAPTER

1

INTRODUCTION

1-1

Specifications

1-

2

Features

1-

3

Board

1-

4

Jumper

............................................................................................

2

CONFIGURATION

2-

1

Microprocessor

2-2

Math

2-3

Main

2-4

Cache

2-5

The

2-6

Shadow

2-7

DMA

2-8

Interrupt

2-9

Timers

2-10

Real-Time

2-11

Keyboard

2-12

1/0

2-13

1/0

2-

14

1/0

...........................................................

......................................................................

Layout

for

325S/333S/333SC/340SC..4

Setting

for

325S/333S/333SC/340SC..

........................................................

Coprocessor

Memory

Memory

SIS

85C310/85C320/85C330

RAM

Controller

Controller

........................................................................

Clock

Controller

Port

Address

Channel

Channel

...............................................

.........................................................

.....................................................

&

Memory

...................................................

and

MAP

Pin

Assignments

Signal

Remapping

..............................................

Nonvolatile

...........................................

......................................

Description

Chip

Set

........

RAM

....

.........................

......................

1

3

5

9

10

10

11

12
12

14
14

15

16

17

18

20

21

CHAPTER

3

INSTALLATION

3-

1

3-2

3-3

Static

Precautions

Peripherals

Building

Required

Up a

.................................................

.....................................................

System

...........................................

27

28

28

CHAPTER

4

POWER-ON

4-

1

Error

4-2

Error

4-

3

Error

SELF

Message

Message

Message

From

From

From

TEST

Speaker

Speaker

Display

or

Display,.

........................

.........................

31

32

33

CHAPTER

5

AMI

BIOS SETUP

5-

1

5-2

STAND

ADVANCED

ARD

CMOS

CMOS

Setup

........................................

Setup

.....................................

36

38

V

1

INTRODUCTION

SPECIFICA

TIONS

325S/333S/333SC/34OSC

compatible

speed

of

processing

bility

with

is

designed

Baby

AT,

try-standard

sion

board

can

design

system

with

components.

The

following

cise

information

1-1

properly

board.

CPU

use



CPU

CLOCK

is

system

the

to be

or

sockets,

a

board

that

while

maintaining

IBM*

PC/AT*.

mounted

PC/AT-type

power

supply

new

system

no

modifications

sections

for

the

325S/333S/333SC/340SC

:

Intel80386DX-25

AMD

in

enclosure

inputs,

and

so

forth.

or

will

the

end

or

Intel80386DX-33

S/333SC

AMD8O386DX-4O

:

Programmable

has

options

by

4

(BIOS

a

high-performance

provides

a

standard

In

upgrade

to

existing

provide

user

divided

setup)

full

The

system

PC

and

uses

connectors,

other

words,

your

or

a

quick

to

understand

for325S

for

340SC

CPU

clock

by

2,

AT-

incredible

compati

board

/

XT*,

indus

expan

you

existing

available

and

pre

and

mother

for

333

which

by

3,

and










CHAPTER

1

INTRODUCTION

/

1

COPROCESSORS:

MEMORY

CACHE

SIZE

BIOS

I/O

SLOTS

JUMPER

LANDMARK

LANDMARK

POWER

NORTON

SHADOW

ON

BOARD

SPEED

SPEED

METER(VI.

SI

(V

4.0):

RAM

Socket

80387DX

Up

to

paging

Up

to

paging

128

byte

or

64K

AMI

figuration)

16-bitx6,8-bit

:

.

H/W

.

Power

.

Speaker

.

External

.Turbo

.

H/W

.

Mono/color

(V0.99):

43.5MH(325S),

(333S),

(VI

.

65.4MHz

2):

4.047MIPS

5.368

7.842MIPS

9.483

30.5

(325S),

40.3

(333SC),

:

System

adapter

for

16MB

mode

8MB

mode

for

byte

(single

reset

LED

LED

speed

58.7MHz

14):

MIPS

MIPS

BIOS

BIOS

Weitek

on

for

on

for

325S

for

333SC/340SC

64K

(J

14)

&

(J

13)

battery

(J

selector

selector

(340SC)

(325S),

(333S)

(333SC)

(34OSC)

39.7

48.5

,

3167

or

boar

with

333SC/34OSC.

board

with

325S

or

333S

/333S

,

128byte

EPROM

x 2

keylock(J

(JI)

11)

(J

12)

(J3)

58.7MHz

(333SC),

(333S)

(340SC)

video

BIOS,

Intel

con

10)

fast

fast

and



2

/

325S/333S/333SC/34OSC

SHADOW

SIZE

CACHE:

System

and

:

33cm

adapter

x

2

BIOS,

1.7cm

BIOS

video

BIOS,

1-2

FEATURES

.

100%

IBM*

.

Supports

.

Programmable

EMS

change

.

Programmable

and

optional

.

Flexible

ent

.

Add

BIOS

.

Rechargeable

line

wait

setting

cache

size

nector

.Network:

.

OS

SCO

.

Software

:

MS-DOS

XENIX(R2.3.

Appications

PC/AT*

version

CPU

shadow

shadow

size

for

cache

states

to

battery

NOVELL

(3.3,

compatible

4.0

clock

block

cache

update

DRAM

and

(3.01)

4.01)or

1)

SCO

:

for

high/low

RAM

&

shadow

size

controller

read/write

external

MS

UNIX

.

Window

.

Auto-CAD

.

PC-tools(5.5)

.Lotus

.

WordPerfect^.

battery

-OS/2

(R

(3.0)

-123

with

,Telix(3.10)

.

dBASE

.Procomm

.ET(2.0),

III

(V2.4.2)

,PEII...etc.

access

(1.20),

3.2.1)

(R10)

(R3.0)

PLUS

speed

cache

differ

con

0)



by



CHAPTER

1

INTRODUCTION

/

3

BOARD

LAYOUT

3338/33380

1

1-3

FOR

3258/

340SC

4

/

325S/333S/333SC/340SC

JUMPER

SETTING

FOR

3258/

333S/333SCZ

340SC

1-4

[J3]

Mono/color

q

”

I

O

Open:

selection

mono

[

q

!

Short:

color

O

[Jll]

Turbo

LED

[ÖÖ]

[J

10]

[J13]

[J

1

PowerLED

I

OOOQO]

Speaker

4

]

External

q

O

O

1

jumper

1

battery

1.

+VDD

2.

3.6V

3.

+VDD

4.

GND

&

keylock

1.

2.

3.

4.

5.

3.

4.

jumper

(External

(Battery)

(Internal

LED

No

connect

GND

Keylock

GND

GND

+5VDC

battery

battery

output

power

power

input)

input)

[J

19]

default

1

&

4

are

2

&

3

short

2

&

3

open

condition

connectors

:

internal

:

discharge

CHAPTER

for

external

battery

used

XCMOS

1

INTRODUCTION

battery

setup

/

5

[J12]

Turbo

O

O

switch

open

:

lowspeed

or

loot

[CTRL][ALT][+]

[CTRL] [ALT]

[J2]

defau

RT

iöl

o

[J14]

Reset

i

[J9]

Cache

(for

O
O

short

lt

condition

switch

1.

GND

2.

Power

size

selection

333SC/340SC

i

1-2

short

:

[-]

high

speed

highspeed

lowspeed

good

only)

:

32KB

cache

6

/

325S/333S/333SC/340SC

[J5,J6,J7,J8]

2-3

All

All

short

short

open

:

:

:

For

64KB

For

model

model

cache

3338/3258

333SC/340SC

[J4]

[JX]

8042

Speed

8042

pin

23

24

29
30

Coprocessor

(for

model

,

__

ÍO"

|o

o|

I

2

I

2

control

J4

short

pin

header

selection

5-6

7-8

1-2

3-4

SYNC/ASYNCselection

340SC

only

)

3

l-2SYNC:Usea40MHz

coprocessor

2-3

ASYNC:Usea33MHz

coprocessor

default

header

:

5-6

short

CHAPTER

1

INTRODUCTION

/

7

8

/

325S/333S/333SC/340SC

2

CONFIGURATION

This

chapter

the

325S/333S/333SC/340SC

ers

thefollowing

.

Microprocessor

.

Math

.

Main

.

Cache

.

TheSIS

.

Shadow

.DMA

.Interrupt

.

Timer

.

Real-Time

.

Keyboard

.

I/O

Port

.

I/O

Channel

.

I/O

Channel

briefly

Coprocessor

Memory

Memory

85C310/SIS

RAM

&

controller

Controller

Clock

Controller

Address

Pin

Signal

describes

topics.

85C320/SIS

Memory

and

Nonvolatile

MAP

Assignments

Description

the

major

system

Remapping

board.

85C330

RAM

features

It

Chip

cov

Set

of



2-1

MICROPRO

CESSOR

The

325S/



AMD

or

25MHz, 33MHz,

advanced

Intel

333S/

32

-bit

333SC/

80386DX

or

40MHz.

microprocessor

CHAPTER

340SC

motherboa

microprocessor

The

80386DX

designed

2

CONFIGURATION

to

uses

run

for

an

at

is

an

ap



/

9

2-2

MATH

COPROCESSOR

plications

timized

32-bit

dresses

to

tes

agement

dress

hardware

operating

the

tems.

tion,

instruction

put.

The

hanced

3167

located

needing

for

registers

and

four

gigabytes

of

virtual

and

translation

and

systems.

simultaneous

Instruction

and

high

execution

system

by

coprocessor

beside

very

multi-tasking

and

data

data

types.

of

physical

memory.

protection

’

s

numeric

adding

registers,

a

protection

In

running

pipelining,

bus

bandwidth

an

into

the

80386

The

addition,

times

optional

high

performance

operating

paths

The

processor

memory

integrated

architecture

advanced

mechanism

the

of

multiple

on

chip

ensure

and

high

processing

80387

a

PGA(pin

CPU.

systems.

support

and

memory

80386DX

operating

address

system

power

grid

and

The

32-bit

addresses

64

teraby

man

includes

multitasking

to

support

allows

transla

short

average

through

may

be

DX

or

Weitek

array)

socket

op

ad

ad

sys

up

en

















MAIN

MEMORY

10

/

325S/333S/333SC/340SC

2-3

NOTE:

Before

make

coprocessor

system

coprocessor's

CPU's

The

following

configurations.

inserting

sure

board

speed.

the

pin

will

table

a

coprocessor

system

clock

1

is

be

in

right

damaged.

speed

lists

power

position

the

in

the

is

turned

Moreover,

should

possible

socket

off

;

otherwise,

the

match

memory

please

and

math

vour

the

DRAM

TYPE

CFG

1

2

3

4

5

6

7

8

Please

80ns

NMBS

BankO

0

256Kx4
256Kx4

1M

x

4

256Kx4

1M

x

4

1M

x

4

1MX4

use256KB/l

propagation

DRAMS.

On

Board

SIM

Module

Bankl

0
0

256Kx4

0

1M

1M

Bank2

0

0
0
0

x

4

0

x

4

0

1MX4 1MX4

1MX4

MB

delay

Memory

1MX4

RAM

time.

banks

Bank3

0
0
0
0
0
0
0

1MX4

modules

Please

are

with

as

follows:

Total

Memory

0

IM

2M

4M
5M

8M

12M
16M

70ns

do

not

use

or

2-4

CACHE

MEMORY

BANKO

BANK

BANKO

BANK

BANKO

BANK

BANKO

BANK

If

you

bytes

It

provides

cache

addition

another

select

of

internal

system.

to

64K

1

1

1

1

the

higher

If

you

the

128

bytes

model

325S/333S,

cache

RAM

performance

select

bytes

cache

CHAPTER

BANK2
BANK3

BANK2

BANK3

BANK2

BANK3

BANK2

BANK3

in

model

of

internal

RAM

2

CONFIGURATION

we

support

a

SIS

85C310chip.

than

a

pure

333SC/340SC,

cache

will

be

supported.

non

RAM,

/

128

in

11



THE

85C310

85C320

85C330

CHIP

2-5

SET

SIS

The

SIS

386

chipset

ming

of

many

/

prises

two

VLSI

/

chips

that

enable

to

be

programmed

wait

states.

set.

The

Chipset

system

The

from

board

(

Very

the

CPU

as

well

Shadow

consists

SIS

allows

functions.The

Large

and

as

the

RAM

of

the

Scale

AT

bus

memory

capability

the

program-

set

Integration

clock

and

com

rates

can

I/O

be



)

SHADOW

&

MEMORY

REMAPPING

RAM

2-6

SIS85C310
SIS85C320
SIS85C330

82C206

TheSIS

different

BIOS

The

following

Option

Cache/Memory

Bus

Daa

85C3

and

SIS

85C3

BIOS

1

64K

2

128K0E0000-0FFFFF0

3

64K

4

1

28KOEOOOO-OFFFFF

Integrated

10

areas

of

video

10

four

options:

BIOS

0F0000-0FFFFF0

0F0000-0FFFFF

Controller

Buffer

has

built-in

memory

BIOS.)

supports

Address

Controller

Peripherals

support

(

which

shadow

Video

64K

1

28K

Controller

for

shadowing

include

RAM

Video

0C0000-0CFFFF

0C0000-0DFFFF

in

system

one

of

Address

the

12

/

325S/333S/333SC/340SC

All

shadow

a

write

to

tion,

the

these

areas

and,

therefore,

considered

and

ATCYC*

The

rest

to

extended

cally.

The

memory

the

specified

shadowed

are

an

off

will

of

the

384K

memory

remapping

has

shadow

area

becomes

considered

are

cacheable.

board

be

active.

shadow

(from

area

to

be

initial

main

memory

1

MB

is

arranged

area.

read-only.

memory

A

write

cycle

area

can

to

ized

After

1

6MB)

by

initializa

to

this

(AT

be

remapped

automati

as

follows:

enabling

Reads

accesses

area

cycle)



to

is



Condition

Shadow

RAM

IM

DRAM

2M

DRAM

4M

DRAM

Over

4M

Condition

Shadow

RAM

64K

(ROM

1

28K

(ROM

64K

+

128K+

(1)

(2)

64K

128K(V

Disable

used
used

used

DRAM

Enable

Space)

Space)

(vo

Bus

obus

used

+

rom

+

rom

)

)

Remapping

384K
384K
256K

0

Remapping

256K

256K
256K

0

Memory

Memory

Size

Size

CHAPTER

2

CONFIGURATION

/

13

2-7

DMA

CONTROLLER

The

equivalents

implemented

channel

ory

transfer

and

memory

mationtransfer

The

two

provide

peripherals

fers

to

0

provides

two

DMA

compatibility.

DMA
DMA

DMA

DMA
DMA
DMA
DMA

DMA

DMA

addresses

information

DMA

four

(DMA1),

16-bit

the

devices,

Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel

of

two

in

the

82C206.Each

device

and

control

directly.

DMA

with

less

Controllers

channels

peripherals

cascade

thereby

0

:

spare

1

:

IBM

2

:

Diskette

3

:

spare

4

:

cascade

5

:

spare

6

:

spare

7

:

spare

8237A

DMA

which

will

signals

between

This

and

interconnection

allows

CPU

are

three

(

DMA2).

maintaining

SDLC

adapter

for

a

intervention.

internally

for

channels

DMA

Controllers

controller

generate

necessary

peripheral

high

speed

cascaded

transfers

DMA2

between

IBM

controller

is

the

device

to

for

trans

Channel

PC/AT

are

a

four

mem

infor

8-bit

the

1



to



to



INTERRUPT

CONTROLLER

14

/

325S/333S/333SC/340SC

2-8

The

equivalents

rupt

Controllers

They

accept

priorities

terrupt

which

to

determine

cute.

on

pending

requests

is

used

of

(PICs)

requests

to

as

an

which

two

8259

are

from

interrupts

the

CPU,

acceptance

interrupt

Programmable

included

in

peripherals,

in

service,

and

provide

index

service

the

by

routine

Inter

82C206.

resolve

issue

a

vector

the

CPU

to

exe



in



Interrupt

Level

NMI

IRQO

IRQ1

IRQ2

IRQ3

1RQ4

IRQ5

IRQ6

IRQ7

IRQ8
IRQ9

IRQ10

IRQ

11

IRQ

12

IRQ

13

IRQ

14

IRQ

15

Description

Parity

check

System

Keyboard

Interrupt

IRQ

Serial

Serial

Paral

Floppy

Paralied

15

led

timer

rerouting

port

port

printer

disk

printer

output

Clock/Calendar

Rerounting

IRQ2

Spare

Spare
Spare

Math

Coprocessor

Hard

disk

adapter

Spare

error

interrupt

2

1

adapter

toINT

buffer

port

port

from

2

1

10

from

80387

from

full

IRQ8

timer

through

hardware

8254-2

2-9

TIMERS

The

timers,each

MHz.

Timer

Timer

82C206

0

1

chip

with

The

output

request

This

fresh

can

the

0

timer

cycles.

provide

same

timing frequency

of

this

timer

(IRQO)

is

used

CHAPTER

three

programmable

is

tied

to

trigger

2

CONFIGURATION

of

to

interrupt

memory

/

1.19

re



15

2-10

REAL-TIME

CLOCK

AND

NONVOLATILE

RAM

Timer

2

The

82C206chip

nent

that

dition

to

computer

control

RAM.

consumes

for

long

(one

rechargeable

tery

connector

Adrs

Description

00

Seconds

01

Second

02

Minutes

03

Minute

04

Hours

05

Hour

06

Day

07

Data

08

Month

09

Year

0A

Status

This

timer

provides

plicationprograms

into

this

timer

frequencies.

contains

maintains

storing

system.

registers

Because

very

periods

alarm

of

of

data

configuration

It

and

of

the

little

of

time

battery

on

alarm

alarm

week

Month

Register

the

to

a

and

contains

50

bytes

use

of

power

withan

and

mainboard).

Adrs

10

11

12

13

14

15

16

17

18

A

19-2D

the speaker

can

load

different

generate

real-time

time

and

various

information

information

14

bytes

of

general

CMOS

can

be

inexpensive

one

6Vexternal

Description

technology,

clock

Diskette

byte-drives

Reserved

Mixed

disk

byte-drives

Reserved

Equipment

Low-base

High-base

Low-expansion

memory

High-expansion

memory

Reserved

tone.

counts

sound

compo

about

of

clock

purpose

maintained

battery

drive

A

and

type

C

and

byte

memory

memory

byte

Ap

in

bat

type

ad

the

and

B

D







it

16

/

325S/333S/333SC/340SC

2-11

KEYBOARD

CONTROLLER

(Continual)

Adrs

OB

OC

0D

0E

OF

The

8042

keyboard

receives

parity

ents

output

tem

for

when

Description

Status

Register

Status

Register

Status

Register

Diagnostic

Shutdown

keyboard

microprocessor

serial

serial

of

the

the

data

buffer.

when

data

the

system

data

is

available.

status

controller

interface.

data

data,

translates

to

the

The

is

placed

to poll

Adrs

B

2E-2F

C

30

D

31

32
33

34-3F

isa

programmed

The

from

the

system

controller

in

its

its

status

Description

2-byteCMOS

check

Low-expansion

memory

High-expansion

memory

Data

century

Information

(set

during

on)

Reserved

single-chip

to

keyboard

keyboard,

scan

codes,

as

a

byte

can

interrupt

output

buffer,

register

sum

byte

byte

power

8742

support

controller

checks

and

of

data

the

or

to

determine

flags

pres

in

byte

or

the

the

sys

wait



its



Data

is

controller

input

buffer

to

the

input

sent

’

to

s

status

is

ready

buffer.

the

register

keyboard

to

accept

CHAPTER

by

first

to

determine

data

and

2

CONFIGURATION

polling

then

when

writing

the

the

/

17

I/O

ADDRESS

2-12

PORT

MAP

Each

byte

an

odd

board

is

sions;

another

keyboard

previous

may

be

Hex

Range

000-01F
020-03F
040-05F
060-06F

070-07

F

080-09F

0A0-0BF

0C0-0DF

0F0

0F1

0F8-0FF

of

data

parity

required

until

byte

used

for

Devices

DMA

Interrupt

Timer,

Keyboard

Real

DMA

Interrupt

DMA

Clear

Reset

Math

is

sent

to

the

bit

automatically

to

acknowledge

byte

of

data

acknowledgment

sent.

The

"output

both

send

and

controller

controller

8254-2

I/O

time

clock,

page

register,

control!

controller

Math

Coprocessor

Math

Coprocessor

Coprocessor

keyboard

inserted.

all

should

is

buffer

receive

l,8237A-5

1,

8259A

NMI

74LS612

er

2,

8259A

2,

8237A-5

serial

data

not

be

received

full"

routines.

mask

Busy

ly

The

transmis

sent

to

for

interrupt

Usage

System
System
System
System

System
System
System
System
System
System

System

with

key

the
the




18

/

325S/333S/333SC/340SC

Hex

1

<ange

Devices

Usage

150-

200

278

2F8

300
360

378

380

3A0

3B0

3C0

3

DO

3F0

3F8

1F8

207

27F

2FF

31F
36F

37F

38F

3AF

3BF

3CF

3DF

3F7

3FF

Fixed

Disk

Game

I/O I/O

Parallel

Serial

Prototype

port

printer

2

card

port

2

Reserved

Parallel

SDLC,

Bisynchronous

Monochrome

printer

port

bisynchronous

1

display

1

printer

adapter

Reserved

Color/Graphic

Floppy

Serial

diskette

port

1

monitor

controller

2

adapter

I/O

I/O
I/O

I/O

I/O
I/O

I/O

I/O

I/O

I/O
I/O
I/O
I/O

CHAPTER

2

CONFIGURATION

/

19

2-13

I/O

CHANNEL

PIN

ASSIGNMENTS

Pin-Out

----------------------------------------------------------------

Signals

Ground

Reset

+5VDC

IRQ9

-5VDC

DRQ2

-12VDC

OWS

+

Ground

-SMEMW

-SMEMR

-IOW

-IOR

-DACK3

DRQ3

-DACK1

DRQ1

-Refresh

CLK

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

-DACK2

T/C

BALE

Drive

12VDC

Specifications

I/O

[0]

[I]

in

in

[0]

[0]

[I/O]
[I/O]

[0]

[I]

[0]

[I]

[I/O]

[0]

[I]

[I]

[I]
[I]

[I]

[0]
[0]

[0]

Pin

Bl

B2

B3

B4

B5

B6

B7

B8

B9

BIO

Bl

B12
B13

B14

B15

B16

B17
B18
B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

for

8-Bit

Expansion

No.

Signals

Al

-I/O

SD7

A2
A3

SD6

A4

SD5

SD4

A5

A6

SD3

A7

SD2

A8

SD1

SDO

A9

A10

-I/O

1

All

AEN

A12

SA19

A13

SA18

A14

SA17

A15

SA16

A16

SA15

A17

SA14

A18

SA13

A19

SA12

A20

SAH

A21

SA10

A22

SA9

A23

SA8

A24

SA7

A25

SA6

A26

SA5

A27

SA4

A28

SA3

CH

CH

Slots

CK

DRY[I]

I/O

[I]

[I/O]
[I/O]
[I/O]

[I/O]

[I/O]

[I/O]
[I/O]
[I/O]

[0]

[I/O]

I/O]

[I/O]
[I/O]

[I/O]
[I/O]

[I/O]
[I/O]

[I/O]
[I/O]
[I/O]

[I/O]

[I/O]

[I/O]

[I/O]
[I/O]

[I/O]

20

/

325S/333S/333SC/340SC

Pin-Out

Specifications

for

16-Bit

Expansion

Slots

Signals

+5VDC

OSC

Ground

-MEMCS16

-I/OCS16

IRQ

10

IRQ

11

IRQ12
IRQ15

IRQ14

-DACK0

DRQO

-DACK5

DRQ5

-DACK6

DRQ6

-DACK7

DRQ7

+5VDC

-Master

Ground

I/O

[0]

[I]

[I]

[I]
[I]
[I]
[I]

[I]

[0]

[I]

(0]

[I]

[0]

[I]

[0]

[I]

[I]

Pin

B29

B30

B31

DI

D2
D3

D4
D5

D6

D7

D8

D9

DIO

Dll

D12

D13

D14

D15

D16

D17
D18

No.

A29

A30

A31

Cl

C2
C3

C4

C5

C6

C7
C8
C9

CIO

CH

C12

C13

C14

C15

C16

C17
C18

Signals

SA2

SAI

SAO

SBHE

LA23

LA22

LA21

LA20

LA

19

LA

18

LA

17

-MEMR

-MEMW

SD8

SD9

SD10

SD1

1

SD12
SD13

SD14

SD15

[I/O]

[I/O]
[I/O]

[I/O]

[I/O]
[I/O]
[I/O]

[I/O]
[I/O]
[I/O]
[I/O]
[I/O]
[I/O]
[I/O]
[I/O]
[I/O]
[I/O]

[I/O]

[I/O]
[I/O]
[I/O]
[I/O]

2-14

I/O

CHANNEL

SIGNAL

DESCRIPTION

All

signal

loading

CLK

The

CLK

those

lines

of

two

[Output]

signals

of

CPU

are

TTL-compatible

Low-Power

of

the

CLK.

CHAPTER

I/O

Shockty

slot

are

2

CONFIGURATION

with

a

maximun

[LS]

devices.

synchronous

to

/

21

RESET

This

voltage,

SAO-

The

are

LA

DRV

signal

or

19

[Input/output]

System

latched

17-23

goes

hardware

Address

on

[Input/Output]

TheUnlatched

S

DO-15

[Input/Output]

System

BALE

The

S

high

I/O

The

indicates

Buffered

AO-SA

during

CHCK

I/O

data

[Output]

19

on to

DMA

[Input]

Channel

that

[Output]

to

the

Address

bits

Oto

Address

the

Check

a

parity

high

reset.

Lines

falling

15.

falling

cycles.

during

Lines

Latch

is

error

run

edge

edge.

an

exists

active

power-up,

from

bit

of

run

from

Enable

Th

is

low

on

0

to

"BALE"

bit

is

used

signal

signal

the

I/O

low

19.

They

.

17to23.

to

is

forced

which

board.

line

latch



22

/

325S/333S/333SC/34OSC

I/O

CHRDY

This

signal

cycle

and

can

only

onds.

IRQ3-7,

The

interrupt

request

ing

sequence:

[Input]

lengthens

should

be

held

low

9-12,14-15

Request

attention.

HIGHESTIRQ9,

be

They

the

held

for

[Input]

I/O

low

a

maximum

signals

are

prioritized

or

with

indicate

memory

read/write

a

val

id

address

of

2.5

microsec

I/O

in

the

10,11,12,14,15,3,

service

follow

.

It





4,5,6,7

-I/OR

The

I/O

instructs

bus.

-I/OW

The

I/O

the

I/O

Lowest.

[Input/Output]

read

Signal

the

I/O

device

[Input/Output]

write

is an

device

to

read

is

active

data

to

an

active

drive

low

signal

from

low

signal

which

its

data

onto

the

data

which

the

data

instructs

bus.

-SMEMR

The

system

mega

byte

-MEMR

The

Memory

location

-SMEMW

The

System

mega

by

-MEMW

Memory

being

written.

DRQ

Request

transfer.

DMA

Request

transfer.

[Output]

Memory

of

memory

[Input/Output]

Read

is

being

read.

[Output]

Memory

te

of

memory

[Input/Output]

Write

is

low

channels

channels

Read

is

Signal

Write

is

while

being

is

being

0

5

is

used

low

is

written

any

to

to

low

while

low

memory

3

are

7

are

while

.

while

.

for

for

any

location

16-bit

the

low

memory

the

low

8-bit

data

data

1

1

is

DMA

Request

channel

4

is

CHAPTER

used

internally

2

CONFIGURATION

on

the

/

23

system

A

DMA

sponding

Their

priority

DRQO,

board.

Request

DMA.

1,2,3,5,6,7

is

should

in

the

Lowest.

be

held

following

high

until

sequence:

the

Highest

corre



-DACK

The

DMA

0-3,5-7

spending

AEN

[Output]

The

DMA

controller

the

80286

-REFRESH

This

signal

and

can

be

channel.

T/C

[Output]

Terminal
count

for

SBHE

[Input/Output]

The

System

bytes

SD8-SD

[Output]

Acknowledge

acknowledge

Address

is

driving

CPU

is

driving

[Input/Output]

is

used

to

driven

by

Count

provides

any

DMA

Bus

HIGH

15

on

0

to

signals

Enable

indicate

channel

the

is

the

address

the

a

a

microprocessor

a

pulse

is

Enable

data

bus.

3,

5

to

for

DRQ

high

bus.

address

memory

when

reached.

indicates

7

when

are

0

It

is

bus.

refresh

on

the

the

corre

TO

3,5-7.

the

DMA

low

when

cycle

the

terminal

the

I/O

high



24

/

325S/333S/333SC/34OSC

-MASTER

The

Master

wh

ich

gains

low

for

a

memory

[Input]

is

control

maximum

may

be

the

lost

signal

as

of

due

from

the

master

15

microseconds

to

the

lack

the

and

I/O

should

of

processor

or

refresh.

be

held

system

-MEM

CS

The

memory

data

transfer

operation.

-I/O

CS

The

I/O

fer

isa

OSC

[Output]

The

Oscillator

color

graphic

OWS

[Input,

The

O-Wait

that

the

inserting

16

16

[Input,

Chip

1-Wait

present

an

[Input,

chip

Select

is

a

1-Wait

Open

Select

State

is

a

14.31818

board.

Open

collector]

State

indicates

bus

additional

Open

16

collector]

indicates

16-bit

cycle

wait

collector]

indicates

State

16-bit

the

data

I/O

MHz

to

can

be

state.

that

the

data

present

the

data

operation.

signal

used

microprocessor

completed

present

memory

trans

for

without

the



CHAPTER

2

CONFIGURATION

/

25

26

/

325S/333S/333SC/340SC

3

3-1

STATIC

PRECAUTIONS

INSTALLATION

This

chapter

up

a

working

340SC

its

anti-static

electricity

Static

systems.

may

circuits

to

observe

to

handle

areas

static

accidental

repairs.

sufficient

discharge:

.

Touch

static

a

grounded

.

When

system

on

a

mainboard.

precautions.

electricity

The

be

more

on

the

basic

or

with

a

humid

build-up,it

damage

The

following

to

a

grounded

electricity

unpacking

components,

anti-static

provides

system

Before

bag

read

is

charge

than

system

precautions

use

computer

is

best

protect

in

wrist

strap).

and

surface.

based

a

sufficient

board

climate

that

your

the

information

on

removing

the

section

constant

that

can

.

whenever

components.

to

always

may

measures

your

metal

object

body

handling

all

materials

for

the

325S/333S/333SC/

the

board

below

about

danger

to

build

up

in

your

to

It

is

damage

therefore

you

are

much

less

safeguard

result

in

expensive

should

generally

equipment

(or,

the

from

to

discharge

preferably,

board

should

you

to

set

from

static

computer

body

integrated

important

are

going

Although

prone

to

against

be

static

the

wear

and

other

be

placed

CHAPTER

3

INSTALLATION

/

27

When

handling

ules,

be

careful

nents

on

connectors

them

that

individual

to

avoid

and

also

plug

into

cards

contact

with

the

or

boards

with

the

"golden

expansion

the

bus.

or

mod

compo

finger"




3-2

PERIPHERALS

REQUIRED

3-3

BUILDING

A

SYSTEM

UP

.

The325S,333S,

.

An

IBM-AT

commend

supply

.

An

.

An

for

IBM-AT

IBM-AT

compatible.

.

At

least

one

1.44M..]

.

An

IBM-ATdisplay

or

compatible.

.

A

monitor

.

MS-DOS

3.

1)

Install

2)

Put

cure

3)

Plug

at

4)

Install

in

5)

Select

the

6)

Connect

7)

Connect

10orlater,orOS/2.

the

the

mainboard

it.

in

the

the

back

an

the

I/O

monochrome

card

installed

the

the

power

that

the

system.

keyboard

fixed

floppy

that

corresponds

version

SIMM

keyboard

of

the

MDA,

slot.

monitor

power

333SC,

supply

you

use

disk/floppy

disk

card:

3.10

DRAM

system

CGA,

or

in

step

supply

or

340SCmainboard.

or

compatible;

at

least

a

180

or

compatible.

disk

controller

drive

[360K,

CGA,MDA,EGA,VGA

to

or

later,

card

into

computer

connector

unit

EGA,

color

on

(4).

cable

to

connectors

the

PC-DOS

on

to

as

in

VGA,

switch

the

720K,

display

the

case

the

Figure

display

display

we

watt

power

1.2M,

card.

version

mainboard.

and

keyboard

3-1.

card

J3

to

match

card.

to

the

se

re



or



28

/

325S/333S/333SC/340SC

Power

8)

The325S,333S,

able

battery

external

9)

For

those

equivalent,

the"Power

front

of

10)

Turn

on

1

l)Turn

Connector

on

backup

who

plug

LED

the

system

the

monitor.

on

the

power

as

show

in

333SCor

board;

battery

have

in

and

unit.

34OSC

however,

to

the

the

IBM

the speaker connector

KEYLOCK"

supply.

Figure

you

J

1.

PC/AT

3-2.

has

a

recharge

can

plug

chassis

connector



in

an

or

and

at

the

CHAPTER

3

INSTALLATION

/

29

Pin

Description

1

KEYBOARD

2

KEYBOARD

3

SPARE

4

GROUND

5

+5VDC

Figure

3-1

Keyboard

1

1

POWER

I

2

3

4

5
6

1

2

3

4

5

6

1
1

I

1

I
I

I
I

I

1

+5V

+12V

-12V

GROUND

GROUND
GROUND

GROUND

-5V

+5V
+5V

+5V

GOOD

Orange

Red

Yellow

Blue

Black
Black
Black

Black

White

Red
Red

Red

Connector

CLOCK

DATA

Figure

30

/

325S/333S/333SC/34OSC

3-2

Power

Supply

Connector

ERROR

MESSAGES

FROM

SPEAKER

DISPLAY

4

4-1

OR

POWER-ON

The

Power-On

that

resides

in

cally

whenever

POST

checks

peripheral

board,

AMI-BIOS

time

is

either

played

the
the

encountered

monitor,

the

a

on

display

error

devices

performs

system

few

the

device

with

Self

Test

the

ROM-BIOS

you

turn

the

processor,

connected

disk

drives,

is

powered

during these

short

beeps

monitor.

is

several

SELF

(POST)

on

or

and

various

up.

or

If

the

initialized

short

beeps.

is

a

diagnostic

and

runs

reset

your

the

memory,

to

the

computer

others).

diagnostic

Whenever

tests,

an

error

error

the

system

TEST

automati

system.

tests

an

there

message

occurs

test

The

and

the

(Key

at

the

error

will

be

dis

before

reports







If

the

error

the

FATAL

process

is

FATAL

error.

continues

If

after

CHAPTER

the

system

the

error

reporting

4

POWER-ON

halts

after

is

NON-FATAL

the

error.

SELF

reporting

TEST

the

/

31

4-2

ERROR

MESSAGES

FROM

SPEAKER

Fatal

These

beeps

between

the

number

Errors

errors

in

an

are

infinite

two

subsequent

in

Through

conveyed

each

Beeps

process,but

sets

set.

through

there

of

error

a

is

number

enough

beeps

to

time

tell

of

Beep

Count

1

3

4

5

6

7
9

Non-Fatal

These

errors

by

several

Beep

Count

3

8

Meaning

DRAM

Base

System

Processor

Keyboard

Virtual

ROM-BIOS

Errors

are

conveyed

short

beeps.

Meaning

Conventional

ure

Display

tal

retrace

refresh

64-Kbyte

Timer

Failure

Controller-Gate

Mode

Exception

CheckSum

Through

as

and

test

and

test

failure

failure

RAM

Failure

one

long

Extended

vertical

failure

Error

Failure

Beeps

beep

and

A20

followed

test

horizon

error

fail





32

/

325S/333S/333SC/340SC

4-3

ERROR

MESSAGE

FROM

DISPLAY

Fatal

Errors

When

these

cleared,

by

CMOS

CMOS

8042

protected

INVALID

DMA

and

a

line

saying

INOPERATIONAL

shutdown

GATE-A20ERROR

mode

ERROR,

failure.

DMA

41

ERROR,

DMA

42

ERROR,

shown

errors

the

error

"SYSTEM

register

SWITCH

DMA

are

message

controller

DMA

DMA

in

Display

displayed

HALTED"

indicates

test

,

an

MEMORY

Unit

Unit

2

display

error

page

1

register
register

the

screen

is

followed

.

failure

in

getting

FAILURE

register

test
test

of

into

test

failed.
failed.

the

is

Non-Fatal

There

are

1.

Ones

th

at

the

option

2.

Ones

that

give

a

SETUP

Errors

CMOS

battery,

CMOS

CMOS

CMOS

low

or

With

battery

or

system

battery,

checksum

a

failure

two

wait

wait

a

Errors

types

for

to

run

for

option.

Setup

state

failure

options

or

in

CHAPTER

of

the

SETUP.

the

low

in

failure

failure

set

and

shown

errors

F

1

key

F

1

key

Option

indicates

the

not

in

indicates

checksum

4

POWER-ON

set

set

set

in

in

this

to

be

to

be

and

indicates

and

Display

category:

pressed

pressed

failure

checksum

checksum

CMOS

tests.

SELF

and

of

failure

TEST

and

don

CMOS

tests.

tests.

battery

/

g

ive

’

t

of

33

CMOS

display

display

CMOS

Configuration

CMOS

verification.

memory

time

Configuration

timer).

type

size

and

setup

&

date

verification

mismatch

mismatch

failure.

not

set

error

indicates

indicates

indicates

and

setup

failure

a

a

error

System

System

(in

of

Errors

CH-2

timer

failure.

Keyboard

KB

/Interface

Display

type

verification

Keyboard

HDD

controller

verification

C

:

Drive

D

:

Drive

D

:

Drivefailure

Without

error

error

error

switch

is

locked.

error

error
error

Setup

indicates

indicates

indicates

setting

error.

..

error

in

hard

indicates

indicates

indicates

not

proper

Unlock

indicates

disk

hard
hard

Option

channel

keyboard

keyboard

it.

system

setup.

disk

disk

hard

disk

2,1,0

test

failure.

test

indicates

Configuation

setup

error

setup

error

failure.

timer

failure.

display

test

34 /

325S/333S/333SC/340SC

BIOS

(C)

SETUP

1990

5

American

AMI

AMI

BIOS

340SC

system

pleted,

gram

will

PROGRAM

Megatrends

BIOS

is

designed

motherboard

easily.

After

press

the

appear

-

AMI

<ESC>

in

BIOS

Inc.,

SETUP

in

to

so

that

the

memory

key

Ti

few

SETUP

All

the

users

and

seconds.

Rights

325S/333S/333SC/

can

configure

test

has

been

the

following

UTILITIES

Reserved

their

com

dia




AUTO

Standard

-------

1

ESC:

STANDARD

ADVANCED

ADVANCED

AUTO

CONFIGURATION

CONFIGURATION

WRITE

DO

NOT

CMOS

Setup

Exit

CHANGE

HARD

TO

WRITE

for

changing

Sel

CMOS

CMOS

CHIPSET

WITH

WITH

PASSWORD

DISK

UTILITY

CMOS

TO

CMOS

Time,

F2/F3:

SETUP

SETUP

SETUP

BIOS

POWER-ON

AND

EXIT

AND

Date,

Color

CHAPTER

DEFAULTS

EXIT

Hard

F10:

5

AMI

DEFAULTS

Disk

Type,

Save

&

Exit

BIOS

SET-UP

etc.

I

/

35

STANDARD

CMOS

5-1

SETUP

This

is

system

display,

there

left

bottom

menu

a

general

components

and

memory.

will

be

online

of

for

the

STANDARD

the

setup

such

help

menu.

tor

as

Once

information

the

user

floppy

a

Figure

CMOS

field

drive,

to

configúrelos

harddisk,

is

highlighted

shown

5-1

is

a

SETUP.

in

sample

the

BIOS

(C)

Date

Time

Floppy

Floppy

Hard
Hard

Primary

Keyboard

Month

Date

Year

ESC:Exit,4,

Figure

SETUP

1990

(mn/date/year);

(hour/min/sec);18:35:40

drive

A

drive

B

disk

C

disk

D

display

”

>T^

“

PROGRAM

American

: :

1.2

:

Not

:type

:

Not

:

type

:

Not

:

Monochrome

:

Installed

Jan,Feb

01,02,03

1901,1902

:

Select,

PgU

5-1

Megatrends

MB,

.............

.............

p/Pg/Dn

CMOS

5.25"

Installed

Installed

Installed

Dec

31

...........

=

Setup

-STANDARD

Inc.;

All

Base

Ext.

C

yin

Head

Sun

31

7

14

21

2099

Modify

28

4

Screen

Rights

memory

memory

WPcom

Mon

1

8

15

22

29

5

CMOS

size

Tue

2.

9

16

23

30

6

SETUP

Reserved

size

:640

:

3328KB

LZone

Thu

Wed

4

3

10

1

18 19

17

24

25

3

1

8

7

KB

Sect

Size

Fri

Sat

5

6

12

1

1

26

13

20

27

2

3

9

10

36

/

325S/333S/333SC/340SC

AMI

Hard

Disk

Types

Reference

Type

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27
28
29
30

31

Cylinders

306

615

615

940
940

615

462

733

900

820

855
855

306

733

000
612

977

977

1024

733
733
733

306

325

925
754

754
699

823

918

1024

Heads

4

4
6

8

6

4

8

5

15

3

5
7

8

7

0

4

5

7

7
5
7
5

4

7

9

7

11

7

10

7

11

Write-

Precomp

128

300

300

512
512

65535

256

65535
65535

65535

65535

65535

128

65535

000

0000

300

65535

512

300

300
300

0000
0000

65535

754

65535

256

65535

818

65535

Landing

Zone

305

615
615

940
940

615

511

733

901

820

855

855

319

733

000

663
977

977

1023

732

732

733

336

925
925

754
754

699

823

918

1024

Capacity

(Mbytes)

20

31

62
47
20

31

30

20

35

50
20

43

00
20

41

57

60

30

43

30

54

69
44
69

41

68

53

94

10

112

10

CHAPTER

5

AMI

BIOS

SET-UP

/

37

Type

Cylinders

Heads

Write-

Precomp

Landing

>

Zone

Capacity

(Mbytes)

ADVANCED

CMOS

5-2

SETUP

1024

32

1024

33

612

34

1024

35

1024

36

615

37

987

38

987

39

820

40

977

41

981

42

830

43

830

44

917

45

1224

46

Choose

SETUP"

CMOS

with

333S

the

.

facturer's

15

5

2

9

8
8

3

7

6
5

5

7

10

15
15

the

second

at

the

beginning

Setup

Program.

manufacturer's

Figure

5-3

is

default

values

65535

1024

128

65535

512

128

987
987

820

977

981

512

65535
65535
65535

option

Figure5-2

default

a

sample

for

1024

1024

612

1024

1024

615
987
987

820

977

981

830
830

918

1223

"ADVANCD

to

enter

is

a

values

menu

and

the

333SC/340SC.

the

Advance

sample

for

the

with

128

43

10

77
68

41

25
57

41
41
41

48
69

114

152

CMOS

menu

325S/

manu



38

/

325S/333S/333SC/340SC

Figure

BIOS

(C)

5-2

1990

SETUP

ADVANCED

PROGRAM

American

SETUP

Megatrends

SCREEN

-

ADVANCED

Inc.,

FOR

325S/333S

CMOS

SETUP

All

Rights

Reserved

Typematic

Typematic

Typematic

Above

Memory

Memory

Hit

<

Hard

Wait

For

System

Nuneric

Weitek

Floppy

System
System

Cache

Cache

Shadow

__i

1

MB

Test

Parity

ESC

Disk

<

Boot

Processor

Processor

Drive

Boot

Boot

Select

Wrtie

RAM

ESC:Exit

Rate

Rate

Rate

Memory

>

Message

Type

Fl

Up

Up

Wait

Tick

>

Seek

Up

(see

Programming

Delay

(msec)

(Chars/sec)

Test

Sound

Error

Check

Display

47

Data

Area

If

Any

Error

Num

Lock

At

Boot

Sequence

CPU

Speed

State

Help

)

F5:

Old

Vals

DRAM

Wait

State

(see

Help

Slate

State

F2/F3:

for

Color

)

325S

-2W/S

:

SCLK/3

:7.16MHZ

-5

W/S

-2W/S

d

:

Disabled

Bus

Clock

Bit

Bit

Modify

F7:

Speed:

Speed

Clock

AT

Cycle

AT

Cycle

Fl:

Power-on

Select

Wait

Wait

Help

Defaults

SCLK/3

250

PU/PD:

Defaults

Clock

DMA

8

16

:10.0

:

Disabled

:

Enabled

-Enabled

-Enabled

0.300

:

Disabled

-On

-Absent

:

Absent

-Disabled

-A-,C-

:High

:

Internal

:OW/S

<?+F

Sel

(CTRL)

F6:

BIOS

Setup

Note:Bus

SCLK/4for333S

CHAPTER

5

AMI

BIOS

SET-UP

/

39

Figure

BIOS

(C)

SETUP

1990

5-3

American

ADVANCED

PROGRAM

Megatrends

SETUP

-

ADVANCED

Inc.,

SCREEN

All

CMOS

Rights

FOR

Reserved

333SC/340SC

SETUP

Typematic

Typematic

Typematic

Above

1

Memory

Memory

Hit

<

ESC

Hard

Disk

Wait

For

System

Boot

Nuneric

Weitek

Processor

Floppy

Drive

System

System

Cache

Select

Cache

WrGe

Shadow

Rate

Rate
Rate

MB

Memory

Test

Tick

Parity

>

Message

Type

<F1

>

Up

Processor

Seek

Boot

Up

Boot

Up

Wait

RAM

(see

ESC:

Exit

Programm!

Delay

(msec)

(Chars/sec)

Test

Sound

Error

Check

Display

47

Data

If

Any

Error

Num

Lock

At

Boot

Sequence

CPU

Speed

Slate

Help

F5:

OldValsFó:

Area

)

ng

BlOSSetupDefaults

-Disabled

250

.10.0

:Di

sableó

:

Enabled

-Enabled

-Enabled

-0-300

-Disabled

-On

:

Absent

:

Absent

-Disabled

A--C-

-High

Ó4KB+

:O

W/S

C+F

Sel

(CTRL)PU/PD:

Note:DRAM

DRAM

Bus

Clock

DMA

Clock

8

Bit

AT

16

Bit

AT

Modify

F7:

Power-onDefaults

Wait

State:

Wait

Cycle

Speed

Select

Cycle

Fl:

State

(see

Wait

Wait

HelpF2/F3:

2

W/S

3

W/S

State

State

Help

for

for

)

Color

333SC

340SC

2

W/S

-SCLK/4

:7.16MHZ

-5

W/S

-2

W/S

40

/

325S/333S/333SC/340SC