CEL NE5500179A User Manual
查询NE5500179A供应商
DATA SHEET
SILICON POWER MOS FET
NE5500179A
4.8 V OPERATION SILICON RF POWER LD-MOS FET
FOR 1.9 GHz 1 W TRANSMISSION AMPLIFIERS
DESCRIPTION
The NE5500179A is an N-channel silicon power MOS FET specially designed as the transmission driver amplifier
for 4.8 V GSM 1 800 and GSM 1 900 handsets. Dies are manufactured using NEC’s NEWMOS technology (NEC’s
0.6 µm WSi gate lateral-diffusion MOS FET) and housed in a surface mount package. The device can deliver 30.0
dBm output power with 55% power added efficiency at 1.9 GHz under the 4.8 V supply voltage, or can deliver 27
dBm output power with 50% pozwer added efficiency at 3.5 V, respectively.
FEATURES
• High output power : P
• High power added efficiency :
• High linear gain : GL = 14.0 dB TYP. (VDS = 4.8 V, I
• Surface mount package : 5.7 × 5.7 × 1.1 mm MAX.
• Single supply : VDS = 3.0 to 6.0 V
= 30.0 dBm TYP. (VDS = 4.8 V, I
out
= 55% TYP. (VDS = 4.8 V, I
η
add
= 200 mA, f = 1.9 GHz, Pin = 20 dBm)
Dset
= 200 mA, f = 1.9 GHz, Pin = 20 dBm)
Dset
= 200 mA, f = 1.9 GHz, Pin = 10 dBm)
Dset
APPLICATIONS
• Digital cellular phones : 4.8 V driver amplifier for GSM 1 800/ GSM 1 900 class 1 handsets, or 4.8 V final stage
amplifier
• Digital cordless phones : 3.5 V final stage amplifier for DECT
• Others : General purpose amplifiers for 1.6 to 2.5 GHz TDMA applications
ORDERING INFORMATION
Part Number Package Marking Supplying Form
NE5500179A-T1 79A R1 • 12 mm wide embossed t api ng
• Gate pin face the perforation s i de of the tape
• Qty 1 kpcs/reel
Remark To order evaluation samples, consult your NEC sales representative.
Part number for sample order: NE5500179A
Caution Please handle this device at static-free workstation, because this is an electrostatic
sensitive device.
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices
representative for availability and additional information.
Document No. PU10118EJ01V1DS (1st edition)
(Previous No. P15190EJ1V0DS00)
Date Published April 2002 CP(K)
Printed in Japan
The mark
shows major revised points.
!!!!
NEC Compound Semiconductor Devices 2002
NEC Corporation 1999
ABSOLUTE MAXIMUM RATINGS (TA = +25°°°°C)
Parameter Symbol Ratings Unit
NE5500179A
Drain to Source Voltage V
Gate to Source Voltage V
Drain Current I
Drain Current (Pulse Test)
!
Total Power Dissipation P
Channel Temperature T
Storage Temperature T
!
Note Duty Cycle ≤ 50%, T
≤ 1 s
on
DS
GSO
D
Note
I
D
tot
ch
stg
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Test Condit i ons MIN. TYP. MAX. Unit
Drain to Source Voltage V
Gate to Source Voltage V
!
Drain Current (Pulse Test) I
Input Power P
DS
GSO
D
in
ELECTRICAL CHARACTERISTICS (TA = +25°°°°C)
8.5 V
5.0 V
0.25 A
0.5 A
10 W
125 °C
−65 to +125 °C
3.0 4.8 6.0 V
02.03.5V
Duty Cycle ≤ 50%, Ton ≤ 1 s − 340 − mA
f = 1.9 GHz, VDS = 4.8 V 0 20 22 dBm
Parameter Symbol Test Conditions MIN. TY P . MAX. Unit
Gate to Source Leak Current I
Saturated Drain Current
(Zero Gate Voltage Drain Current)
Gate Threshold Voltage V
Transconductance g
Drain to Source Breakdown Voltage BV
Thermal Resistance R
Linear Gain G
Output Power P
Operating Current I
Power Added Efficiency
!
Notes 1. Peak measurement at Duty Cycle ≤ 50%, T
2. DC performance is 100% testing. RF performance is testing several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
V
GSO
I
DSS
th
m
DSIDSS
th
L
out
op
η
add
= 5.0 V −−100 nA
GSS
V
= 8.5 V −−100 nA
DSS
VDS = 4.8 V, IDS = 1 mA 1.0 1.45 2.0 V
VDS = 4.8 V, IDS = 250 mA − 420 − mS
= 10 µA2024− V
Channel to Case − 10 −°C/W
f = 1.9 GHz, Pin = 10 dBm,
V
= 4.8 V, I
DS
= 200 mA,
Dset
Note 1, 2
− 14.0 − dB
f = 1.9 GHz, Pin = 20 dBm, 28.5 30.0 − dBm
VDS = 4.8 V, I
= 200 mA,
Dset
Note 1, 2
− 340 − mA
48 55 − %
≤ 1 s.
on
2
Data Sheet PU10118EJ01V1DS
TYPICAL CHARACTERISTICS (TA = +25°°°°C)
NE5500179A
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
3.5
VGS = 10 V MAX.
Step = 1.0 V
3.0
2.5
(A)
D
2.0
1.5
1.0
Drain Current I
0.5
0
Drain to Source Voltage VDS (V)
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
35
VDS = 4.8 V
Dset
= 100 mA
I
f = 1.9 GHz
30
P
(dBm)
out
25
20
Output Power P
15
10
out
I
D
Input Power Pin (dBm)
161412108624
500
400
(mA)
D
300
200
Drain Current I
100
0
302515105020
SET DRAIN CURRENT vs.
GATE TO SOURCE VOLTAGE
1 000
(mA)
Dset
Set Drain Current I
VDS = 4.8 V
100
10
1
0.1
Gate to Source Voltage VGS (V)
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. INPUT POWER
100
V
DS
= 4.8 V
Dset
= 100 mA
I
f = 1.9 GHz
(%)
add
η
η
(%)
d
η
50
Drain Efficiency
Power Added Efficiency
0
Input Power Pin (dBm)
d
η
add
3.02.52.01.51.0
30252015105
OUTPUT POWER, DRAIN CURRENT
vs. GATE TO SOURCE VOLTAGE
31
VDS = 4.8 V
f = 1.9 GHz
in
= 20 dBm
P
30
(dBm)
out
29
28
Output Power P
27
26
Gate to Source Voltage VGS (V)
P
out
I
D
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. GATE TO SOURCE VOLTAGE
500
400
(mA)
D
300
200
Drain Current I
100
0
4.02.01.00.0 3.0
Data Sheet PU10118EJ01V1DS
100
(%)
add
η
(%)
d
η
50
Drain Efficiency
Power Added Efficiency
0
V
DS
= 4.8 V
f = 1.9 GHz
in
= 20 dBm
P
η
d
η
add
Gate to Source Voltage VGS (V)
4.03.02.01.0
3
NE5500179A
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
30
VDS = 3.5 V
Dset
= 100 mA
25
(dBm)
out
20
I
f = 1.9 GHz
P
out
15
I
D
Output Power P
10
5
Input Power Pin (dBm)
OUTPUT POWER, DRAIN CURRENT
vs. GATE TO SOURCE VOLTAGE
28
V
DS
= 3.5 V
f = 1.9 GHz
in
= 18 dBm
P
27
(dBm)
out
26
25
Output Power P
24
23
Gate to Source Voltage VGS (V)
P
out
I
D
500
400
(mA)
D
300
200
Drain Current I
100
0
302515105020
500
400
(mA)
D
300
200
Drain Current I
100
0
4.02.01.00.0 3.0
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. INPUT POWER
100
V
DS
= 3.5 V
Dset
= 100 mA
I
f = 1.9 GHz
(%)
add
η
η
(%)
d
η
50
Drain Efficiency
Power Added Efficiency
0
d
η
add
30252015105
Input Power Pin (dBm)
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. GATE TO SOURCE VOLTAGE
100
V
DS
= 3.5 V
f = 1.9 GHz
in
= 18 dBm
50
P
η
d
η
add
0
4.03.02.01.0
Gate to Source Voltage VGS (V)
(%)
add
η
(%)
d
η
Drain Efficiency
Power Added Efficiency
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
30
VDS = 4.5 V
Dset
= 100 mA
25
(dBm)
out
20
I
f = 460 MHz
P
out
15
I
Output Power P
10
D
5
Input Power Pin (dBm)
4
DRAIN EFFICIENCY, POWER ADDED
EFFICIENCY vs. INPUT POWER
500
400
(mA)
D
300
200
Drain Current I
100
0
25201050–5 15
Data Sheet PU10118EJ01V1DS
100
(%)
add
η
(%)
d
η
50
Drain Efficiency
Power Added Efficiency
0
VDS = 4.5 V
Dset
= 100 mA
I
f = 460 MHz
Input Power Pin (dBm)
η
d
η
add
2520151050–5
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