CCE T546P Schematic

5

4

3

2

1

Topstar Digital technologies Co.,LTD

D D

Board name: MotherBoard Schematic Project name: C46 Version: VerA Initial Date: MAY.9, 2008

02. System block & Index

03. PWR Block & Description

04. Notes & Annotations

05. Schematic Modify and History

59. CLOCK Distribution

60. Power on & off Sequence

60. Power On Sequence & Reset Map

61. ACPI Mode Switch Timings

Topstar Confidential

C C

Hardware drawing by:

Power drawing by:

Hardware check by: EMI Check by:

Power check by:

Manager Sign by:

B B

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent Title

Title

C46

1

159Friday, November 27, 2009

A

of

5

4

3

2

1

Topstar Confidential

ShenZhen Topstar Industry Co.,LTD

D D

Backlight Connector

+VDC

TFT

+V3.3S

C C

LVDS switch

VGA

+V5S

LVDS

PCIE mini Card

B B

PCIE mini Half-Card

NEW CARD(Type II)

C46 SYSTEM BLOCK Ver:A

Only for PM

64M*16Bit*4 GDDRIII

+V1.5GDDR

Memory

Nvidia NB11

Camera

1.3M/2.0M MODULE

interface

+VGA_CORE, +V1.05GPU +V1.8GDDR, +V3.3GPU +V1.5GPU

PCIE 1X

HDMI

BLUE TOOTH(V1.2)

BTM-203/CCOM

+V3.3S

+V3.3AL

LVDS

R/G/B TMDS

PCI-Express X16

USB1.1/2.0

PEGX16 /eDP

USB PORT1

+V5AL

SPI

BIOS

8Mbit

+V3.3AL

KB Controller/EC

+V3.3AL,+V3.3S,+V5AL

Arrandule/clarsfield

989rPGA

+VCC_CORE,+VccGFX +V1.5S, +V1.8S, +V1.1S_VTT

FDI

DMI*4 100MHz

Ibex_peak

1071 BGA

+V3.3A,+V3.3S,+V1.5S, +V1.05S,+V1.8S, +V5A,+V5S

LPC

ENE 3926

SLG8SP585

+V3.3S

DDR3 800/1066

PCIE 1X

USB1.1/2.0

AZALIA

TCM

CK505M Clocking

+V3.3S,+V3.3AL

DDR3 SODIMM0 800/1066

+V0.75S,+V1.5,+V3.3S

DDR3 SODIMM1 800/1066

+V0.75S,+V1.5,+V3.3S

RJ45

RTL8102E

SATA ODD

S-ATA

2.5" HDD

+V5S,+V3.3S

+V5S

Card Reader

ITE 1337

+V3.3S,+V3.3AL

L

R

AZALIA

ALC662

+V5S,+V3.3S

RJ45

SD/MMC/MS CARD

MiC

LED/TouchPAD/Button/

DAUGHTER BOARD

KB Matrix

A A

5

4

3

Q-key/LID

DAUGHTER BOARD

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

bent Sys block

Sys block

C46

1

A

259Friday, November 27, 2009

A

of

5

4

3

2

1

C46 POWER BLOCK Ver:A

Platform Logic

D D

VIN V_5 V_3

VR_ON

IMVP-6.5

CLK_ENABLE#

IMVP6_PWRGD

PCH CPU-M

C C

CLK CHIP

注意:

虚线表示电源电压信号。

VCC_SENCE VSS_SENCE

IMON

VR_TT# Vcc_core

VID[6...0] PSI# DPRSLPVR

CPU_PWRGD

PSI#

PROCHOT#

Charge ISL6251

Adapter

B B

65/90W

Battery

Power Switch

+VDC

5A

51A

+VCC_CORE

VCC_CORE ISL62882

+V1.8S

MOSFET

+V1.8GPU

KIA1117

Always_On Power

ISL62872

+VGA_CORE

10A

A A

5

ISL62881

+VGFX

14A

TPS51218

+V1.05S

8A

+V1.05GPU

2.5A

MOSFET

TPS51218

+V1.1S_VTT

18A

4

TPS51125

+V3.3AL +V5AL

5A/5A

MOSFET

+V3.3GPU

<0.5A

DDR Power TPS51218 +APL5331

12A/2.5A

MOSFET

+V1.5GPU

3A

+V1.5 +V0.75S

3

+V1.5S

3A

+V5S +V3.3S

MOSFET

System Power +V_S

TOPSTAR TECHNOLOG

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

bent

PWR Block

C46

1

A

359Friday, November 27, 2009

A

of

5

4

3

2

1

Voltage Rails

+VDC

D D

+VCC_CORE

+V1.1S_VTT

+V1.05S +V0.75S +V1.5

+V3.3AL

+V3.3S +V5AL +V5S +VGA_CORE

+V1.5S

+V1.8S

+V3.3GPU

+V1.05GPU

C C

+V1.8GPU 1.8V for external GPU

+V1.5GPU 1.5V for external GPU

Primary DC system power supply(9V-19V) Core voltage for processor

1.1V for CPU

1.05V for PCH core

0.75V DDR3 Termination voltage

1.5V power rail for DDR3

3.3V always on power rail

3.3V main power rail 5V for USB Device 5V main power rail

0.8--1.03V for GPU NB8M core voltage

1.5S for PCIE Device

1.8V for display votage

3.3V for external GPU

1.05V for external GPU

I2C SMB Address

Device

Clock Generator SO-DIMM0 SO-DIMM1 NEW CARD PCIE Mini CARD

Smart Battery

0001 011x 16 I2C ENE3926

Address

1101 001x 1010 000x 1010 010x

Variable Variable SMB1_PCHPCH

BusHex

SMB_PCH

D2

SMB_PCH

A0

SMB_PCH

A4

SMB_PCH

VariableVariable

SMB_PCH

VariableVariable

Master

PCH PCH PCH PCH PCH

ENE3926

Power States/AC mode

Board stack up description

PCB Layers

TOP

GND

IN1

IN2

VCC

IN3

B B

GND

Bottom

Trace Impedence:50ohm +/-15%(Default)

Signal

S0(Full On) S3(STM) S4(STD) S5(SoftOff)

SLP_S3#

HIGH LOW LOW OFF LOW

SLP_S4#

HIGH HIGH ON OFF LOW LOW

SLP_S5#

HIGH HIGH HIGH LOW

+V*AL

ON

ON ON

+V*

ON ON ON

OFF

+V*S

OFF OFF OFF

Clock

ON

OFF OFF

Wake up Events

USB Table

USB Port#

A A

Function Description

0

Express Card

1

minicard1

reserved

2

3

camera

4

USB port1

5

Bluetooth

6

Reserved

7

Reserved

8

CARD Reader

9

minicard2

10

USB port2

11

USB port3

5

4

3

LID switch from EC Power switch from EC

TOPSTAR TECHNOLOG

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Notes

C46

bent

A

459Friday, November 27, 2009

1

A

of

5

4

3

2

1

VerA to VerB Changelist

1.

外置

VBIOS ROM

2. 27M clock

3.PCH 端100M的CLK-REQ#

4. PCH GPIO16

D D

5.Switch IC的footprint

6. RGB的ESD

7. HDMI

接到EC的

8. SYS_RST#

9.SIM 卡/

键盘/电池三个

10.GPU_RST#

11.HD connecter 和TP

12.BT connect

VerB to VerC Changelist

1. N11M

那边加上背光控制的与门解决开机屏就白着的问题。

2.

C C

蓝牙那边的那组

3.EC那边IMVP_ON的1K

VerC to VerD Changelist

1.N11M

那边

2. 3.3AL/5AL

USB线P/N

HDMI

电那边

改成内置，

的串联电阻

0ohm

下拉改为上拉。

下拉改为上拉，

改成符合实物的。

管子摆放方向改正。

预留

detect 0hm

信号接法调整。

connecter换footprint

预留上拉。

键的左右按钮物料更改。

那边有改发

反转过来，之前接反了。

电阻换

0ohm

。（电源那边已经分压了）。

信号线连接有误。

colay 220uf poscap

srrap

改为

上拉改为

33ohm

15K

。

follow CHECK LIST

ECN

注意不要遗漏

D2+/-与D1+/-

的电容。

调换。

。

B B

TOPSTAR TECHNOLOG

bent

Page Name

Size

A A

5

4

3

Size

Project Name Rev

A

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

history

C46

A

of

559Friday, November 27, 2009

1

5

4

+V3.3S {8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57} +V3.3AL {23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56}

3

2

1

0.1UF/25V,Y5V

C216

C234

0.1UF/25V,Y5V

C0402

+V3.3S

R247

R247 10K

10K

R0402

C217

0.1UF/25V,Y5V

C0402

+V3.3S

R277

R277 10K

10K

R0402

ns

+V3.3S_CK_VDD

C220

0.1UF/25V,Y5V

C0402

+VDDIO_CLK

C229

0.1UF/25V,Y5V

C0402

C227

C0402

Layout Note: Cap Close to CK505 PWR pin

C222

0.1UF/25V,Y5V

C0402

CLK_BUF_REF14

C232 10PF/50V,NPOnsC0402C232 10PF/50V,NPOnsC0402

C231 27pF/50V,NPO

C0402

2 1

C233 27pF/50V,NPO

C0402

update Y1 footprint

+V3.3S_CK_VDD

+VDDIO_CLK

No more than 500 mil

Y1

43

14.318MHz

XS4_5032_0D8

XTAL_IN XTAL_OUT

1

5 17 29

24 18 15

G1 G2 G3 G4

28 27

G5

2

8

9 12 21 26

U12

VDD_DOT VDD_27 VDD_SRC VDD_REF

VDD_CPU VDD_CPU_IO VDD_SRC_IO GND1 GND2 GND3 GND4 XTAL_IN

XTAL_OUT GND5

VSS_DOT VSS_27 VSS_SATA VSS_SRC VSS_CPU VSS_REF

CK505QFN32

SMB_DATA

SMB_CLK

CPU_STOP#

CPU0

CPU0#

CPU1

CPU1# DOT96

DOT96#

SRC0/SATA

SRC0#/SATA

SRC1

SRC1#

27M_NSS

27M_SS

REF/FS

CK_PWRGD/PWRDWN#

SMBUS ADD:1101 001X

31 32

16 23

22 20

19 3

4 10

11 13

14 6

7 30

25

R275 0 R0402R275 0 R0402

R276 0 R0402R276 0 R0402

CPU_STOP# BCLK

R264 0 R0402R264 0 R0402

BCLK#

R261 0 R0402R261 0 R0402

Integrated resistors on differentail clk

DOT96

R262 0 R0402R262 0 R0402

DOT96#

R260 0 R0402R260 0 R0402

R243 0 R0402R243 0 R0402

R242 0 R0402R242 0 R0402

R241 0 R0402R241 0 R0402

R240 0 R0402R240 0 R0402

BCLK_FS

R278 33 R0402R278 33 R0402

CLK_PWRGD

SMB_DATA_S {15,16,23,40,41} SMB_CLK_S {15,16,23,40,41}

CLK_BUF_BCLK_P {23} CLK_BUF_BCLK_N {23}

CLK_BUF_DOT96_P {23} CLK_BUF_DOT96_N {23}

CLK_BUF_SATA_P {23} CLK_BUF_SATA_N {23}

CLK_BUF_EXP_P {23} CLK_BUF_EXP_N {23}

27M_nonSSC {20}

27M_SSC {20}

CLK_BUF_REF14 {23}

FB10 100ohm@100MHz,3A

D D

C C

B B

+V3.3S

12

FB0805

C226

10UF/6.3V,X5R

0.1UF/25V,Y5V

C0805

CPU_STOP#

FB9 100ohm@100MHz,3A

1 2

FB0805

C230

10UF/6.3V,X5R

C0805

Frequence Select High:100Mhz Low:133Mhz(Default)

C223

C0402

C0805

BCLK_FS

+V3.3S

R307

R307 10K

10K

R314

R0402

10K

ns

10K

ns

R0402

3

PQ32

PQ32 2N7002

2N7002

SOT23

R317 1K

CK505_CLK_EN#{55}

A A

5

R317 1K

R0402

C249

C0402ns

0.1UF/25V,Y5V

4

SOT23

1

2

C244

C0402

0.1UF/25V,Y5V

R306 0nsR306 0ns

+V3.3AL

C236

0.1UF/10V,X7R

53

VCC

1 2

GND

CLK_PWRGD

4 SOT23_5

SOT23_5

SN74AHC1G08DBV

SN74AHC1G08DBV U15

U15

TOPSTAR TECHNOLOG

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

CK505M

M21

bent

B

659Friday, November 27, 2009

1

B

of

5

4

3

2

1

U2A

D D

C C

B B

A A

5

DMI_TXN0{24} DMI_TXN1{24} DMI_TXN2{24} DMI_TXN3{24}

DMI_TXP0{24} DMI_TXP1{24} DMI_TXP2{24} DMI_TXP3{24}

DMI_RXN0{24} DMI_RXN1{24} DMI_RXN2{24} DMI_RXN3{24}

DMI_RXP0{24} DMI_RXP1{24} DMI_RXP2{24} DMI_RXP3{24}

FDI_TXN[7:0]{24}

FDI_TXP[7:0]{24}

FDI_FSYNC0{24} FDI_FSYNC1{24}

FDI_INT{24}

FDI_LSYNC0{24} FDI_LSYNC1{24}

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

DMI Intel(R) FDI

4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS PEG_RX#[0]

PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_IRCOMP_R

EXP_RBIAS

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

R560 49.9,1%

R552 750 OHM

PEG_RXN[15:0] {17}

PEG_RXP[15:0] {17}

GC1320.1UF/10V,X7RGC1320.1UF/10V,X7R GC1850.1UF/10V,X7R GC1850.1UF/10V,X7R

GC1270.1UF/10V,X7R GC1270.1UF/10V,X7R

GC1830.1UF/10V,X7R GC1830.1UF/10V,X7R GC1230.1UF/10V,X7R GC1230.1UF/10V,X7R GC1780.1UF/10V,X7RGC1780.1UF/10V,X7R GC1180.1UF/10V,X7RGC1180.1UF/10V,X7R GC1730.1UF/10V,X7RGC1730.1UF/10V,X7R GC1120.1UF/10V,X7R GC1120.1UF/10V,X7R GC1690.1UF/10V,X7RGC1690.1UF/10V,X7R GC1070.1UF/10V,X7R GC1070.1UF/10V,X7R

GC1640.1UF/10V,X7RGC1640.1UF/10V,X7R GC1030.1UF/10V,X7RGC1030.1UF/10V,X7R

GC1590.1UF/10V,X7RGC1590.1UF/10V,X7R

GC960.1UF/10V,X7R GC960.1UF/10V,X7R

GC1550.1UF/10V,X7R GC1550.1UF/10V,X7R

GC1300.1UF/10V,X7RGC1300.1UF/10V,X7R

GC1840.1UF/10V,X7RGC1840.1UF/10V,X7R

GC1260.1UF/10V,X7RGC1260.1UF/10V,X7R

GC1810.1UF/10V,X7RGC1810.1UF/10V,X7R

GC1210.1UF/10V,X7RGC1210.1UF/10V,X7R

GC1770.1UF/10V,X7RGC1770.1UF/10V,X7R

GC1170.1UF/10V,X7RGC1170.1UF/10V,X7R

GC1720.1UF/10V,X7RGC1720.1UF/10V,X7R

GC1110.1UF/10V,X7RGC1110.1UF/10V,X7R

GC1670.1UF/10V,X7RGC1670.1UF/10V,X7R

GC1060.1UF/10V,X7RGC1060.1UF/10V,X7R

GC1620.1UF/10V,X7RGC1620.1UF/10V,X7R

GC1010.1UF/10V,X7RGC1010.1UF/10V,X7R

GC1580.1UF/10V,X7RGC1580.1UF/10V,X7R

GC94 0.1UF/10V,X7RGC94 0.1UF/10V,X7R

GC1540.1UF/10V,X7RGC1540.1UF/10V,X7R

3

R0402

PEG_NV_RXN0 PEG_NV_RXN1 PEG_NV_RXN2 PEG_NV_RXN3 PEG_NV_RXN4 PEG_NV_RXN5 PEG_NV_RXN6 PEG_NV_RXN7 PEG_NV_RXN8 PEG_NV_RXN9 PEG_NV_RXN10 PEG_NV_RXN11 PEG_NV_RXN12 PEG_NV_RXN13 PEG_NV_RXN14 PEG_NV_RXN15

PEG_NV_RXP0 PEG_NV_RXP1 PEG_NV_RXP2 PEG_NV_RXP3 PEG_NV_RXP4 PEG_NV_RXP5 PEG_NV_RXP6 PEG_NV_RXP7 PEG_NV_RXP8 PEG_NV_RXP9 PEG_NV_RXP10 PEG_NV_RXP11 PEG_NV_RXP12 PEG_NV_RXP13 PEG_NV_RXP14 PEG_NV_RXP15

PEG_NV_RXN[15:0] {17}

PEG_NV_RXP[15:0] {17}

2

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

B

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent Arrandule

Arrandule

C46

A

of

759Friday, November 27, 2009

1

5

4

3

2

+V1.1S_VTT {10,11,27,28,29,38,50,51,55} +V3.3S {6,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5 {11,15,16,49,56,57}

1

D D

U2B

H_COMP3 H_COMP2 H_COMP1

0 R0402

R213

R185

R185 750 OHM

750 OHM

R0402

H_COMP0

H_CATERR#

H_PECI_R

VR_PROCHOT#

H_CPURST#_R

H_PM_SYNC_R

VCCPWRGOOD_1_R

VCCPWRGD_0_R

PLT_RST#_R

+V1.1S_VTT

R187

49.9,1%

R0402

R548 68 R0402

ns

R549 68 R0402

ns

R182 0 R0402R182 0 R0402

R180 0 R0402R180 0 R0402

PM_DRAM_PWRGD

H_PWRGD_XDP_R

1.5K,1%

R181

R0402

R433 0 R0402R433 0 R0402

H_PECI{27}

+V1.1S_VTT

THERMTRIP#{27,38}

+V1.1S_VTT

C C

+V1.1S_VTT

R212

ns

1K,1%

R0402

B B

PM_DRAM_PWRGD

H_PM_SYNC{24}

VCCPWRGD_0{27}

PM_DRAM_PWRGD{24}

CPU_VTT_PWG{43}

BUF_PLT_RST#{17,26,38,39,40,41,43,44}

+V1.5

R105

1.21K,1%

R101

3.3K

U2B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

R198

49.9,1%

R0402

MISC THERMAL

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

Processor Compensation Signals

H_COMP1 H_COMP0

R543

R544

49.9,1%

R0402

R543

20,1%

r0402

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

H_COMP3 H_COMP2

R542

R542 20,1%

20,1%

r0402

BCLK_CPU_P_R

A16

BCLK_CPU_N_R

B16

BCLK_ITP_P

AR30

BCLK_ITP_N

AT30

CLK_EXP_P_R

E16

CLK_EXP_N_R

D16

CLK_DP_P_R

A18

CLK_DP_N_R

A17

F6 AL1

AM1 AN1

AN15 AP15

AT28 AP27

AN28

TCK

AP28

TMS

AT27 AT29

TDI

AR27

TDO

AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PM_EXT_TS#0 PM_EXT_TS#1

XDP_REQ

TCK TMS TRST#

TDI TDO TDI_M TDO_M

TDI_M

TDO_M

Layout Note: Place close to CPU

R520 0 R0402R520 0 R0402 R522 0 R0402R522 0 R0402

R528 0 R0402R528 0 R0402 R524 0 R0402R524 0 R0402

R539 0 R0402

R539 0 R0402 R531 0 R0402

R531 0 R0402

ns

ns ns

ns

T24nsT24

T18nsT18 T20nsT20 T23nsT23 T25nsT25 T26nsT26 T19nsT19 T22nsT22 T21nsT21

SM_RCOMP_2 SM_RCOMP_1 SM_RCOMP_0

100,1%

R0402

T59nsT59 T58nsT58

DDR3_DRAMRST# {15,16}

TDO

TMS

TCK

R559

49.9,1%

ns

R0402

TDI

ns ns

XDP_REQ

ns ns ns ns ns ns

R217

R217 0

0

R0402

ns

DDR3 Compensation Signals

R439

R438

24.9,1%

R0402

BCLK_CPU_P {27} BCLK_CPU_N {27}

ns ns

CLK_EXP_P {23} CLK_EXP_N {23}

49.9,1%

R0402

R566

ns

R216

49.9,1%

R0402 ns

49.9,1%

R0402

R218

49.9,1%

49.9,1% R568

R568

R0402 ns

49.9,1%

49.9,1% R214

R214

R0402 ns

R437

R437 130,1%

130,1%

R0402

+V1.1S_VTT

nsR218

ns

R634

R634 1K

1K

R0402

PM_EXT_TS#0

PM_EXT_TS#1

+V3.3S

R632

R632 10K

10K

R0402

1

Q30

Q30 MMBT3904-F

MMBT3904-F

SOT23

2 3

R0402

R123

R123 10K

10K

+V1.1S_VTT

R133

R133 10K

10K

+V1.1S_VTT

R636

R636 1K

1K

R0402

Q9

+V1.1S_VTT

Q8

MMBT3904-FSOT23

ns

23

+V1.1S_VTT

1

MMBT3904-FSOT23

ns

R129

R129 1K,1%

1K,1%

R0402

ns

1

23

Q31

Q31 MMBT3904-F

MMBT3904-F

SOT23

1

VR_PROCHOT#

R139

R139 1K,1%

1K,1%

R0402

ns

23

+V3.3S

R130

R130 10K

10K

R0402

ns

R118

R118 10K

10K

R0402

ns

EC_PROCHOT# {43}

R635

R635 1K

1K

R0402

VR_PROCHOT# {55}

+V3.3S

+V1.1S_VTT+V1.1S_VTT

Voltage Level?

DIM_EXTTS#0 {16}

Voltage Level?

DIM_EXTTS#1 {15}

目前我们用的内存端没有做过温的功能。

CPU_VTT_PWG

R344

R344 750 OHM

750 OHM

R0402

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent Arrandule

Arrandule

C46

1

A

859Friday, November 27, 2009

A

of

5

U2C

D D

MA_DATA[63:0]{16}

C C

MA_A_BS0{16} MA_A_BS1{16}

B B

MA_A_BS2{16}

MA_A_CAS#{16} MA_A_RAS#{16}

MA_A_WE#{16}

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

AK12

AK11

AM10 AR11

AT11 AP12 AM12 AN12 AM13 AT14 AT12

AR14 AP14

AJ10 AL10

AL11

AL13

A10

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39] SA_DQ[40]

AJ9

SA_DQ[41] SA_DQ[42] SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45] SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

4

AA6

SA_CK[0]

AA7

SA_CK#[0]

P7

SA_CKE[0]

Y6

SA_CK[1]

Y5

SA_CK#[1]

P6

SA_CKE[1]

AE2

SA_CS#[0]

AE8

SA_CS#[1]

AD8

SA_ODT[0]

AF9

SA_ODT[1]

MA_DM0

B9

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

MA_DM1

D7

MA_DM2

H7

MA_DM3

M7

MA_DM4

AG6

MA_DM5

AM7

MA_DM6

AN10

MA_DM7

AN13

MA_DQS#0

C9

MA_DQS#1

F8

MA_DQS#2

J9

MA_DQS#3

N9

MA_DQS#4

AH7

MA_DQS#5

AK9

MA_DQS#6

AP11

MA_DQS#7

AT13

MA_DQS0

C8

MA_DQS1

F9

MA_DQS2

H9

MA_DQS3

M9

MA_DQS4

AH8

MA_DQS5

AK10

MA_DQS6

AN11

MA_DQS7

AR13

MA_A_A0

Y3

MA_A_A1

W1

MA_A_A2

AA8

MA_A_A3

AA3

MA_A_A4

V1

MA_A_A5

AA9

MA_A_A6

V8

MA_A_A7

T1

MA_A_A8

Y9

MA_A_A9

U6

MA_A_A10

AD4

MA_A_A11

T2

MA_A_A12

U3

MA_A_A13

AG8

MA_A_A14

T3

MA_A_A15 MB_B_A14

V9

M_CLK_DDR0 {16}

M_CLK_DDR#0 {16} M_CKE0 {16}

M_CLK_DDR1 {16}

M_CLK_DDR#1 {16} M_CKE1 {16}

M_CS#0 {16} M_CS#1 {16}

M_ODT0 {16} M_ODT1 {16}

MA_DM[7:0] {16}

MA_DQS#[7:0] {16}

MA_A_A[15:0] {16}

MA_DQS[7:0] {16}

3

U2D

MB_DATA[63:0]{15}

MB_B_BS0{15} MB_B_BS1{15} MB_B_BS2{15}

MB_B_CAS#{15} MB_B_RAS#{15}

MB_B_WE#{15}

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

AR10 AT10

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61] SB_DQ[62] SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

2

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

MB_DM0

D4

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

MB_DM1

E1

MB_DM2

H3

MB_DM3

K1

MB_DM4

AH1

MB_DM5

AL2

MB_DM6

AR4

MB_DM7

AT8

MB_DQS#0

D5

MB_DQS#1

F4

MB_DQS#2

J4

MB_DQS#3

L4

MB_DQS#4

AH2

MB_DQS#5

AL4

MB_DQS#6

AR5

MB_DQS#7

AR8

MB_DQS0

C5

MB_DQS1

E3

MB_DQS2

H4

MB_DQS3

M5

MB_DQS4

AG2

MB_DQS5

AL5

MB_DQS6

AP5

MB_DQS7

AR7

MB_B_A0

U5

MB_B_A1

V2

MB_B_A2

T5

MB_B_A3

V3

MB_B_A4

R1

MB_B_A5

T8

MB_B_A6

R2

MB_B_A7

R6

MB_B_A8

R4

MB_B_A9

R5

MB_B_A10

AB5

MB_B_A11

P3

MB_B_A12

R3

MB_B_A13

AF7 P5

MB_B_A15

N1

M_CLK_DDR2 {15}

M_CLK_DDR#2 {15} M_CKE2 {15}

M_CLK_DDR3 {15}

M_CLK_DDR#3 {15} M_CKE3 {15}

M_CS#2 {15} M_CS#3 {15}

M_ODT2 {15} M_ODT3 {15}

MB_DM[7:0] {15}

MB_DQS#[7:0] {15}

MB_DQS[7:0] {15}

MB_B_A[15:0] {15}

1

IC,AUB_CFD_rPGA,R1P0

S_Bot

A A

5

4

3

IC,AUB_CFD_rPGA,R1P0

S_Bot

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

bent Arrandule

Arrandule

C46

1

A

959Friday, November 27, 2009

A

of

5

U2F

+VCC_CORE +V1.1S_VTT

4

3

2

+VCC_CORE {55} +V1.1S_VTT {8,11,27,28,29,38,50,51,55}

1

D D

C C

B B

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

PROC_DPRSLPVR

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

PSI#

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

VTT_SELECT_R

G15

Vcore_IMON_R

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

TP_VTT_SENSE

B15

TP_VSS_SENSE_VTT

A15

R5800R580 0

R1930R193 0

ns

C362

C362 10uF/6.3V,X5R

10uF/6.3V,X5R

C186

C186 10uF/6.3V,X5R

10uF/6.3V,X5R

C360

C360 10uF/6.3V,X5R

10uF/6.3V,X5R

Vcore_IMON {55}

R5810R581 R5820R582

0 0

ICTPns

T15

ICTP

T14

C363

C363 10uF/6.3V,X5R

10uF/6.3V,X5R

C388

C388 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.1S_VTT

C361

C361 10uF/6.3V,X5R

10uF/6.3V,X5R

PM_PSI# {55}

H_VID0 {55} H_VID1 {55} H_VID2 {55} H_VID3 {55} H_VID4 {55} H_VID5 {55} H_VID6 {55} PM_DPRSLPVR {55}

VTT_SELECT {50}

+VCC_CORE

R589

R589 100,1%

100,1%

R0402

VCCSENSE {55} VSSSENSE {55}

R590

R590 100,1%

100,1%

R0402

C364

10uF/6.3V,X5R

C145

10uF/6.3V,X5R

C365

10uF/6.3V,X5R

C146

10uF/6.3V,X5R

C380

C380 10uF/6.3V,X5R

10uF/6.3V,X5R

C147

0.22uF/10V,X7R

C170

10uF/6.3V,X5R

C373

10uF/6.3V,X5R

C171

C171 10uF/6.3V,X5R

10uF/6.3V,X5R

C368

0.01uF/25V,X7R

C379

C379 10uF/6.3V,X5R

10uF/6.3V,X5R

C384

C384 10uF/6.3V,X5R

10uF/6.3V,X5R

C381

C381 10uF/6.3V,X5R

10uF/6.3V,X5R

C174

C174 10uF/6.3V,X5R

10uF/6.3V,X5R

C192

C192 10uF/6.3V,X5R

10uF/6.3V,X5R

C385

C385 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.1S_VTT +V1.1S_VTT

R575

ns

1K

R0402

PM_PSI# PM_DPRSLPVR

R0402

R576

R576 1K

1K

R0402

Clarksfield 1.1v Arrandale 1.05v

C189

C175

C175 10uF/6.3V,X5R

10uF/6.3V,X5R

C172

C172 10uF/6.3V,X5R

10uF/6.3V,X5R

C377

C377 10uF/6.3V,X5R

10uF/6.3V,X5R

C173

C173 10uF/6.3V,X5R

10uF/6.3V,X5R

C376

C376 10uF/6.3V,X5R

10uF/6.3V,X5R

C209

C209 10uF/6.3V,X5R

10uF/6.3V,X5R

C176

C176 10uF/6.3V,X5R

10uF/6.3V,X5R

C378

C378 10uF/6.3V,X5R

10uF/6.3V,X5R

C199

C199 1uF/10V,X7R

1uF/10V,X7R

C169

C169 10uF/6.3V,X5R

10uF/6.3V,X5R

C375

C375 10uF/6.3V,X5R

10uF/6.3V,X5R

C198

C198 1uF/10V,X7R

1uF/10V,X7R

C374

C374 10uF/6.3V,X5R

10uF/6.3V,X5R

C197

0.22uF/10V,X7R

C190

C190 10uF/6.3V,X5R

10uF/6.3V,X5R

C387

C387 10uF/6.3V,X5R

10uF/6.3V,X5R

R221

R221 1K

1K

R0402

R220

ns

1K

R0402

C191

C191 10uF/6.3V,X5R

10uF/6.3V,X5R

C386

C386 10uF/6.3V,X5R

10uF/6.3V,X5R

C196

0.22uF/10V,X7R

C188

10uF/6.3V,X5R

C383

C383 10uF/6.3V,X5R

10uF/6.3V,X5R

C212

0.01uF/25V,X7R

+VCC_CORE

C187

C187 10uF/6.3V,X5R

10uF/6.3V,X5R

C382

10uF/6.3V,X5R

C210

0.01uF/25V,X7R

C211

C211 10uF/6.3V,X5R

10uF/6.3V,X5R

IC,AUB_CFD_rPGA,R1P0

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent Arrandule

Arrandule

C46

1

A

10 59Friday, November 27, 2009

A

of

5

D D

4

3

2

+VGFX {51}

+V1.1S_VTT {8,10,27,28,29,38,50,51,55}

+V1.5 {8,15,16,49,56,57}

+V1.8S {26,28,29,31,49,56,57}

1

+VGFX

C184

C161

C161 10uF/6.3V,X5R

10uF/6.3V,X5R

C148

C148 10uF/6.3V,X5R

10uF/6.3V,X5R

C184 10uF/6.3V,X5R

10uF/6.3V,X5R

C150

C150 10uF/6.3V,X5R

10uF/6.3V,X5R

C162

C371

0.01uF/25V,X7R

C151

C151 10uF/6.3V,X5R

10uF/6.3V,X5R

C162 10uF/6.3V,X5R

10uF/6.3V,X5R

C149

C149 10uF/6.3V,X5R

10uF/6.3V,X5R

C181

C181 10uF/6.3V,X5R

10uF/6.3V,X5R

C C

C160

0.22uF/10V,X7R

+V1.1S_VTT

B B

C183 10uF/6.3V,X5R

10uF/6.3V,X5R

C154

C154 10uF/6.3V,X5R

10uF/6.3V,X5R

C372

C372 10uF/6.3V,X5R

10uF/6.3V,X5R

C183

C152

C152 10uF/6.3V,X5R

10uF/6.3V,X5R

AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16

AL21 AL19 AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

U2G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

GRAPHICS

FDI PEG & DMI

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_DPRSLPVR

GRAPHICS VIDs

POWER

DDR3 - 1.5V RAILS

1.1V1.8V

VAXG_SENSE

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

VGFXVCCSEN {51} VGFXVSSSEN {51}

GFXVR_VID_0 {51} GFXVR_VID_1 {51} GFXVR_VID_2 {51} GFXVR_VID_3 {51} GFXVR_VID_4 {51} GFXVR_VID_5 {51} GFXVR_VID_6 {51}

GFXVR_DPRSLPVR {51}

VGFX_IMON {51}

C106

C110

10uF/6.3V,X5R

C358

C358 10uF/6.3V,X5R

10uF/6.3V,X5R

VCCPLL

C108

C108 1uF/10V,X7R

1uF/10V,X7R

C359

C359 10uF/6.3V,X5R

10uF/6.3V,X5R

C107

1uF/10V,X7R

C185

C185 10uF/6.3V,X5R

10uF/6.3V,X5R

GFXVR_EN {51}

R545

4.7K

R0402

C111

C111 1uF/10V,X7R

1uF/10V,X7R

+V1.1S_VTT

C153

C153 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.5

C109

C109 1uF/10V,X7R

1uF/10V,X7R

IC,AUB_CFD_rPGA,R1P0

+V1.8S

VCCPLL

C200

C200 1uF/10V,X7R

1uF/10V,X7R

A A

5

4

C201

C201 1uF/10V,X7R

1uF/10V,X7R

C195

C195 1uF/10V,X7R

1uF/10V,X7R

3

FB8

1 2

300ohm@100MHz,1.5A

C193

10uF/6.3V,X5R

FB0805FB8

FB0805

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

bent Arrandule

Arrandule

C46

1

A

11 59Friday, November 27, 2009

A

of

5

U2H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

A A

VSS8

AR17

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

IC,AUB_CFD_rPGA,R1P0

S_Bot

5

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

4

3

U2I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

IC,AUB_CFD_rPGA,R1P0

S_Bot

3

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

2

Page Name

Page Name Size

Size

Project Name Rev

B

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

1

TOPSTAR TECHNOLOGY

bent

bent Arrandule

Arrandule

C46

12 59Friday, November 27, 2009

1

A

of

5

U2E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

D D

ns

R209 0

VREFA_DDR3{16}

VREFB_DDR3{15}

R572

R0402

3.01K,1%

C C

B B

A A

R209 0 R204 0

R204 0

R570

R0402

3.01K,1%

3.01K,1% R573

R573

3.01K,1%

R0402

ns

never pull down for switchable graphic

5

VREF_CH_A_DIMM VREF_CH_B_DIMM

ns

CFG0

CFG3 CFG4

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0

4

AJ13

RSVD32

AJ12

RSVD33

AH25

RSVD34

AK26

RSVD35

AL26

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

KEY RSVD62 RSVD63 RSVD64 RSVD65

VSS

AR2 AJ26

AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD_TP_59 RSVD_TP_60

RESERVED

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

4

3

BRACKET

CPU_BRACKET

R579 0 R0402R579 0 R0402

3

H11

CPU_HOLE

11223344556677889

2

H12

CPU_HOLE

ns

11223344556677889

9

ns

9

2

H13

CPU_HOLE

ns

11223344556677889

ns

9

BRACKET1_Mylar

Mylar

Page Name

Page Name Size

Size

Project Name Rev

B

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

H14

CPU_HOLE

ns

11223344556677889

ns

9

TOPSTAR TECHNOLOGY

bent

bent Arrandule

Arrandule

C46

13 59Friday, November 27, 2009

1

A

of

5

4

3

2

1

PCH Strapping

Name

SPKR

D D

INIT3_3V#

Reboot option at power-up

Internal pull-up. Leave as "No Connect"

GNT3#/GPIO55

INTVRMEN

GNT0# GNT1#

GNT2#/ GPIO53

SPI_MOSI

NV_ALE

NV_CLE

HDA_DOCK_EN

C C

#/GPIO33

HDA_SDO

HDA_SYNC

GPIO15

GPIO8

GPIO27

Integrated VRM Mode

Default(SPI): Leave both GNT0#and GNT1# floating. Boot: From PCI: Connect GNT1# to ground with 1k resistor,leave GNT0# Floating From LPC:Connect both GNT0# and GNT1#to ground with 1k resistor

Intel Anti-Theft Technology

DMI termination voltage

Flash Descriptor Security

Weak internal pull-down

Intel ME Crypto TLS cipher suite With

Weak internal pull-up

Default: floating

01Description

Default Mode No Reboot Mode

Top Block Swap Mode

with TCO Disabled

Default Mode

EnabledDisabled

Configures DMI for ESI

Default Mode

Disabled Enabled

EnabledDisabled

/

Security measure enabled

Weak internal pull-down Weak internal pull-down

Weak internal pull-up

1.Security measure Overridden

2.Sampled on the rising edge of PWROK,disables Intel ME& its freatures

/

No confidentiality Confidentiality

Weak internal pull-up Disables the internal VccVRM

/

Enables the internal VccVRM

Processor Strapping

Description

CFG[4]

CFG[3]

CFG[0]

Embedded DisplayPort Presence

PCI-E Static Lane Reversal

PIC-Express Configuration Select

An external Display Port device is connected to the Embedded Display Port

Lane Numbers Resersed 15->0.14->1, ...

Bifurcation enable Single PCIE Graphics

Note: Default value for each bit is 1 unless specified otherless

10

No Physical Display Port attached to Embedded Displayport

Normal Operation

Name Pin Attr Description GPIO0 +V3.3S I/O GPIO1 +V3.3S I/O GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

B B

A A

GPIO9 GPIO10

GPIO11 GPIO12 GPIO13 GPIO14 GPIO15

GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27

GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39

GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45

5

10Kohm pull up to V3.3S EXTSMI# Reserve for EC,10k to V3.3S

+V3.3S I/OD

8.2Kohm pull up to V3.3S

+V3.3S I/OD

8.2Kohm pull up to V3.3S

+V3.3S I/OD

8.2Kohm pull up to V3.3S

+V3.3S I/OD

As LVDS_DDC_SEL for DDC select

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

As EC_RUNTIME_SCI# link to EC,10K to V3.3S 10Kohm pull up to V3.3AL

+V3.3A I/O

As USB_OC#5 for USB board

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O +V3.3A I/O

NC

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

1Kohm pull up to V3.3AL

+V3.3S I/O

10K to GND,reserve 10K to V3.3S for debug

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

MiniPCIE_REQ# Reserve,10k to V3.3S

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

minicard_CLKREQ# Reserve,10k to V3.3S 10Kohm pull up to V3.3S

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

Reserve 10Kohm pull up to V3.3S for debug

+V3.3S I/O

10Kohm pull up to V3.3AL and 10K to GND

+V3.3A I/O

EXPCARD_CLKREQ# Reserve,100k to V3.3AL

+V3.3A I/O +V3.3A I/O

8.2Kohm pull up to V3.3AL

+V3.3A I/O

Reserve 10Kohm pull down to GND for debug

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

NC

+V3.3A I/O

As ALW_ACK link to EC and 10K to V3.3AL

+V3.3A I/O

As AC_IN_PCH link to EC

+V3.3S I/O

10Kohm pull up to V3.3S

4.7Kohm pull down to GND

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

10Kohm pull down to GND

+V3.3S I/O +V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

10Kohm pull down to GND for BIOS ver

+V3.3S I/O

10Kohm pull down to GND for BIOS ver

+V3.3S I/O

10Kohm pull down to GND for BIOS ver

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

As USB_OC#2 for USB board

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

8.2Kohm pull up to V3.3AL

+V3.3A I/O

As TP(test point)

Name Pin Attr Description GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66 GPIO67 GPIO72 GPIO73 GPIO74 GPIO75

+V3.3A I/O +V3.3A I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O

As TP(test point) As PCIE_CLKREQ for N10,10K to GND and 10K to V3.3GPU 10Kohm pull up to V3.3S 10Kohm pull up to V3.3S

8.2Kohm pull up to V3.3S Reserve 1K pull down to GND

8.2Kohm pull up to V3.3S As LVDS_BLT_SEL for BLT select

8.2Kohm pull up to V3.3S Reserve 1K pull down to GND

8.2Kohm pull up to V3.3AL 10Kohm pull up to V3.3AL As SML1CLK and 2.2K to V3.3AL 10Kohm pull up to V3.3AL 10Kohm pull up to V3.3AL As PM_SUS_STAT# link to EC and 1k to V3.3AL As TP As TP NC NC NC As CLK_CR_48M for IT1337E output 48M clock As BAT_LOW# link to EC and 10K to V3.3AL 10Kohm pull down to GND 10Kohm pull up to V3.3AL As SML1DATA and 2.2K to V3.3AL

4

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

bent black

black

C46

A

14 59Friday, November 27, 2009

1

A

of

5

4

3

2

+V3.3S {6,8,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5 {8,11,16,49,56,57} +V0.75S {16,49,56}

1

D D

MB_B_A[15:0]{9}

+V1.5

C27

C47

C0805

2.2UF/10V,X7R

0.1UF/25V,Y5V

+V1.5

C25

C0402

0.1UF/25V,Y5V

C21

C0805

2.2UF/10V,X7R

ns

10UF/6.3V,X5R

0.1UF/25V,Y5V

C C

Layout note:

B B

ns

C0402

2.2UF/10V,X7R

+V1.5

C46

C46 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C40

C0402

2.2UF/10V,X7R

0.1UF/25V,Y5V

电容靠近

C77

C0805

C20

C0805

C27

C78

C47

C44

C75

C0402

C0805

0.1UF/25V,Y5V

2.2UF/10V,X7R

C48

C48 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C19

ns

C0805

0.1UF/25V,Y5V

2.2UF/10V,X7R

DDR slot VDD PIN

0.1UF/25V,Y5V

C76

ns

C0805

2.2UF/10V,X7R

C38

ns

C0402

2.2UF/10V,X7R

+V3.3S

C30

C0402

C34

C45

C0805

C0402

0.1UF/25V,Y5V

C35

C39

ns

C0805

2.2UF/10V,X7R

Note: SO-DIMM1 SPD Address is 0xA4

C31

2.2UF/10V,X7R

C0805

close to DDR pin199

M_CLK_DDR2{9} M_CLK_DDR#2{9} M_CLK_DDR3{9} M_CLK_DDR#3{9}

MB_DQS[7:0]{9}

VREFB_DDR3

C28

0.1UF/25V,Y5V

C0402

close to DDR pin1

DDR3_DRAMRST#{8,16}

MB_B_BS0{9} MB_B_BS1{9} MB_B_BS2{9}

M_CS#2{9} M_CS#3{9}

MB_DM[7:0]{9}

MB_B_WE#{9} MB_B_CAS#{9} MB_B_RAS#{9}

M_CKE2{9} M_CKE3{9}

M_ODT2{9} M_ODT3{9}

SMB_DATA_S{6,16,23,40,41} SMB_CLK_S{6,16,23,40,41}

R46 10K R0402R46 10K R0402 R49 10K R0402R49 10K R0402

DIM_EXTTS#1{8}

C29

2.2UF/10V,X7R

C0805

MB_B_A0 MB_B_A1 MB_B_A2 MB_B_A3 MB_B_A4 MB_B_A5 MB_B_A6 MB_B_A7 MB_B_A8 MB_B_A9 MB_B_A10 MB_B_A11 MB_B_A12 MB_B_A13 MB_B_A14 MB_B_A15

MB_DQS0 MB_DQS1 MB_DQS2 MB_DQS3 MB_DQS4 MB_DQS5 MB_DQS6 MB_DQS7

VREFB_CA

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

+V1.5+V0.75S

203

204

VTT1

VTT2

VDD175VDD276VDD381VDD482VDD587VDD688VDD793VDD894VDD9

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

CS0

121

CS1

11

DQM0

28

DQM1

46

DQM2

63

DQM3

136

DQM4

153

DQM5

170

DQM6

187

DQM7

113

WE

115

CAS

110

RAS

73

CKE0

74

CKE1

101

CK0

103

CK0

102

CK1

104

CK1

116

ODT0

120

ODT1

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

200

SDA

202

SCL

197

SA0

201

SA1

199

VDDSPD

1

VREF_DQ

126

VREF_CA

198

EVENT#

30

RESET#

77

NC1

122

NC2

125

NCTEST

DDR3_SODIMM204_0

99

100

105

106

111

112

VDD10

VDD11

VDD12

VDD13

VSS23VSS38VSS49VSS513VSS614VSS719VSS820VSS925VSS1026VSS1131VSS1232VSS1337VSS1438VSS1543VSS1644VSS1748VSS1849VSS1954VSS2055VSS2160VSS2261VSS2365VSS2466VSS2571VSS2672VSS27

VSS1

2

VDD14

151

145

150

155

VDD16

156

123

124

VSS36

VSS34

VSS35

VSS37

VDD17

VDD18

117

118

VDD15

161

162

167

168

172

173

178

179

184

185

189

190

195

196

DIMM2

MB_DATA0

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

VSS29

VSS30

VSS28

127

133

134

128

5

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

D0

MB_DATA1

7

D1

MB_DATA2

15

D2

MB_DATA3

17

D3

MB_DATA4

4

D4

MB_DATA5

6

D5

MB_DATA6

16

D6

MB_DATA7

18

D7

MB_DATA8

21

D8

MB_DATA9

23

D9

MB_DATA10

33

D10

MB_DATA11

35

D11

MB_DATA12

22

D12

MB_DATA13

24

D13

MB_DATA14

34

D14

MB_DATA15

36

D15

MB_DATA16

39

D16

MB_DATA17

41

D17

MB_DATA18

51

D18

MB_DATA19

53

D19

MB_DATA20

40

D20

MB_DATA21

42

D21

MB_DATA22

50

D22

MB_DATA23

52

D23

MB_DATA24

57

D24

MB_DATA25

59

D25

MB_DATA26

67

D26

MB_DATA27

69

D27

MB_DATA28

56

D28

MB_DATA29

58

D29

MB_DATA30

68

D30

MB_DATA31

70

D31

MB_DATA32

129

D32

MB_DATA33

131

D33

MB_DATA34

141

D34

MB_DATA35

143

D35

MB_DATA36

130

D36

MB_DATA37

132

D37

MB_DATA38

140

D38

MB_DATA39

142

D39

MB_DATA40

147

D40

MB_DATA41

149

D41

MB_DATA42

157

D42

MB_DATA43

159

D43

MB_DATA44

146

D44

MB_DATA45

148

D45

MB_DATA46

158

D46

MB_DATA47

160

D47

MB_DATA48

163

D48

MB_DATA49

165

D49

MB_DATA50

175

D50

MB_DATA51

177

D51

MB_DATA52

164

D52

MB_DATA53

166

D53

MB_DATA54

174

D54

MB_DATA55

176

D55

MB_DATA56

181

D56

MB_DATA57

183

D57

MB_DATA58

191

D58

MB_DATA59

193

D59

MB_DATA60

180

D60

MB_DATA61

182

D61

MB_DATA62

192

D62

MB_DATA63

194

D63

MB_DQS#0

10

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

VSS31

VSS32

VSS33

GND1

138

139

144

205

MB_DQS#1

27

MB_DQS#2

45

MB_DQS#3

62

MB_DQS#4

135

MB_DQS#5

152

MB_DQS#6

169

MB_DQS#7

186

GND2

206

MB_DATA[63:0] {9}

MB_DQS#[7:0] {9}

+V1.5 +V1.5

R50

R48

R48 1K,1%

1K,1%

R0402

VREFB_DDR3

R47

R47 1K,1%

1K,1%

R0402

A A

5

R0402

VREFB_DDR3 {13}

4

R50 1K,1%

1K,1%

R0402

R51

R51 1K,1%

1K,1%

R0402

C53

0.1UF/25V,Y5V

C0402

VREFB_CA

C43

2.2UF/10V,X7R

C0805

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

bent DDR3 SODIMM1

DDR3 SODIMM1

C46

1

A

15 59Friday, November 27, 2009

A

of

5

D D

C C

+V3.3S

0.1UF/25V,Y5V

0.1UF/25V,Y5V C42

C42

C0402

B B

C41

2.2UF/10V,X7R

C0805

MA_DM[7:0]{9}

MA_A_CAS#{9} MA_A_RAS#{9}

M_CLK_DDR0{9} M_CLK_DDR#0{9} M_CLK_DDR1{9} M_CLK_DDR#1{9}

MA_DQS[7:0]{9}

SMB_DATA_S{6,15,23,40,41} SMB_CLK_S{6,15,23,40,41}

VREFA_DDR3

MA_A_A[15:0]{9}

MA_A_BS0{9} MA_A_BS1{9} MA_A_BS2{9}

M_CS#0{9} M_CS#1{9}

MA_A_WE#{9}

M_CKE0{9} M_CKE1{9}

M_ODT0{9} M_ODT1{9}

R54 0R54 0

0.1UF/25V,Y5V

C52

C0402

MA_DQS0 MA_DQS1 MA_DQS2 MA_DQS3 MA_DQS4 MA_DQS5 MA_DQS6 MA_DQS7

close to DDR pin

DIM_EXTTS#0{8}

DDR3_DRAMRST#{8,15}

+V3.3S {6,8,15,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5 {8,11,15,49,56,57} +V0.75S {15,49,56}

MA_A_A0

98

MA_A_A1

97

MA_A_A2

96

MA_A_A3

95

MA_A_A4

92

MA_A_A5

91

MA_A_A6

90

MA_A_A7

86

MA_A_A8

89

MA_A_A9

85

MA_A_A10

107

MA_A_A11

84

MA_A_A12

83

MA_A_A13

119

MA_A_A14

80

MA_A_A15

78

109 108

79

114 121

MA_DM0

11

MA_DM1

28

MA_DM2

46

MA_DM3

63

MA_DM4

136

MA_DM5

153

MA_DM6

170

MA_DM7

187 113

115 110

73 74

101 103 102 104

116 120

12 29 47

64 137 154 171 188

200

VREFA_CA

202 197

201 199

1

126 198

30

77 122 125

DDR3_SODIMM204_0

R65 10K R0402R65 10K R0402 R64 10K R0402R64 10K R0402

C50

2.2UF/10V,X7R

C0805

4

+V1.5+V0.75S

203

204

VTT1

VTT2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15

BA0 BA1 BA2

CS0 CS1

DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7

WE CAS RAS

CKE0 CKE1

CK0 CK0 CK1 CK1

ODT0 ODT1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

SDA SCL

SA0 SA1

VDDSPD VREF_DQ

VREF_CA EVENT#

RESET# NC1

NC2 NCTEST

99

100

105

106

111

112

117

VDD175VDD276VDD381VDD482VDD587VDD688VDD793VDD894VDD9

VSS1

2

VDD10

VDD11

VDD12

VDD13

VDD14

VSS23VSS38VSS49VSS513VSS614VSS719VSS820VSS925VSS1026VSS1131VSS1232VSS1337VSS1438VSS1543VSS1644VSS1748VSS1849VSS1954VSS2055VSS2160VSS2261VSS2365VSS2466VSS2571VSS2672VSS27

VDD15

3

+V1.5

12

C96

151

145

150

155

156

161

162

167

168

172

173

178

179

184

185

189

190

195

118

123

124

VSS36

VSS34

VSS35

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VDD16

VDD17

VDD18

VSS43

VSS28

127

133

128

196

DIMM1

MA_DATA0

VSS44

VSS45

VSS29

VSS30

134

5

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

D0

MA_DATA1

7

D1

MA_DATA2

15

D2

MA_DATA3

17

D3

MA_DATA4

4

D4

MA_DATA5

6

D5

MA_DATA6

16

D6

MA_DATA7

18

D7

MA_DATA8

21

D8

MA_DATA9

23

D9

MA_DATA10

33

D10

MA_DATA11

35

D11

MA_DATA12

22

D12

MA_DATA13

24

D13

MA_DATA14

34

D14

MA_DATA15

36

D15

MA_DATA16

39

D16

MA_DATA17

41

D17

MA_DATA18

51

D18

MA_DATA19

53

D19

MA_DATA20

40

D20

MA_DATA21

42

D21

MA_DATA22

50

D22

MA_DATA23

52

D23

MA_DATA24

57

D24

MA_DATA25

59

D25

MA_DATA26

67

D26

MA_DATA27

69

D27

MA_DATA28

56

D28

MA_DATA29

58

D29

MA_DATA30

68

D30

MA_DATA31

70

D31

MA_DATA32

129

D32

MA_DATA33

131

D33

MA_DATA34

141

D34

MA_DATA35

143

D35

MA_DATA36

130

D36

MA_DATA37

132

D37

MA_DATA38

140

D38

MA_DATA39

142

D39

MA_DATA40

147

D40

MA_DATA41

149

D41

MA_DATA42

157

D42

MA_DATA43

159

D43

MA_DATA44

146

D44

MA_DATA45

148

D45

MA_DATA46

158

D46

MA_DATA47

160

D47

MA_DATA48

163

D48

MA_DATA49

165

D49

MA_DATA50

175

D50

MA_DATA51

177

D51

MA_DATA52

164

D52

MA_DATA53

166

D53

MA_DATA54

174

D54

MA_DATA55

176

D55

MA_DATA56

181

D56

MA_DATA57

183

D57

MA_DATA58

191

D58

MA_DATA59

193

D59

MA_DATA60

180

D60

MA_DATA61

182

D61

MA_DATA62

192

D62

MA_DATA63

194

D63

MA_DQS#0

10

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

VSS31

VSS32

VSS33

GND1

138

139

144

205

206

GND2

MA_DQS#1

27

MA_DQS#2

45

MA_DQS#3

62

MA_DQS#4

135

MA_DQS#5

152

MA_DQS#6

169

MA_DQS#7

186

MA_DATA[63:0] {9}

MA_DQS#[7:0] {9}

C96

1

+

ns

CT7343_19

220uF/2.5V,POSCAP

+V1.5

C208

10uF/6.3V,X5R

Layout note:

+V0.75S

C51

1uF/10V,X7R

C37

C0402

0.1UF/25V,Y5V

2.2UF/10V,X7R

C23

C0402

0.1UF/25V,Y5V

2

C33

C417

ns

C0805

2.2UF/10V,X7R

0.1UF/25V,Y5V

C419

C0805

2.2UF/10V,X7R

电容靠近

DDR slot VDD PIN

C72

1uF/10V,X7R

C26

C0402

2.2UF/10V,X7R

C418

C418 10uF/6.3V,X5R

10uF/6.3V,X5R

2.2UF/10V,X7R

C32

C32 1uF/10V,X7R

1uF/10V,X7R

C22

C0805

0.1UF/25V,Y5V

C213

C0805

0.1UF/25V,Y5V

C36

C49

ns

C0402

C0805

2.2UF/10V,X7R

1, A minimum of 9 high frequency capacitors are recommended to be placed near each SO-DIMM of DDR2. 2, 2.2µF*5 per DIMM,0.1µF*4 per DIMM,330µF*1 per DIMM

C24

C0402

C18

C18 1uF/10V,X7R

1uF/10V,X7R

1

+V1.5

R52

R52 1K,1%

1K,1%

R0402

VREFA_DDR3

R53

R53 1K,1%

1K,1%

R0402

A A

5

VREFA_DDR3 {13}

+V1.5

R435

R435 1K,1%

1K,1%

R0402

R436

R436 1K,1%

1K,1%

R0402

C328

0.1UF/25V,Y5V

C0402

VREFA_CAVREFA_CA

4

C327

2.2UF/10V,X7R

C0805

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

bent DDR3 SODIMM0

DDR3 SODIMM0

C46

1

A

16 59Friday, November 27, 2009

A

of

5

4

3

+V3.3GPU {20,21,33,34,52,57} +VGA_CORE {52} +V1.05GPU {18,19,20,57}

2

1

GR53

GR53 10K

10K

S_Top

GPU_RST#

PM

+V3.3GPU

GR41

GR41 10K

10K

S_Bot

PCIE_CLKREQ

PM

GR16 0

+V3.3GPU

S_Top

ns

GC3

0.1uF/10V,X7R

53

GU2

S_Top

VCC

PEG_RXP15 PEG_RXN15

PEG_NV_RXP15 PEG_NV_RXN15

PEG_RXP14 PEG_RXN14

PEG_NV_RXP14 PEG_NV_RXN14

PEG_RXP13 PEG_RXN13

PEG_NV_RXP13 PEG_NV_RXN13

PEG_RXP12 PEG_RXN12

PEG_NV_RXP12 PEG_NV_RXN12

PEG_RXP11 PEG_RXN11

PEG_NV_RXP11 PEG_NV_RXN11

PEG_RXP10 PEG_RXN10

PEG_NV_RXP10 PEG_NV_RXN10

PEG_RXP9 PEG_RXN9

PEG_NV_RXP9 PEG_NV_RXN9

PEG_RXP8 PEG_RXN8

PEG_NV_RXP8 PEG_NV_RXN8

PEG_RXP7 PEG_RXN7

PEG_NV_RXP7 PEG_NV_RXN7

PEG_RXP6 PEG_RXN6

PEG_NV_RXP6 PEG_NV_RXN6

PEG_RXP5 PEG_RXN5

PEG_NV_RXP5 PEG_NV_RXN5

PEG_RXP4 PEG_RXN4

PEG_NV_RXP4 PEG_NV_RXN4

PEG_RXP3 PEG_RXN3

PEG_NV_RXP3 PEG_NV_RXN3

PEG_RXP2 PEG_RXN2

PEG_NV_RXP2 PEG_NV_RXN2

PEG_RXP1 PEG_RXN1

PEG_NV_RXP1 PEG_NV_RXN1

PEG_RXP0 PEG_RXN0

PEG_NV_RXP0 PEG_NV_RXN0

PCIE_CLKREQ{23} CLK_PCIE_N11M{23}

CLK_PCIE_N11M#{23}

1 2

GND

SN74AHC1G08DBV

ns

SN74AHC1G08DBV

ns

SOT23_5

SOT23_5 S_Top

S_Top

GC1500.1UF/10V,X7R

S_Bot

GC1000.1UF/10V,X7R

S_Top

GC1530.1UF/10V,X7R

S_Bot

GC1050.1UF/10V,X7R

S_Top

GC1570.1UF/10V,X7R

S_Bot

GC1100.1UF/10V,X7R

S_Top

GC1600.1UF/10V,X7R

S_Bot

GC1160.1UF/10V,X7R

S_Top

GC1660.1UF/10V,X7R

S_Bot

GC1200.1UF/10V,X7R

S_Top

GC1710.1UF/10V,X7R

S_Bot

GC1250.1UF/10V,X7R

S_Top

GC1740.1UF/10V,X7R

S_Bot

GC1290.1UF/10V,X7R

S_Top

GC1800.1UF/10V,X7R

S_Bot

GC1330.1UF/10V,X7R

S_Top

4

GC1490.1UF/10V,X7R

S_Bot

PM

GC97 0.1UF/10V,X7R

S_Top

PM

GC1520.1UF/10V,X7R

S_Bot

PM

GC1040.1UF/10V,X7R

S_Top

PM

GC1560.1UF/10V,X7R

S_Bot

PM

GC1080.1UF/10V,X7R

S_Top

PM

GC1610.1UF/10V,X7R

S_Bot

PM

GC1130.1UF/10V,X7R

S_Top

PM

GC1650.1UF/10V,X7R

S_Bot

PM

GC1190.1UF/10V,X7R

S_Top

PM

GC1700.1UF/10V,X7R

S_Bot

PM

GC1240.1UF/10V,X7R

S_Top

PM

GC1760.1UF/10V,X7R

S_Bot

PM

GC1280.1UF/10V,X7R

S_Top

PM

GC1790.1UF/10V,X7R

S_Bot

PM

GC1340.1UF/10V,X7R

S_Top

PM

EC_GPU_RST#{43}

BUF_PLT_RST#{8,26,38,39,40,41,43,44}

GR2 is used for test only, so it can be unstuff for cost saving.

GPU_RST#

GR42

GR42 100K

100K

S_Bot

PCIE_CLKREQ

GR20 200,1% R0402

ns

S_Top

PEG_NV_TXP15 PEG_NV_TXN15

PM

PEG_NV_TXP14 PEG_NV_TXN14

PM

PEG_NV_TXP13 PEG_NV_TXN13

PM

PEG_NV_TXP12 PEG_NV_TXN12

PM

PEG_NV_TXP11 PEG_NV_TXN11

PM

PEG_NV_TXP10 PEG_NV_TXN10

PM

PEG_NV_TXP9 PEG_NV_TXN9

PM

PEG_NV_TXP8 PEG_NV_TXN8

PM

PEG_NV_TXP7 PEG_NV_TXN7

PM

PEG_NV_TXP6 PEG_NV_TXN6

PM

PEG_NV_TXP5 PEG_NV_TXN5

PM

PEG_NV_TXP4 PEG_NV_TXN4

PM

PEG_NV_TXP3 PEG_NV_TXN3

PM

PEG_NV_TXP2 PEG_NV_TXN2

PM

PEG_NV_TXP1 PEG_NV_TXN1

PM

PEG_NV_TXP0 PEG_NV_TXN0

PM

CLOSE TO N10

AM16 AR13

AJ17 AJ18

AR16 AR17

AL17 AM17

AP17 AN17

AM18 AM19

AN19 AP19

AL19 AK19

AR19 AR20

AL20 AM20

AP20 AN20

AM21 AM22

AN22 AP22

AL22 AK22

AR22 AR23

AL23 AM23

AP23 AN23

AM24 AM25

AN25 AP25

AL25 AK25

AR25 AR26

AL26 AM26

AP26 AN26

AM27 AM28

AN28 AP28

AL28 AK28

AR28 AR29

AK29 AL29

AP29 AN29

AM29 AM30

AN31 AP31

AM31 AM32

AR31 AR32

AN32 AP32

AR34 AP34

U3A

PEX_RST# PEX_CLKREQ

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PEX_REFCLK PEX_REFCLK#

PEX_TX0 PEX_TX0#

PEX_RX0 PEX_RX0#

PEX_TX1 PEX_TX1#

PEX_RX1 PEX_RX1#

PEX_TX2 PEX_TX2#

PEX_RX2 PEX_RX2#

PEX_TX3 PEX_TX3#

PEX_RX3 PEX_RX3#

PEX_TX4 PEX_TX4#

PEX_RX4 PEX_RX4#

PEX_TX5 PEX_TX5#

PEX_RX5 PEX_RX5#

PEX_TX6 PEX_TX6#

PEX_RX6 PEX_RX6#

PEX_TX7 PEX_TX7#

PEX_RX7 PEX_RX7#

PEX_TX8 PEX_TX8#

PEX_RX8 PEX_RX8#

PEX_TX9 PEX_TX9#

PEX_RX9 PEX_RX9#

PEX_TX10 PEX_TX10#

PEX_RX10 PEX_RX10#

PEX_TX11 PEX_TX11#

PEX_RX11 PEX_RX11#

PEX_TX12 PEX_TX12#

PEX_RX12 PEX_RX12#

PEX_TX13 PEX_TX13#

PEX_RX13 PEX_RX13#

PEX_TX14 PEX_TX14#

PEX_RX14 PEX_RX14#

PEX_TX15 PEX_TX15#

PEX_RX15 PEX_RX15#

NB10_G128

S_Bot

PM

PCI_EXPRESS

PEX_IOVDD_01 PEX_IOVDD_02 PEX_IOVDD_03 PEX_IOVDD_04 PEX_IOVDD_05

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9

PEX_IOVDDQ_10

PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24 PEX_IOVDDQ_25

PEX_SVDD_3V3_1 PEX_SVDD_3V3_2

VDD_SENSE1 VDD_SENSE2

VDD_SENSE3 GND_SENSE1 GND_SENSE2 GND_SENSE3

PEX_PLLVDD

PEX_CAL_PU_GND/NC

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5

PEX_TERMP

TESTMODE

AK16 AK17 AK21 AK24 AK27

PEX_IOVDD+PEX_IOVDDQ:MAX:2200mA

AG11 AG12 AG13 AG15

0.1uF/10V,X7R

AG16 AG17

S_Top

AG18 AG22 AG23 AG24

AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16

A2

NC_1

AA4

NC_2

AB4

NC_3

AB7

NC_4

AC5

NC_5

AD6

NC_6

AF6

NC_7

AG6

NC_8

AJ5

NC_9

AK15

NC_10

AL7

NC_11

E7

NC_14

H32

NC_16

M7

NC_17

P6

NC_18

U7

NC_21

V6

NC_22

Y4

NC_23

F7 AG19

J10 J11 J12 J13 J9

D35 P7 AD20 AD19

R505 0 R0402

R7 E35

PM

S_Bot

MAX:120mA

AG14

T16 ns

AG20

GR19 2.49K,1% R0402

AG21

PM

GR29 10K R0402

AP35

S_Top

S_Top S_Top

S_Top

GR28 10K R0402

PM

S_Top

S46 VerA:Add reserved pull up resistor on TESTMODE follewed nvidia suggest

Under GPU Near GPU

GC71

GC84

C0402

0.1uF/10V,X7R

0.1uF/10V,X7R 1uF/10V,X5R

1uF/10V,X5R

S_Top

PM

S_Top

PM

Under GPU Near GPU

GC98

GC82

GC69

C0402

0.1uF/10V,X7R

0.1uF/10V,X7R 1uF/10V,X5R

1uF/10V,X5R

S_Top

PM

S_Top

PM

MAX:19.6A

GC26

GC35

C0402

0.047uF/16V,X7R

S_Top

0.047uF/16V,X7R

S_Top

0.01uF/25V,X7R

S_Top

0.01uF/25V,X7R

S_Top

0.22uF/10V,X7R

0.047uF/16V,X7R

S_Top

PM

S_Top

PM

GC56

GC78

C0402

0.022uF/16V,X7R

PM

S_Top

PM

GC70

GC75

C0402

0.01uF/25V,X7R

S_Top

PM

S_Top

PM

GC64

GC72

C0402

4700pF/25V,X7R

S_Top

PM

MAX:120mA

0.1uF/10V,X7R

S_Top

PM

0.1uF/10V,X7R

S_Top

PM

GC13

PM

0.1uF/10V,X7R

S_Top

PM

MAX:180mA

NVVDD_SENSE {52}

Near GPU

1uF/10V,X7R

S_Top

+V3.3GPU

ns

GC73

C0402

1uF/10V,X5R

S_Top

PM

GC65

C0402

1uF/10V,X5R

S_Top

PM

GC66

PM

GC51

C0402

0.022uF/16V,X7R

S_Top

PM

GC59

C0402

PM

GC55

C0402

4700pF/25V,X7R

S_Top

PM

GC32

GC18

GC8

C0603

PM

Under GPU

0.22uF/10V,X7R

S_Top

PM

0.01uF/25V,X7R

S_Top

PM

Near GPUUnder GPU

PM

GC6

4.7uF/10V,X5R

S_Top

PM

+V1.05GPU

GC87

GC93

C0805

4.7uF/10V,X5R

S_Top

GC90

C0805

4.7uF/10V,X5R

S_Top

GC39

C0603

GC62

C0402

0.022uF/16V,X7R

S_Top

GC49

GC23

C0603

1uF/10V,X7R

S_Top

GFB1

1 2

C0805

GC87

C0805

10uF/6.3V,X5R

S_Top

PM

+V1.05GPU

GC91

GC102

C0805

10uF/6.3V,X5R

4.7uF/10V,X5R

S_Top

PM

+VGA_CORE

Near GPU

GC50

GC31

C0805

1uF/10V,X5R

4.7uF/10V,X5R

S_Top

PM

GC60

0.022uF/16V,X7R

S_Top

PM

+V3.3GPU

GC11

C0805

4.7uF/10V,X5R

S_Top

PM

S46 VerA:Delete some caps followed N10M DG 090327

+V1.05GPU

FB0603

120ohm@100MHz,500mA

PM

S_Top

Layout Notice

Under GPU: The total trace length measured from GPU ball to cap is no more than 150 mil Near GPU: The total trace length measured from GPU ball to cap is no more than 750 mil

U3F

+VGA_CORE +VGA_CORE

NVVDD

AB11

VDD_001

AB13

VDD_002

AB15

VDD_003

AB17

VDD_004

AB19

VDD_005

AB21

VDD_006

AB23

VDD_007

AB25

VDD_008

AC11

VDD_009

AC12

VDD_010

AC13

VDD_011

AC14

VDD_012

AC15

VDD_013

AC16

VDD_014

AC17

VDD_015

AC18

VDD_016

AC19

VDD_017

AC20

VDD_018

AC21

VDD_019

AC22

VDD_020

AC23

VDD_021

AC24

VDD_022

AC25

VDD_023

AD12

VDD_024

AD14

VDD_025

AD16

VDD_026

AD18

VDD_027

AD22

VDD_028

AD24

VDD_029

L11

VDD_030

L12

VDD_031

L13

VDD_032

L14

VDD_033

L15

VDD_034

L16

VDD_035

L17

VDD_036

L18

VDD_037

L19

VDD_038

L20

VDD_039

L21

VDD_040

L22

VDD_041

L23

VDD_042

L24

VDD_043

L25

VDD_044

M12

VDD_045

M14

VDD_046

M16

VDD_047

M18

VDD_048

M20

VDD_049

M22

VDD_050

M24

VDD_051

P11

VDD_052

P13

VDD_053

P15

VDD_054

P17

VDD_055

P19

VDD_056

NB10_G128

S_Bot

PM

VDD_057 VDD_058 VDD_059 VDD_060 VDD_061 VDD_062 VDD_063 VDD_064 VDD_065 VDD_066 VDD_067 VDD_068 VDD_069 VDD_070 VDD_071 VDD_072 VDD_073 VDD_074 VDD_075 VDD_076 VDD_077 VDD_078 VDD_079 VDD_080 VDD_081 VDD_082 VDD_083 VDD_084 VDD_085 VDD_086 VDD_087 VDD_088 VDD_089 VDD_090 VDD_091 VDD_092 VDD_093 VDD_094 VDD_095 VDD_096 VDD_097 VDD_098 VDD_099 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 VDD_111

P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24

U3G

GND

E15

GND_096

E18

PM

GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095

NB10_G128

S_Bot

GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191

E24 E27 E30 E6 E9 F2 F31 F34 F5 J2 J31 J34 J5 L9 M11 M13 M15 M17 M19 M2 M21 M23 M25 M31 M34 M5 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R31 R34 R5 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V12 V14 V16 V18 V2 V20 V22 V24 V31 V5 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25

AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19

AA2 AA20 AA21 AA22 AA23 AA24 AA25 AA34

AA5 AB12 AB14 AB16 AB18 AB20 AB22 AB24

AC9 AD11 AD13 AD15 AD17

AD2 AD21 AD23 AD25 AD31 AD34

AD5 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25

AG2 AG31 AG34

AG5

AK2 AK31 AK34

AK5 AL12 AL15 AL18 AL21 AL24 AL27 AL30

AL6

AL9

AN2 AN34 AP12 AP15 AP18 AP21 AP24 AP27

AP3 AP30 AP33

AP6

AP9

B12

B15

B21

B24

B27

B3 B30 B33

B6

B9

C2 C34 E12

D D

C C

B B

+V3.3GPU

PM

PEG_NV_RXP[15:0]{7} PEG_NV_RXN[15:0]{7}

PEG_RXP[15:0]{7}

PEG_RXN[15:0]{7}

VerA: all PCIE singala lane reversal llh0523

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

D

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

1

bent N10M PCIE&PWR&GND

N10M PCIE&PWR&GND

C46

A

17 59Friday, November 27, 2009

of

5

U3B

FBAD_0

L32

FBA_D0

FBAD_1 FBAD_2 FBAD_3 FBAD_4 FBAD_5 FBAD_6 FBAD_7 FBAD_8 FBAD_9 FBAD_10 FBAD_11 FBAD_12

+V1.5GPU

GR11

GR11 1K,1%

1K,1%

ns

GR8

2.49K,1%

ns

FBA_CLK0

FBA_CLK0#

FBAD_13 FBAD_14 FBAD_15 FBAD_16 FBAD_17 FBAD_18 FBAD_19 FBAD_20 FBAD_21 FBAD_22 FBAD_23 FBAD_24 FBAD_25 FBAD_26 FBAD_27 FBAD_28 FBAD_29 FBAD_30 FBAD_31 FBAD_32 FBAD_33 FBAD_34 FBAD_35 FBAD_36 FBAD_37 FBAD_38 FBAD_39 FBAD_40 FBAD_41 FBAD_42 FBAD_43 FBAD_44 FBAD_45 FBAD_46 FBAD_47 FBAD_48 FBAD_49 FBAD_50 FBAD_51 FBAD_52 FBAD_53 FBAD_54 FBAD_55 FBAD_56 FBAD_57 FBAD_58 FBAD_59 FBAD_60 FBAD_61 FBAD_62 FBAD_63

FBADQM_0 FBADQM_1 FBADQM_2 FBADQM_3 FBADQM_4 FBADQM_5 FBADQM_6 FBADQM_7

FBADQS_0 FBADQS_1 FBADQS_2 FBADQS_3 FBADQS_4 FBADQS_5

FBADQS_6

FBADQS_7

FBADQS_0# FBADQS_1# FBADQS_2# FBADQS_3# FBADQS_4# FBADQS_5# FBADQS_6# FBADQS_7#

GC44

0.01uF/16V,X7R

ns

+V1.5GPU

GC80

0.1uF/10V,X7R

PM

GC189

0.1uF/10V,X7R

PM

D D

C C

B B

A A

AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33

AL31 AM33 AL33 AK30 AK32

AJ30 AH30 AH33 AH35 AH34 AH32

AJ33 AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35

AF32 AL32 AL34 AF35

AE31

AJ32

AJ34 AC33

AD32

AJ31

AJ35 AC34

AG29 AH29 AD29 AE29

N33 L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31 F30 G30 G32 K30 K32 H30 K31 L31 L30 M32 N30 M30 P31 R32 R30

P32 H34 J30 P30

L34 H35 J32 N31

L35 G35 H31 N32

P29 R29 L29 M29

J27

5

FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_WDS0/NC FBA_WDS0#/NC FBA_WDS1/NC FBA_WDS1#/NC FBA_WDS2/NC FBA_WDS2#/NC FBA_WDS3/NC FBA_WDS3#/NC

FB_VREF

NB10_G128

PM

GC139

0.1uF/10V,X7R

PM

GC92

0.1uF/10V,X7R

PM

FBA_ODT0

GR30

GR30 10K

10K

PM

R558

R558 243,1%

243,1%

PM

FPA

PM

GC135

0.01uF/16V,X7R

GC168

0.01uF/16V,X7R

FBVDDQ0 FBVDDQ1 FBVDDQ2 FBVDDQ3 FBVDDQ4 FBVDDQ5 FBVDDQ6 FBVDDQ7 FBVDDQ8

FBVDDQ9 FBVDDQ10 FBVDDQ11 FBVDDQ12 FBVDDQ13 FBVDDQ14 FBVDDQ15 FBVDDQ16 FBVDDQ17 FBVDDQ18 FBVDDQ19 FBVDDQ20 FBVDDQ21 FBVDDQ22 FBVDDQ23 FBVDDQ24 FBVDDQ25 FBVDDQ26

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9

FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27

FBA_CMD28 FBA_CMD29/NC FBA_CMD30/NC

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

FBA_DEBUG

FB_DLLAVDD0 FB_PLLAVDD0

FBB_ODT0

GR37

GR37 10K

10K

PM

FBA_CLK1

FBA_CLK1#

J23 J24 J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22

V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29

T32 T31 AC31 AC30

T30

AG27 AF27

GC81

0.1uF/10V,X7R

PM

GC88

0.1uF/10V,X7R

PM

MAX:5700mA

FBA_A4 FBA_RAS# FBA_A5 FBA_BA1

FBB_A2 FBB_A4 FBB_A3

FBB_CS# FBA_A11 FBA_CAS#

FBA_WE# FBA_BA0 FBB_A5 FBA_A12 FBA_RST FBA_A7 FBA_A10 FBA_CKE FBA_A0 FBA_A9 FBA_A6 FBA_A2 FBA_A8 FBA_A3 FBA_A1 FBA_A13 FBA_BA2

FBB_ODT0

FBA_CS0#

FBA_ODT0

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

GC190

1uF/10V,X7R

PM

GC144

1uF/10V,X7R

PM

FBB_CKE

T17 nsT17 ns

MAX:100mA

C0603

GC74

0.01uF/16V,X7R

PM

GC83

0.01uF/16V,X7R

0.047uF/16V,X7R

PM

1uF/10V,X5R

GC182

C0603

1uF/10V,X7R

PM

GC140

C0603

1uF/10V,X7R

PM

0.047uF/16V,X7R

PM

Near GPU

GC85

PM

R616

R616 243,1%

243,1%

PM

GC76

GC77

PM

GC86

4.7uF/10V,X5R

C0805

PM

GC79

C0805

4.7uF/10V,X5R

GC131

C0805

4.7uF/10V,X5R

GC53

0.1uF/10V,X7R

GC48

0.1uF/10V,X7R

GFB8

120ohm@100MHz,500mA

1 2

PM

Near GPUUnder GPU

PM

FB0603

+

+V1.5GPU

GC68

4.7uF/10V,X5R

+V1.05GPU

GC138

GC138 150UF/2.5V

150UF/2.5V

CT7343_28

ns

+V1.5GPU

PM

4

GC115

0.1uF/10V,X7R

PM

GC142

0.1uF/10V,X7R

4

PM

GC141

0.1uF/10V,X7R

PM

GC147

0.1uF/10V,X7R

FBB_VREF3

FBB_VREF1

FBAD_6 FBAD_1 FBAD_7 FBAD_4 FBAD_3 FBAD_0 FBAD_5 FBAD_2 FBADQS_0# FBADQS_0

FBAD_60 FBAD_59 FBAD_61 FBAD_56 FBAD_63 FBAD_58 FBAD_62 FBAD_57

FBADQS_7

PM

+V1.5GPU

GC151

0.01uF/16V,X7R

GC187

0.01uF/16V,X7R

A1 C1 F1 D2 H2 A8 C9 E9 H9

N1 R1 B2 K2 G7 K8 D9 N9 R9

B1 D1 G1 E2 D8 E8 B9 F9 G9

E1 M1 P1 T1 J2 B3 G8 J8 A9 M9 P9 T9

H1 M8

D7 C3 C8 C2 A7 A2 B8 A3 B7 C7

A1 C1 F1 D2 H2 A8 C9 E9 H9

N1 R1 B2 K2 G7 K8 D9 N9 R9

B1 D1 G1 E2 D8 E8 B9 F9 G9

E1 M1 P1 T1 J2 B3 G8 J8 A9 M9 P9 T9

H1 M8

D7 C3 C8 C2 A7 A2 B8 A3 B7 C7

PM

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

VREFDQ VREFCA

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU# DQSU

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

VREFDQ VREFCA

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU# DQSU

GC148

0.1uF/10V,X7R

GC186

0.1uF/10V,X7R

3

+V1.05GPU {17,19,20,57} +V1.5GPU {19,57}

U11

DDR3

U29

DDR3

1uF/10V,X7R

PM

GC137

GC137 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

FBA_A0

N3

A0

FBA_A1

P7

A1

FBA_A2

P3

A2

FBA_A3

N2

A3

FBA_A4

P8

A4

FBA_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

A15/BA3

FBA_ODT0

K1

ODT0

J1

ODT1

FBA_CS0#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

RESET#

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_0

D3

DMU

FBADQM_3

E7

DML

FBA_CLK0

J7

CK

FBA_CLK0#

K7

CK#

FBA_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_25

E3

DQL0

FBAD_27

F7

DQL1

FBAD_28

F2

DQL2

FBAD_29

F8

DQL3

FBAD_26

H3

DQL4

FBAD_30

H8

DQL5

FBAD_24

G2

DQL6

FBAD_31

H7

DQL7

FBADQS_3#

G3

DQSL#

FBADQS_3

F3

DQSL

FBA_A0

N3

A0

FBA_A1

P7

A1

FBB_A2

P3

A2

FBB_A3

N2

A3

FBB_A4

P8

A4

FBB_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

A15/BA3

FBB_ODT0

K1

ODT0

J1

ODT1

FBB_CS#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

RESET#

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_7

D3

DMU

FBADQM_4

E7

DML

FBA_CLK1

J7

CK

FBA_CLK1#

K7

CK#

FBB_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_32

E3

DQL0

FBAD_36

F7

DQL1

FBAD_33

F2

DQL2

FBAD_37

F8

DQL3

FBAD_35

H3

DQL4

FBAD_39

H8

DQL5

FBAD_34

G2

DQL6

FBAD_38

H7

DQL7

FBADQS_4#FBADQS_7#

G3

DQSL#

FBADQS_4

F3

DQSL

GC175

GC122

GC122 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

GC95

GC114

1uF/10V,X7R

4.7uF/10V,X5R

C0603

C0805

PM

GC99

4.7uF/10V,X5R

C0805

GR48

GR48 243,1%

243,1%

PM

GR39

GR39 243,1%

243,1%

PM

FBB_CKE

FBA_CKE FBA_RST

待确定

3

GR31

GR38

10K

PM

+V1.5GPU

PM

+V1.5GPU +V1.5GPU

GR51

GR51 1K,1%PM

1K,1%PM

FBB_VREF3 FBB_VREF4

GR50

GR50 1K,1%

1K,1%

PM

GR26

GR26 1K,1%

1K,1%

FBB_VREF1

GR25

GR25 1K,1%

1K,1%

PM

GC188

0.01uF/16V,X7R

GR33

GR33 10K

10K

GC89

0.01uF/16V,X7R

+V1.5GPU

PM

GR46

GR46 1K,1%

1K,1%

FBB_VREF2

GR47

GR47 1K,1%

1K,1%

PM

GC163

0.01uF/16V,X7R

PM

GR34

GR34 1K,1%

1K,1%

GR36

GR36 1K,1%

1K,1%

GC136

0.01uF/16V,X7R

PM

2

FBB_VREF2

FBB_VREF4

2

FBAD_13 FBAD_11 FBAD_14 FBAD_8 FBAD_12 FBAD_10 FBAD_15 FBAD_9 FBADQS_1# FBADQS_1

FBAD_48 FBAD_52 FBAD_50 FBAD_54 FBAD_51 FBAD_55 FBAD_49 FBAD_53 FBADQS_6# FBADQS_6

+V1.5GPU

1

U26

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

PM

U13

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

PM

A15/BA3

RESET#

A15/BA3

RESET#

FBA_A0

N3

A0

FBA_A1

P7

A1

FBA_A2

P3

A2

FBA_A3

N2

A3

FBA_A4

P8

A4

FBA_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBA_ODT0

K1

ODT0

J1

ODT1

FBA_CS0#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_1

D3

DMU

FBADQM_2

E7

DML

FBA_CLK0

J7

CK

FBA_CLK0#

K7

CK#

FBA_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_23

E3

DQL0

FBAD_19

F7

DQL1

FBAD_20

F2

DQL2

FBAD_16

F8

DQL3

FBAD_22

H3

DQL4

FBAD_17

H8

DQL5

FBAD_21

G2

DQL6

FBAD_18

H7

DQL7

FBADQS_2#

G3

DQSL#

FBADQS_2

F3

DQSL

FBA_A0

N3

A0

FBA_A1

P7

A1

FBB_A2

P3

A2

FBB_A3

N2

A3

FBB_A4

P8

A4

FBB_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBB_ODT0

K1

ODT0

J1

ODT1

FBB_CS#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_6

D3

DMU

FBADQM_5

E7

DML

FBA_CLK1

J7

CK

FBA_CLK1#

K7

CK#

FBB_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_47

E3

DQL0

FBAD_43

F7

DQL1

FBAD_46

F2

DQL2

FBAD_41

F8

DQL3

FBAD_45

H3

DQL4

FBAD_42

H8

DQL5

FBAD_44

G2

DQL6

FBAD_40

H7

DQL7

FBADQS_5#

G3

DQSL#

FBADQS_5

F3

DQSL

GR27

GR27 243,1%

243,1%

PM

待确定

GR49

GR49 243,1%

243,1%

PM

待确定

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

D

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

bent N10M memory1

N10M memory1

C46

A

18 59Friday, November 27, 2009

of