CCE T546P Schematic

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Topstar Digital technologies Co.,LTD

D D

Board name: MotherBoard Schematic Project name: C46 Version: VerA Initial Date: MAY.9, 2008

02. System block & Index

03. PWR Block & Description

04. Notes & Annotations

05. Schematic Modify and History

59. CLOCK Distribution

60. Power on & off Sequence

60. Power On Sequence & Reset Map

61. ACPI Mode Switch Timings

Topstar Confidential

C C

Hardware drawing by:

Power drawing by:

Hardware check by: EMI Check by:

Power check by:

Manager Sign by:

B B

A A

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

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the expressed written consent of TOPSTAR

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Title

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Topstar Confidential

ShenZhen Topstar Industry Co.,LTD

D D

Backlight Connector

+VDC

TFT

+V3.3S

C C

LVDS switch

VGA

+V5S

LVDS

PCIE mini Card

B B

PCIE mini Half-Card

NEW CARD(Type II)

C46 SYSTEM BLOCK Ver:A

Only for PM

64M*16Bit*4 GDDRIII

+V1.5GDDR

Memory

Nvidia NB11

Camera

1.3M/2.0M MODULE

interface

+VGA_CORE, +V1.05GPU +V1.8GDDR, +V3.3GPU +V1.5GPU

PCIE 1X

HDMI

BLUE TOOTH(V1.2)

BTM-203/CCOM

+V3.3S

+V3.3AL

LVDS

R/G/B TMDS

PCI-Express X16

USB1.1/2.0

PEGX16 /eDP

USB PORT1

+V5AL

SPI

BIOS

8Mbit

+V3.3AL

KB Controller/EC

+V3.3AL,+V3.3S,+V5AL

Arrandule/clarsfield

989rPGA

+VCC_CORE,+VccGFX +V1.5S, +V1.8S, +V1.1S_VTT

FDI

DMI*4 100MHz

Ibex_peak

1071 BGA

+V3.3A,+V3.3S,+V1.5S, +V1.05S,+V1.8S, +V5A,+V5S

LPC

ENE 3926

SLG8SP585

+V3.3S

DDR3 800/1066

PCIE 1X

USB1.1/2.0

AZALIA

TCM

CK505M Clocking

+V3.3S,+V3.3AL

DDR3 SODIMM0 800/1066

+V0.75S,+V1.5,+V3.3S

DDR3 SODIMM1 800/1066

+V0.75S,+V1.5,+V3.3S

RJ45

RTL8102E

SATA ODD

S-ATA

2.5" HDD

+V5S,+V3.3S

+V5S

Card Reader

ITE 1337

+V3.3S,+V3.3AL

L

R

AZALIA

ALC662

+V5S,+V3.3S

RJ45

SD/MMC/MS CARD

MiC

LED/TouchPAD/Button/

DAUGHTER BOARD

KB Matrix

A A

5

4

3

Q-key/LID

DAUGHTER BOARD

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

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Sys block

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C46 POWER BLOCK Ver:A

Platform Logic

D D

VIN V_5 V_3

VR_ON

IMVP-6.5

CLK_ENABLE#

IMVP6_PWRGD

PCH CPU-M

C C

CLK CHIP

注意:

虚线表示电源电压信号。

VCC_SENCE VSS_SENCE

IMON

VR_TT# Vcc_core

VID[6...0] PSI# DPRSLPVR

CPU_PWRGD

PSI#

PROCHOT#

Charge ISL6251

Adapter

B B

65/90W

Battery

Power Switch

+VDC

5A

51A

+VCC_CORE

VCC_CORE ISL62882

+V1.8S

MOSFET

+V1.8GPU

KIA1117

Always_On Power

ISL62872

+VGA_CORE

10A

A A

5

ISL62881

+VGFX

14A

TPS51218

+V1.05S

8A

+V1.05GPU

2.5A

MOSFET

TPS51218

+V1.1S_VTT

18A

4

TPS51125

+V3.3AL +V5AL

5A/5A

MOSFET

+V3.3GPU

<0.5A

DDR Power TPS51218 +APL5331

12A/2.5A

MOSFET

+V1.5GPU

3A

+V1.5 +V0.75S

3

+V1.5S

3A

+V5S +V3.3S

MOSFET

System Power +V_S

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

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PWR Block

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Voltage Rails

+VDC

D D

+VCC_CORE

+V1.1S_VTT

+V1.05S +V0.75S +V1.5

+V3.3AL

+V3.3S +V5AL +V5S +VGA_CORE

+V1.5S

+V1.8S

+V3.3GPU

+V1.05GPU

C C

+V1.8GPU 1.8V for external GPU

+V1.5GPU 1.5V for external GPU

Primary DC system power supply(9V-19V) Core voltage for processor

1.1V for CPU

1.05V for PCH core

0.75V DDR3 Termination voltage

1.5V power rail for DDR3

3.3V always on power rail

3.3V main power rail 5V for USB Device 5V main power rail

0.8--1.03V for GPU NB8M core voltage

1.5S for PCIE Device

1.8V for display votage

3.3V for external GPU

1.05V for external GPU

I2C SMB Address

Device

Clock Generator SO-DIMM0 SO-DIMM1 NEW CARD PCIE Mini CARD

Smart Battery

0001 011x 16 I2C ENE3926

Address

1101 001x 1010 000x 1010 010x

Variable Variable SMB1_PCHPCH

BusHex

SMB_PCH

D2

SMB_PCH

A0

SMB_PCH

A4

SMB_PCH

VariableVariable

SMB_PCH

VariableVariable

Master

PCH PCH PCH PCH PCH

ENE3926

Power States/AC mode

Board stack up description

PCB Layers

TOP

GND

IN1

IN2

VCC

IN3

B B

GND

Bottom

Trace Impedence:50ohm +/-15%(Default)

Signal

S0(Full On) S3(STM) S4(STD) S5(SoftOff)

SLP_S3#

HIGH LOW LOW OFF LOW

SLP_S4#

HIGH HIGH ON OFF LOW LOW

SLP_S5#

HIGH HIGH HIGH LOW

+V*AL

ON

ON ON

+V*

ON ON ON

OFF

+V*S

OFF OFF OFF

Clock

ON

OFF OFF

Wake up Events

USB Table

USB Port#

A A

Function Description

0

Express Card

1

minicard1

reserved

2

3

camera

4

USB port1

5

Bluetooth

6

Reserved

7

Reserved

8

CARD Reader

9

minicard2

10

USB port2

11

USB port3

5

4

3

LID switch from EC Power switch from EC

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

Notes

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VerA to VerB Changelist

1.

外置

VBIOS ROM

2. 27M clock

3.PCH 端100M的CLK-REQ#

4. PCH GPIO16

D D

5.Switch IC的footprint

6. RGB的ESD

7. HDMI

接到EC的

8. SYS_RST#

9.SIM 卡/

键盘/电池三个

10.GPU_RST#

11.HD connecter 和TP

12.BT connect

VerB to VerC Changelist

1. N11M

那边加上背光控制的与门解决开机屏就白着的问题。

2.

C C

蓝牙那边的那组

3.EC那边IMVP_ON的1K

VerC to VerD Changelist

1.N11M

那边

2. 3.3AL/5AL

USB线P/N

HDMI

电那边

改成内置，

的串联电阻

0ohm

下拉改为上拉。

下拉改为上拉，

改成符合实物的。

管子摆放方向改正。

预留

detect 0hm

信号接法调整。

connecter换footprint

预留上拉。

键的左右按钮物料更改。

那边有改发

反转过来，之前接反了。

电阻换

0ohm

。（电源那边已经分压了）。

信号线连接有误。

colay 220uf poscap

srrap

改为

上拉改为

33ohm

15K

。

follow CHECK LIST

ECN

注意不要遗漏

D2+/-与D1+/-

的电容。

调换。

。

B B

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

history

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+V3.3S {8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57} +V3.3AL {23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56}

3

2

1

0.1UF/25V,Y5V

C216

C234

0.1UF/25V,Y5V

C0402

+V3.3S

R247

R247 10K

10K

R0402

C217

0.1UF/25V,Y5V

C0402

+V3.3S

R277

R277 10K

10K

R0402

ns

+V3.3S_CK_VDD

C220

0.1UF/25V,Y5V

C0402

+VDDIO_CLK

C229

0.1UF/25V,Y5V

C0402

C227

C0402

Layout Note: Cap Close to CK505 PWR pin

C222

0.1UF/25V,Y5V

C0402

CLK_BUF_REF14

C232 10PF/50V,NPOnsC0402C232 10PF/50V,NPOnsC0402

C231 27pF/50V,NPO

C0402

2 1

C233 27pF/50V,NPO

C0402

update Y1 footprint

+V3.3S_CK_VDD

+VDDIO_CLK

No more than 500 mil

Y1

43

14.318MHz

XS4_5032_0D8

XTAL_IN XTAL_OUT

1

5 17 29

24 18 15

G1 G2 G3 G4

28 27

G5

2

8

9 12 21 26

U12

VDD_DOT VDD_27 VDD_SRC VDD_REF

VDD_CPU VDD_CPU_IO VDD_SRC_IO GND1 GND2 GND3 GND4 XTAL_IN

XTAL_OUT GND5

VSS_DOT VSS_27 VSS_SATA VSS_SRC VSS_CPU VSS_REF

CK505QFN32

SMB_DATA

SMB_CLK

CPU_STOP#

CPU0

CPU0#

CPU1

CPU1# DOT96

DOT96#

SRC0/SATA

SRC0#/SATA

SRC1

SRC1#

27M_NSS

27M_SS

REF/FS

CK_PWRGD/PWRDWN#

SMBUS ADD:1101 001X

31 32

16 23

22 20

19 3

4 10

11 13

14 6

7 30

25

R275 0 R0402R275 0 R0402

R276 0 R0402R276 0 R0402

CPU_STOP# BCLK

R264 0 R0402R264 0 R0402

BCLK#

R261 0 R0402R261 0 R0402

Integrated resistors on differentail clk

DOT96

R262 0 R0402R262 0 R0402

DOT96#

R260 0 R0402R260 0 R0402

R243 0 R0402R243 0 R0402

R242 0 R0402R242 0 R0402

R241 0 R0402R241 0 R0402

R240 0 R0402R240 0 R0402

BCLK_FS

R278 33 R0402R278 33 R0402

CLK_PWRGD

SMB_DATA_S {15,16,23,40,41} SMB_CLK_S {15,16,23,40,41}

CLK_BUF_BCLK_P {23} CLK_BUF_BCLK_N {23}

CLK_BUF_DOT96_P {23} CLK_BUF_DOT96_N {23}

CLK_BUF_SATA_P {23} CLK_BUF_SATA_N {23}

CLK_BUF_EXP_P {23} CLK_BUF_EXP_N {23}

27M_nonSSC {20}

27M_SSC {20}

CLK_BUF_REF14 {23}

FB10 100ohm@100MHz,3A

D D

C C

B B

+V3.3S

12

FB0805

C226

10UF/6.3V,X5R

0.1UF/25V,Y5V

C0805

CPU_STOP#

FB9 100ohm@100MHz,3A

1 2

FB0805

C230

10UF/6.3V,X5R

C0805

Frequence Select High:100Mhz Low:133Mhz(Default)

C223

C0402

C0805

BCLK_FS

+V3.3S

R307

R307 10K

10K

R314

R0402

10K

ns

10K

ns

R0402

3

PQ32

PQ32 2N7002

2N7002

SOT23

R317 1K

CK505_CLK_EN#{55}

A A

5

R317 1K

R0402

C249

C0402ns

0.1UF/25V,Y5V

4

SOT23

1

2

C244

C0402

0.1UF/25V,Y5V

R306 0nsR306 0ns

+V3.3AL

C236

0.1UF/10V,X7R

53

VCC

1 2

GND

CLK_PWRGD

4 SOT23_5

SOT23_5

SN74AHC1G08DBV

SN74AHC1G08DBV U15

U15

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

CK505M

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U2A

D D

C C

B B

A A

5

DMI_TXN0{24} DMI_TXN1{24} DMI_TXN2{24} DMI_TXN3{24}

DMI_TXP0{24} DMI_TXP1{24} DMI_TXP2{24} DMI_TXP3{24}

DMI_RXN0{24} DMI_RXN1{24} DMI_RXN2{24} DMI_RXN3{24}

DMI_RXP0{24} DMI_RXP1{24} DMI_RXP2{24} DMI_RXP3{24}

FDI_TXN[7:0]{24}

FDI_TXP[7:0]{24}

FDI_FSYNC0{24} FDI_FSYNC1{24}

FDI_INT{24}

FDI_LSYNC0{24} FDI_LSYNC1{24}

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

DMI Intel(R) FDI

4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS PEG_RX#[0]

PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_IRCOMP_R

EXP_RBIAS

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

R560 49.9,1%

R552 750 OHM

PEG_RXN[15:0] {17}

PEG_RXP[15:0] {17}

GC1320.1UF/10V,X7RGC1320.1UF/10V,X7R GC1850.1UF/10V,X7R GC1850.1UF/10V,X7R

GC1270.1UF/10V,X7R GC1270.1UF/10V,X7R

GC1830.1UF/10V,X7R GC1830.1UF/10V,X7R GC1230.1UF/10V,X7R GC1230.1UF/10V,X7R GC1780.1UF/10V,X7RGC1780.1UF/10V,X7R GC1180.1UF/10V,X7RGC1180.1UF/10V,X7R GC1730.1UF/10V,X7RGC1730.1UF/10V,X7R GC1120.1UF/10V,X7R GC1120.1UF/10V,X7R GC1690.1UF/10V,X7RGC1690.1UF/10V,X7R GC1070.1UF/10V,X7R GC1070.1UF/10V,X7R

GC1640.1UF/10V,X7RGC1640.1UF/10V,X7R GC1030.1UF/10V,X7RGC1030.1UF/10V,X7R

GC1590.1UF/10V,X7RGC1590.1UF/10V,X7R

GC960.1UF/10V,X7R GC960.1UF/10V,X7R

GC1550.1UF/10V,X7R GC1550.1UF/10V,X7R

GC1300.1UF/10V,X7RGC1300.1UF/10V,X7R

GC1840.1UF/10V,X7RGC1840.1UF/10V,X7R

GC1260.1UF/10V,X7RGC1260.1UF/10V,X7R

GC1810.1UF/10V,X7RGC1810.1UF/10V,X7R

GC1210.1UF/10V,X7RGC1210.1UF/10V,X7R

GC1770.1UF/10V,X7RGC1770.1UF/10V,X7R

GC1170.1UF/10V,X7RGC1170.1UF/10V,X7R

GC1720.1UF/10V,X7RGC1720.1UF/10V,X7R

GC1110.1UF/10V,X7RGC1110.1UF/10V,X7R

GC1670.1UF/10V,X7RGC1670.1UF/10V,X7R

GC1060.1UF/10V,X7RGC1060.1UF/10V,X7R

GC1620.1UF/10V,X7RGC1620.1UF/10V,X7R

GC1010.1UF/10V,X7RGC1010.1UF/10V,X7R

GC1580.1UF/10V,X7RGC1580.1UF/10V,X7R

GC94 0.1UF/10V,X7RGC94 0.1UF/10V,X7R

GC1540.1UF/10V,X7RGC1540.1UF/10V,X7R

3

R0402

PEG_NV_RXN0 PEG_NV_RXN1 PEG_NV_RXN2 PEG_NV_RXN3 PEG_NV_RXN4 PEG_NV_RXN5 PEG_NV_RXN6 PEG_NV_RXN7 PEG_NV_RXN8 PEG_NV_RXN9 PEG_NV_RXN10 PEG_NV_RXN11 PEG_NV_RXN12 PEG_NV_RXN13 PEG_NV_RXN14 PEG_NV_RXN15

PEG_NV_RXP0 PEG_NV_RXP1 PEG_NV_RXP2 PEG_NV_RXP3 PEG_NV_RXP4 PEG_NV_RXP5 PEG_NV_RXP6 PEG_NV_RXP7 PEG_NV_RXP8 PEG_NV_RXP9 PEG_NV_RXP10 PEG_NV_RXP11 PEG_NV_RXP12 PEG_NV_RXP13 PEG_NV_RXP14 PEG_NV_RXP15

PEG_NV_RXN[15:0] {17}

PEG_NV_RXP[15:0] {17}

2

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent Arrandule

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+V1.1S_VTT {10,11,27,28,29,38,50,51,55} +V3.3S {6,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5 {11,15,16,49,56,57}

1

D D

U2B

H_COMP3 H_COMP2 H_COMP1

0 R0402

R213

R185

R185 750 OHM

750 OHM

R0402

H_COMP0

H_CATERR#

H_PECI_R

VR_PROCHOT#

H_CPURST#_R

H_PM_SYNC_R

VCCPWRGOOD_1_R

VCCPWRGD_0_R

PLT_RST#_R

+V1.1S_VTT

R187

49.9,1%

R0402

R548 68 R0402

ns

R549 68 R0402

ns

R182 0 R0402R182 0 R0402

R180 0 R0402R180 0 R0402

PM_DRAM_PWRGD

H_PWRGD_XDP_R

1.5K,1%

R181

R0402

R433 0 R0402R433 0 R0402

H_PECI{27}

+V1.1S_VTT

THERMTRIP#{27,38}

+V1.1S_VTT

C C

+V1.1S_VTT

R212

ns

1K,1%

R0402

B B

PM_DRAM_PWRGD

H_PM_SYNC{24}

VCCPWRGD_0{27}

PM_DRAM_PWRGD{24}

CPU_VTT_PWG{43}

BUF_PLT_RST#{17,26,38,39,40,41,43,44}

+V1.5

R105

1.21K,1%

R101

3.3K

U2B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

R198

49.9,1%

R0402

MISC THERMAL

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

Processor Compensation Signals

H_COMP1 H_COMP0

R543

R544

49.9,1%

R0402

R543

20,1%

r0402

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

H_COMP3 H_COMP2

R542

R542 20,1%

20,1%

r0402

BCLK_CPU_P_R

A16

BCLK_CPU_N_R

B16

BCLK_ITP_P

AR30

BCLK_ITP_N

AT30

CLK_EXP_P_R

E16

CLK_EXP_N_R

D16

CLK_DP_P_R

A18

CLK_DP_N_R

A17

F6 AL1

AM1 AN1

AN15 AP15

AT28 AP27

AN28

TCK

AP28

TMS

AT27 AT29

TDI

AR27

TDO

AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PM_EXT_TS#0 PM_EXT_TS#1

XDP_REQ

TCK TMS TRST#

TDI TDO TDI_M TDO_M

TDI_M

TDO_M

Layout Note: Place close to CPU

R520 0 R0402R520 0 R0402 R522 0 R0402R522 0 R0402

R528 0 R0402R528 0 R0402 R524 0 R0402R524 0 R0402

R539 0 R0402

R539 0 R0402 R531 0 R0402

R531 0 R0402

ns

ns ns

ns

T24nsT24

T18nsT18 T20nsT20 T23nsT23 T25nsT25 T26nsT26 T19nsT19 T22nsT22 T21nsT21

SM_RCOMP_2 SM_RCOMP_1 SM_RCOMP_0

100,1%

R0402

T59nsT59 T58nsT58

DDR3_DRAMRST# {15,16}

TDO

TMS

TCK

R559

49.9,1%

ns

R0402

TDI

ns ns

XDP_REQ

ns ns ns ns ns ns

R217

R217 0

0

R0402

ns

DDR3 Compensation Signals

R439

R438

24.9,1%

R0402

BCLK_CPU_P {27} BCLK_CPU_N {27}

ns ns

CLK_EXP_P {23} CLK_EXP_N {23}

49.9,1%

R0402

R566

ns

R216

49.9,1%

R0402 ns

49.9,1%

R0402

R218

49.9,1%

49.9,1% R568

R568

R0402 ns

49.9,1%

49.9,1% R214

R214

R0402 ns

R437

R437 130,1%

130,1%

R0402

+V1.1S_VTT

nsR218

ns

R634

R634 1K

1K

R0402

PM_EXT_TS#0

PM_EXT_TS#1

+V3.3S

R632

R632 10K

10K

R0402

1

Q30

Q30 MMBT3904-F

MMBT3904-F

SOT23

2 3

R0402

R123

R123 10K

10K

+V1.1S_VTT

R133

R133 10K

10K

+V1.1S_VTT

R636

R636 1K

1K

R0402

Q9

+V1.1S_VTT

Q8

MMBT3904-FSOT23

ns

23

+V1.1S_VTT

1

MMBT3904-FSOT23

ns

R129

R129 1K,1%

1K,1%

R0402

ns

1

23

Q31

Q31 MMBT3904-F

MMBT3904-F

SOT23

1

VR_PROCHOT#

R139

R139 1K,1%

1K,1%

R0402

ns

23

+V3.3S

R130

R130 10K

10K

R0402

ns

R118

R118 10K

10K

R0402

ns

EC_PROCHOT# {43}

R635

R635 1K

1K

R0402

VR_PROCHOT# {55}

+V3.3S

+V1.1S_VTT+V1.1S_VTT

Voltage Level?

DIM_EXTTS#0 {16}

Voltage Level?

DIM_EXTTS#1 {15}

目前我们用的内存端没有做过温的功能。

CPU_VTT_PWG

R344

R344 750 OHM

750 OHM

R0402

A A

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PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

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U2C

D D

MA_DATA[63:0]{16}

C C

MA_A_BS0{16} MA_A_BS1{16}

B B

MA_A_BS2{16}

MA_A_CAS#{16} MA_A_RAS#{16}

MA_A_WE#{16}

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

AK12

AK11

AM10 AR11

AT11 AP12 AM12 AN12 AM13 AT14 AT12

AR14 AP14

AJ10 AL10

AL11

AL13

A10

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39] SA_DQ[40]

AJ9

SA_DQ[41] SA_DQ[42] SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45] SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

4

AA6

SA_CK[0]

AA7

SA_CK#[0]

P7

SA_CKE[0]

Y6

SA_CK[1]

Y5

SA_CK#[1]

P6

SA_CKE[1]

AE2

SA_CS#[0]

AE8

SA_CS#[1]

AD8

SA_ODT[0]

AF9

SA_ODT[1]

MA_DM0

B9

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

MA_DM1

D7

MA_DM2

H7

MA_DM3

M7

MA_DM4

AG6

MA_DM5

AM7

MA_DM6

AN10

MA_DM7

AN13

MA_DQS#0

C9

MA_DQS#1

F8

MA_DQS#2

J9

MA_DQS#3

N9

MA_DQS#4

AH7

MA_DQS#5

AK9

MA_DQS#6

AP11

MA_DQS#7

AT13

MA_DQS0

C8

MA_DQS1

F9

MA_DQS2

H9

MA_DQS3

M9

MA_DQS4

AH8

MA_DQS5

AK10

MA_DQS6

AN11

MA_DQS7

AR13

MA_A_A0

Y3

MA_A_A1

W1

MA_A_A2

AA8

MA_A_A3

AA3

MA_A_A4

V1

MA_A_A5

AA9

MA_A_A6

V8

MA_A_A7

T1

MA_A_A8

Y9

MA_A_A9

U6

MA_A_A10

AD4

MA_A_A11

T2

MA_A_A12

U3

MA_A_A13

AG8

MA_A_A14

T3

MA_A_A15 MB_B_A14

V9

M_CLK_DDR0 {16}

M_CLK_DDR#0 {16} M_CKE0 {16}

M_CLK_DDR1 {16}

M_CLK_DDR#1 {16} M_CKE1 {16}

M_CS#0 {16} M_CS#1 {16}

M_ODT0 {16} M_ODT1 {16}

MA_DM[7:0] {16}

MA_DQS#[7:0] {16}

MA_A_A[15:0] {16}

MA_DQS[7:0] {16}

3

U2D

MB_DATA[63:0]{15}

MB_B_BS0{15} MB_B_BS1{15} MB_B_BS2{15}

MB_B_CAS#{15} MB_B_RAS#{15}

MB_B_WE#{15}

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

AR10 AT10

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61] SB_DQ[62] SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

2

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

MB_DM0

D4

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

MB_DM1

E1

MB_DM2

H3

MB_DM3

K1

MB_DM4

AH1

MB_DM5

AL2

MB_DM6

AR4

MB_DM7

AT8

MB_DQS#0

D5

MB_DQS#1

F4

MB_DQS#2

J4

MB_DQS#3

L4

MB_DQS#4

AH2

MB_DQS#5

AL4

MB_DQS#6

AR5

MB_DQS#7

AR8

MB_DQS0

C5

MB_DQS1

E3

MB_DQS2

H4

MB_DQS3

M5

MB_DQS4

AG2

MB_DQS5

AL5

MB_DQS6

AP5

MB_DQS7

AR7

MB_B_A0

U5

MB_B_A1

V2

MB_B_A2

T5

MB_B_A3

V3

MB_B_A4

R1

MB_B_A5

T8

MB_B_A6

R2

MB_B_A7

R6

MB_B_A8

R4

MB_B_A9

R5

MB_B_A10

AB5

MB_B_A11

P3

MB_B_A12

R3

MB_B_A13

AF7 P5

MB_B_A15

N1

M_CLK_DDR2 {15}

M_CLK_DDR#2 {15} M_CKE2 {15}

M_CLK_DDR3 {15}

M_CLK_DDR#3 {15} M_CKE3 {15}

M_CS#2 {15} M_CS#3 {15}

M_ODT2 {15} M_ODT3 {15}

MB_DM[7:0] {15}

MB_DQS#[7:0] {15}

MB_DQS[7:0] {15}

MB_B_A[15:0] {15}

1

IC,AUB_CFD_rPGA,R1P0

S_Bot

A A

5

4

3

IC,AUB_CFD_rPGA,R1P0

S_Bot

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

bent Arrandule

Arrandule

C46

1

A

959Friday, November 27, 2009

A

of

5

U2F

+VCC_CORE +V1.1S_VTT

4

3

2

+VCC_CORE {55} +V1.1S_VTT {8,11,27,28,29,38,50,51,55}

1

D D

C C

B B

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

PROC_DPRSLPVR

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

PSI#

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

VTT_SELECT_R

G15

Vcore_IMON_R

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

TP_VTT_SENSE

B15

TP_VSS_SENSE_VTT

A15

R5800R580 0

R1930R193 0

ns

C362

C362 10uF/6.3V,X5R

10uF/6.3V,X5R

C186

C186 10uF/6.3V,X5R

10uF/6.3V,X5R

C360

C360 10uF/6.3V,X5R

10uF/6.3V,X5R

Vcore_IMON {55}

R5810R581 R5820R582

0 0

ICTPns

T15

ICTP

T14

C363

C363 10uF/6.3V,X5R

10uF/6.3V,X5R

C388

C388 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.1S_VTT

C361

C361 10uF/6.3V,X5R

10uF/6.3V,X5R

PM_PSI# {55}

H_VID0 {55} H_VID1 {55} H_VID2 {55} H_VID3 {55} H_VID4 {55} H_VID5 {55} H_VID6 {55} PM_DPRSLPVR {55}

VTT_SELECT {50}

+VCC_CORE

R589

R589 100,1%

100,1%

R0402

VCCSENSE {55} VSSSENSE {55}

R590

R590 100,1%

100,1%

R0402

C364

10uF/6.3V,X5R

C145

10uF/6.3V,X5R

C365

10uF/6.3V,X5R

C146

10uF/6.3V,X5R

C380

C380 10uF/6.3V,X5R

10uF/6.3V,X5R

C147

0.22uF/10V,X7R

C170

10uF/6.3V,X5R

C373

10uF/6.3V,X5R

C171

C171 10uF/6.3V,X5R

10uF/6.3V,X5R

C368

0.01uF/25V,X7R

C379

C379 10uF/6.3V,X5R

10uF/6.3V,X5R

C384

C384 10uF/6.3V,X5R

10uF/6.3V,X5R

C381

C381 10uF/6.3V,X5R

10uF/6.3V,X5R

C174

C174 10uF/6.3V,X5R

10uF/6.3V,X5R

C192

C192 10uF/6.3V,X5R

10uF/6.3V,X5R

C385

C385 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.1S_VTT +V1.1S_VTT

R575

ns

1K

R0402

PM_PSI# PM_DPRSLPVR

R0402

R576

R576 1K

1K

R0402

Clarksfield 1.1v Arrandale 1.05v

C189

C175

C175 10uF/6.3V,X5R

10uF/6.3V,X5R

C172

C172 10uF/6.3V,X5R

10uF/6.3V,X5R

C377

C377 10uF/6.3V,X5R

10uF/6.3V,X5R

C173

C173 10uF/6.3V,X5R

10uF/6.3V,X5R

C376

C376 10uF/6.3V,X5R

10uF/6.3V,X5R

C209

C209 10uF/6.3V,X5R

10uF/6.3V,X5R

C176

C176 10uF/6.3V,X5R

10uF/6.3V,X5R

C378

C378 10uF/6.3V,X5R

10uF/6.3V,X5R

C199

C199 1uF/10V,X7R

1uF/10V,X7R

C169

C169 10uF/6.3V,X5R

10uF/6.3V,X5R

C375

C375 10uF/6.3V,X5R

10uF/6.3V,X5R

C198

C198 1uF/10V,X7R

1uF/10V,X7R

C374

C374 10uF/6.3V,X5R

10uF/6.3V,X5R

C197

0.22uF/10V,X7R

C190

C190 10uF/6.3V,X5R

10uF/6.3V,X5R

C387

C387 10uF/6.3V,X5R

10uF/6.3V,X5R

R221

R221 1K

1K

R0402

R220

ns

1K

R0402

C191

C191 10uF/6.3V,X5R

10uF/6.3V,X5R

C386

C386 10uF/6.3V,X5R

10uF/6.3V,X5R

C196

0.22uF/10V,X7R

C188

10uF/6.3V,X5R

C383

C383 10uF/6.3V,X5R

10uF/6.3V,X5R

C212

0.01uF/25V,X7R

+VCC_CORE

C187

C187 10uF/6.3V,X5R

10uF/6.3V,X5R

C382

10uF/6.3V,X5R

C210

0.01uF/25V,X7R

C211

C211 10uF/6.3V,X5R

10uF/6.3V,X5R

IC,AUB_CFD_rPGA,R1P0

A A

TOPSTAR TECHNOLOGY

bent

Page Name

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Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

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D D

4

3

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+VGFX {51}

+V1.1S_VTT {8,10,27,28,29,38,50,51,55}

+V1.5 {8,15,16,49,56,57}

+V1.8S {26,28,29,31,49,56,57}

1

+VGFX

C184

C161

C161 10uF/6.3V,X5R

10uF/6.3V,X5R

C148

C148 10uF/6.3V,X5R

10uF/6.3V,X5R

C184 10uF/6.3V,X5R

10uF/6.3V,X5R

C150

C150 10uF/6.3V,X5R

10uF/6.3V,X5R

C162

C371

0.01uF/25V,X7R

C151

C151 10uF/6.3V,X5R

10uF/6.3V,X5R

C162 10uF/6.3V,X5R

10uF/6.3V,X5R

C149

C149 10uF/6.3V,X5R

10uF/6.3V,X5R

C181

C181 10uF/6.3V,X5R

10uF/6.3V,X5R

C C

C160

0.22uF/10V,X7R

+V1.1S_VTT

B B

C183 10uF/6.3V,X5R

10uF/6.3V,X5R

C154

C154 10uF/6.3V,X5R

10uF/6.3V,X5R

C372

C372 10uF/6.3V,X5R

10uF/6.3V,X5R

C183

C152

C152 10uF/6.3V,X5R

10uF/6.3V,X5R

AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16

AL21 AL19 AL18

AL16 AK21 AK19 AK18 AK16

AJ21

AJ19

AJ18

AJ16 AH21 AH19 AH18 AH16

U2G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

GRAPHICS

FDI PEG & DMI

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_DPRSLPVR

GRAPHICS VIDs

POWER

DDR3 - 1.5V RAILS

1.1V1.8V

VAXG_SENSE

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

VGFXVCCSEN {51} VGFXVSSSEN {51}

GFXVR_VID_0 {51} GFXVR_VID_1 {51} GFXVR_VID_2 {51} GFXVR_VID_3 {51} GFXVR_VID_4 {51} GFXVR_VID_5 {51} GFXVR_VID_6 {51}

GFXVR_DPRSLPVR {51}

VGFX_IMON {51}

C106

C110

10uF/6.3V,X5R

C358

C358 10uF/6.3V,X5R

10uF/6.3V,X5R

VCCPLL

C108

C108 1uF/10V,X7R

1uF/10V,X7R

C359

C359 10uF/6.3V,X5R

10uF/6.3V,X5R

C107

1uF/10V,X7R

C185

C185 10uF/6.3V,X5R

10uF/6.3V,X5R

GFXVR_EN {51}

R545

4.7K

R0402

C111

C111 1uF/10V,X7R

1uF/10V,X7R

+V1.1S_VTT

C153

C153 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.5

C109

C109 1uF/10V,X7R

1uF/10V,X7R

IC,AUB_CFD_rPGA,R1P0

+V1.8S

VCCPLL

C200

C200 1uF/10V,X7R

1uF/10V,X7R

A A

5

4

C201

C201 1uF/10V,X7R

1uF/10V,X7R

C195

C195 1uF/10V,X7R

1uF/10V,X7R

3

FB8

1 2

300ohm@100MHz,1.5A

C193

10uF/6.3V,X5R

FB0805FB8

FB0805

TOPSTAR TECHNOLOGY

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Page Name

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Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

bent Arrandule

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1

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U2H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

A A

VSS8

AR17

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

IC,AUB_CFD_rPGA,R1P0

S_Bot

5

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

4

3

U2I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

IC,AUB_CFD_rPGA,R1P0

S_Bot

3

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

2

Page Name

Page Name Size

Size

Project Name Rev

B

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

1

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Arrandule

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12 59Friday, November 27, 2009

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5

U2E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

D D

ns

R209 0

VREFA_DDR3{16}

VREFB_DDR3{15}

R572

R0402

3.01K,1%

C C

B B

A A

R209 0 R204 0

R204 0

R570

R0402

3.01K,1%

3.01K,1% R573

R573

3.01K,1%

R0402

ns

never pull down for switchable graphic

5

VREF_CH_A_DIMM VREF_CH_B_DIMM

ns

CFG0

CFG3 CFG4

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0

4

AJ13

RSVD32

AJ12

RSVD33

AH25

RSVD34

AK26

RSVD35

AL26

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

KEY RSVD62 RSVD63 RSVD64 RSVD65

VSS

AR2 AJ26

AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD_TP_59 RSVD_TP_60

RESERVED

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

4

3

BRACKET

CPU_BRACKET

R579 0 R0402R579 0 R0402

3

H11

CPU_HOLE

11223344556677889

2

H12

CPU_HOLE

ns

11223344556677889

9

ns

9

2

H13

CPU_HOLE

ns

11223344556677889

ns

9

BRACKET1_Mylar

Mylar

Page Name

Page Name Size

Size

Project Name Rev

B

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

H14

CPU_HOLE

ns

11223344556677889

ns

9

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1

PCH Strapping

Name

SPKR

D D

INIT3_3V#

Reboot option at power-up

Internal pull-up. Leave as "No Connect"

GNT3#/GPIO55

INTVRMEN

GNT0# GNT1#

GNT2#/ GPIO53

SPI_MOSI

NV_ALE

NV_CLE

HDA_DOCK_EN

C C

#/GPIO33

HDA_SDO

HDA_SYNC

GPIO15

GPIO8

GPIO27

Integrated VRM Mode

Default(SPI): Leave both GNT0#and GNT1# floating. Boot: From PCI: Connect GNT1# to ground with 1k resistor,leave GNT0# Floating From LPC:Connect both GNT0# and GNT1#to ground with 1k resistor

Intel Anti-Theft Technology

DMI termination voltage

Flash Descriptor Security

Weak internal pull-down

Intel ME Crypto TLS cipher suite With

Weak internal pull-up

Default: floating

01Description

Default Mode No Reboot Mode

Top Block Swap Mode

with TCO Disabled

Default Mode

EnabledDisabled

Configures DMI for ESI

Default Mode

Disabled Enabled

EnabledDisabled

/

Security measure enabled

Weak internal pull-down Weak internal pull-down

Weak internal pull-up

1.Security measure Overridden

2.Sampled on the rising edge of PWROK,disables Intel ME& its freatures

/

No confidentiality Confidentiality

Weak internal pull-up Disables the internal VccVRM

/

Enables the internal VccVRM

Processor Strapping

Description

CFG[4]

CFG[3]

CFG[0]

Embedded DisplayPort Presence

PCI-E Static Lane Reversal

PIC-Express Configuration Select

An external Display Port device is connected to the Embedded Display Port

Lane Numbers Resersed 15->0.14->1, ...

Bifurcation enable Single PCIE Graphics

Note: Default value for each bit is 1 unless specified otherless

10

No Physical Display Port attached to Embedded Displayport

Normal Operation

Name Pin Attr Description GPIO0 +V3.3S I/O GPIO1 +V3.3S I/O GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

B B

A A

GPIO9 GPIO10

GPIO11 GPIO12 GPIO13 GPIO14 GPIO15

GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27

GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39

GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45

5

10Kohm pull up to V3.3S EXTSMI# Reserve for EC,10k to V3.3S

+V3.3S I/OD

8.2Kohm pull up to V3.3S

+V3.3S I/OD

8.2Kohm pull up to V3.3S

+V3.3S I/OD

8.2Kohm pull up to V3.3S

+V3.3S I/OD

As LVDS_DDC_SEL for DDC select

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

As EC_RUNTIME_SCI# link to EC,10K to V3.3S 10Kohm pull up to V3.3AL

+V3.3A I/O

As USB_OC#5 for USB board

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O +V3.3A I/O

NC

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

1Kohm pull up to V3.3AL

+V3.3S I/O

10K to GND,reserve 10K to V3.3S for debug

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

MiniPCIE_REQ# Reserve,10k to V3.3S

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

minicard_CLKREQ# Reserve,10k to V3.3S 10Kohm pull up to V3.3S

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

Reserve 10Kohm pull up to V3.3S for debug

+V3.3S I/O

10Kohm pull up to V3.3AL and 10K to GND

+V3.3A I/O

EXPCARD_CLKREQ# Reserve,100k to V3.3AL

+V3.3A I/O +V3.3A I/O

8.2Kohm pull up to V3.3AL

+V3.3A I/O

Reserve 10Kohm pull down to GND for debug

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

NC

+V3.3A I/O

As ALW_ACK link to EC and 10K to V3.3AL

+V3.3A I/O

As AC_IN_PCH link to EC

+V3.3S I/O

10Kohm pull up to V3.3S

4.7Kohm pull down to GND

+V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

10Kohm pull down to GND

+V3.3S I/O +V3.3S I/O

10Kohm pull up to V3.3S

+V3.3S I/O

10Kohm pull down to GND for BIOS ver

+V3.3S I/O

10Kohm pull down to GND for BIOS ver

+V3.3S I/O

10Kohm pull down to GND for BIOS ver

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

As USB_OC#2 for USB board

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

10Kohm pull up to V3.3AL

+V3.3A I/O

8.2Kohm pull up to V3.3AL

+V3.3A I/O

As TP(test point)

Name Pin Attr Description GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66 GPIO67 GPIO72 GPIO73 GPIO74 GPIO75

+V3.3A I/O +V3.3A I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3S I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O +V3.3A I/O

As TP(test point) As PCIE_CLKREQ for N10,10K to GND and 10K to V3.3GPU 10Kohm pull up to V3.3S 10Kohm pull up to V3.3S

8.2Kohm pull up to V3.3S Reserve 1K pull down to GND

8.2Kohm pull up to V3.3S As LVDS_BLT_SEL for BLT select

8.2Kohm pull up to V3.3S Reserve 1K pull down to GND

8.2Kohm pull up to V3.3AL 10Kohm pull up to V3.3AL As SML1CLK and 2.2K to V3.3AL 10Kohm pull up to V3.3AL 10Kohm pull up to V3.3AL As PM_SUS_STAT# link to EC and 1k to V3.3AL As TP As TP NC NC NC As CLK_CR_48M for IT1337E output 48M clock As BAT_LOW# link to EC and 10K to V3.3AL 10Kohm pull down to GND 10Kohm pull up to V3.3AL As SML1DATA and 2.2K to V3.3AL

4

TOPSTAR TECHNOLOGY

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Page Name

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Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

bent black

black

C46

A

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4

3

2

+V3.3S {6,8,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5 {8,11,16,49,56,57} +V0.75S {16,49,56}

1

D D

MB_B_A[15:0]{9}

+V1.5

C27

C47

C0805

2.2UF/10V,X7R

0.1UF/25V,Y5V

+V1.5

C25

C0402

0.1UF/25V,Y5V

C21

C0805

2.2UF/10V,X7R

ns

10UF/6.3V,X5R

0.1UF/25V,Y5V

C C

Layout note:

B B

ns

C0402

2.2UF/10V,X7R

+V1.5

C46

C46 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C40

C0402

2.2UF/10V,X7R

0.1UF/25V,Y5V

电容靠近

C77

C0805

C20

C0805

C27

C78

C47

C44

C75

C0402

C0805

0.1UF/25V,Y5V

2.2UF/10V,X7R

C48

C48 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C19

ns

C0805

0.1UF/25V,Y5V

2.2UF/10V,X7R

DDR slot VDD PIN

0.1UF/25V,Y5V

C76

ns

C0805

2.2UF/10V,X7R

C38

ns

C0402

2.2UF/10V,X7R

+V3.3S

C30

C0402

C34

C45

C0805

C0402

0.1UF/25V,Y5V

C35

C39

ns

C0805

2.2UF/10V,X7R

Note: SO-DIMM1 SPD Address is 0xA4

C31

2.2UF/10V,X7R

C0805

close to DDR pin199

M_CLK_DDR2{9} M_CLK_DDR#2{9} M_CLK_DDR3{9} M_CLK_DDR#3{9}

MB_DQS[7:0]{9}

VREFB_DDR3

C28

0.1UF/25V,Y5V

C0402

close to DDR pin1

DDR3_DRAMRST#{8,16}

MB_B_BS0{9} MB_B_BS1{9} MB_B_BS2{9}

M_CS#2{9} M_CS#3{9}

MB_DM[7:0]{9}

MB_B_WE#{9} MB_B_CAS#{9} MB_B_RAS#{9}

M_CKE2{9} M_CKE3{9}

M_ODT2{9} M_ODT3{9}

SMB_DATA_S{6,16,23,40,41} SMB_CLK_S{6,16,23,40,41}

R46 10K R0402R46 10K R0402 R49 10K R0402R49 10K R0402

DIM_EXTTS#1{8}

C29

2.2UF/10V,X7R

C0805

MB_B_A0 MB_B_A1 MB_B_A2 MB_B_A3 MB_B_A4 MB_B_A5 MB_B_A6 MB_B_A7 MB_B_A8 MB_B_A9 MB_B_A10 MB_B_A11 MB_B_A12 MB_B_A13 MB_B_A14 MB_B_A15

MB_DQS0 MB_DQS1 MB_DQS2 MB_DQS3 MB_DQS4 MB_DQS5 MB_DQS6 MB_DQS7

VREFB_CA

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

+V1.5+V0.75S

203

204

VTT1

VTT2

VDD175VDD276VDD381VDD482VDD587VDD688VDD793VDD894VDD9

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

CS0

121

CS1

11

DQM0

28

DQM1

46

DQM2

63

DQM3

136

DQM4

153

DQM5

170

DQM6

187

DQM7

113

WE

115

CAS

110

RAS

73

CKE0

74

CKE1

101

CK0

103

CK0

102

CK1

104

CK1

116

ODT0

120

ODT1

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

200

SDA

202

SCL

197

SA0

201

SA1

199

VDDSPD

1

VREF_DQ

126

VREF_CA

198

EVENT#

30

RESET#

77

NC1

122

NC2

125

NCTEST

DDR3_SODIMM204_0

99

100

105

106

111

112

VDD10

VDD11

VDD12

VDD13

VSS23VSS38VSS49VSS513VSS614VSS719VSS820VSS925VSS1026VSS1131VSS1232VSS1337VSS1438VSS1543VSS1644VSS1748VSS1849VSS1954VSS2055VSS2160VSS2261VSS2365VSS2466VSS2571VSS2672VSS27

VSS1

2

VDD14

151

145

150

155

VDD16

156

123

124

VSS36

VSS34

VSS35

VSS37

VDD17

VDD18

117

118

VDD15

161

162

167

168

172

173

178

179

184

185

189

190

195

196

DIMM2

MB_DATA0

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

VSS29

VSS30

VSS28

127

133

134

128

5

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

D0

MB_DATA1

7

D1

MB_DATA2

15

D2

MB_DATA3

17

D3

MB_DATA4

4

D4

MB_DATA5

6

D5

MB_DATA6

16

D6

MB_DATA7

18

D7

MB_DATA8

21

D8

MB_DATA9

23

D9

MB_DATA10

33

D10

MB_DATA11

35

D11

MB_DATA12

22

D12

MB_DATA13

24

D13

MB_DATA14

34

D14

MB_DATA15

36

D15

MB_DATA16

39

D16

MB_DATA17

41

D17

MB_DATA18

51

D18

MB_DATA19

53

D19

MB_DATA20

40

D20

MB_DATA21

42

D21

MB_DATA22

50

D22

MB_DATA23

52

D23

MB_DATA24

57

D24

MB_DATA25

59

D25

MB_DATA26

67

D26

MB_DATA27

69

D27

MB_DATA28

56

D28

MB_DATA29

58

D29

MB_DATA30

68

D30

MB_DATA31

70

D31

MB_DATA32

129

D32

MB_DATA33

131

D33

MB_DATA34

141

D34

MB_DATA35

143

D35

MB_DATA36

130

D36

MB_DATA37

132

D37

MB_DATA38

140

D38

MB_DATA39

142

D39

MB_DATA40

147

D40

MB_DATA41

149

D41

MB_DATA42

157

D42

MB_DATA43

159

D43

MB_DATA44

146

D44

MB_DATA45

148

D45

MB_DATA46

158

D46

MB_DATA47

160

D47

MB_DATA48

163

D48

MB_DATA49

165

D49

MB_DATA50

175

D50

MB_DATA51

177

D51

MB_DATA52

164

D52

MB_DATA53

166

D53

MB_DATA54

174

D54

MB_DATA55

176

D55

MB_DATA56

181

D56

MB_DATA57

183

D57

MB_DATA58

191

D58

MB_DATA59

193

D59

MB_DATA60

180

D60

MB_DATA61

182

D61

MB_DATA62

192

D62

MB_DATA63

194

D63

MB_DQS#0

10

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

VSS31

VSS32

VSS33

GND1

138

139

144

205

MB_DQS#1

27

MB_DQS#2

45

MB_DQS#3

62

MB_DQS#4

135

MB_DQS#5

152

MB_DQS#6

169

MB_DQS#7

186

GND2

206

MB_DATA[63:0] {9}

MB_DQS#[7:0] {9}

+V1.5 +V1.5

R50

R48

R48 1K,1%

1K,1%

R0402

VREFB_DDR3

R47

R47 1K,1%

1K,1%

R0402

A A

5

R0402

VREFB_DDR3 {13}

4

R50 1K,1%

1K,1%

R0402

R51

R51 1K,1%

1K,1%

R0402

C53

0.1UF/25V,Y5V

C0402

VREFB_CA

C43

2.2UF/10V,X7R

C0805

TOPSTAR TECHNOLOGY

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Page Name

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Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

bent DDR3 SODIMM1

DDR3 SODIMM1

C46

1

A

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D D

C C

+V3.3S

0.1UF/25V,Y5V

0.1UF/25V,Y5V C42

C42

C0402

B B

C41

2.2UF/10V,X7R

C0805

MA_DM[7:0]{9}

MA_A_CAS#{9} MA_A_RAS#{9}

M_CLK_DDR0{9} M_CLK_DDR#0{9} M_CLK_DDR1{9} M_CLK_DDR#1{9}

MA_DQS[7:0]{9}

SMB_DATA_S{6,15,23,40,41} SMB_CLK_S{6,15,23,40,41}

VREFA_DDR3

MA_A_A[15:0]{9}

MA_A_BS0{9} MA_A_BS1{9} MA_A_BS2{9}

M_CS#0{9} M_CS#1{9}

MA_A_WE#{9}

M_CKE0{9} M_CKE1{9}

M_ODT0{9} M_ODT1{9}

R54 0R54 0

0.1UF/25V,Y5V

C52

C0402

MA_DQS0 MA_DQS1 MA_DQS2 MA_DQS3 MA_DQS4 MA_DQS5 MA_DQS6 MA_DQS7

close to DDR pin

DIM_EXTTS#0{8}

DDR3_DRAMRST#{8,15}

+V3.3S {6,8,15,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5 {8,11,15,49,56,57} +V0.75S {15,49,56}

MA_A_A0

98

MA_A_A1

97

MA_A_A2

96

MA_A_A3

95

MA_A_A4

92

MA_A_A5

91

MA_A_A6

90

MA_A_A7

86

MA_A_A8

89

MA_A_A9

85

MA_A_A10

107

MA_A_A11

84

MA_A_A12

83

MA_A_A13

119

MA_A_A14

80

MA_A_A15

78

109 108

79

114 121

MA_DM0

11

MA_DM1

28

MA_DM2

46

MA_DM3

63

MA_DM4

136

MA_DM5

153

MA_DM6

170

MA_DM7

187 113

115 110

73 74

101 103 102 104

116 120

12 29 47

64 137 154 171 188

200

VREFA_CA

202 197

201 199

1

126 198

30

77 122 125

DDR3_SODIMM204_0

R65 10K R0402R65 10K R0402 R64 10K R0402R64 10K R0402

C50

2.2UF/10V,X7R

C0805

4

+V1.5+V0.75S

203

204

VTT1

VTT2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15

BA0 BA1 BA2

CS0 CS1

DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7

WE CAS RAS

CKE0 CKE1

CK0 CK0 CK1 CK1

ODT0 ODT1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

SDA SCL

SA0 SA1

VDDSPD VREF_DQ

VREF_CA EVENT#

RESET# NC1

NC2 NCTEST

99

100

105

106

111

112

117

VDD175VDD276VDD381VDD482VDD587VDD688VDD793VDD894VDD9

VSS1

2

VDD10

VDD11

VDD12

VDD13

VDD14

VSS23VSS38VSS49VSS513VSS614VSS719VSS820VSS925VSS1026VSS1131VSS1232VSS1337VSS1438VSS1543VSS1644VSS1748VSS1849VSS1954VSS2055VSS2160VSS2261VSS2365VSS2466VSS2571VSS2672VSS27

VDD15

3

+V1.5

12

C96

151

145

150

155

156

161

162

167

168

172

173

178

179

184

185

189

190

195

118

123

124

VSS36

VSS34

VSS35

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VDD16

VDD17

VDD18

VSS43

VSS28

127

133

128

196

DIMM1

MA_DATA0

VSS44

VSS45

VSS29

VSS30

134

5

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

D0

MA_DATA1

7

D1

MA_DATA2

15

D2

MA_DATA3

17

D3

MA_DATA4

4

D4

MA_DATA5

6

D5

MA_DATA6

16

D6

MA_DATA7

18

D7

MA_DATA8

21

D8

MA_DATA9

23

D9

MA_DATA10

33

D10

MA_DATA11

35

D11

MA_DATA12

22

D12

MA_DATA13

24

D13

MA_DATA14

34

D14

MA_DATA15

36

D15

MA_DATA16

39

D16

MA_DATA17

41

D17

MA_DATA18

51

D18

MA_DATA19

53

D19

MA_DATA20

40

D20

MA_DATA21

42

D21

MA_DATA22

50

D22

MA_DATA23

52

D23

MA_DATA24

57

D24

MA_DATA25

59

D25

MA_DATA26

67

D26

MA_DATA27

69

D27

MA_DATA28

56

D28

MA_DATA29

58

D29

MA_DATA30

68

D30

MA_DATA31

70

D31

MA_DATA32

129

D32

MA_DATA33

131

D33

MA_DATA34

141

D34

MA_DATA35

143

D35

MA_DATA36

130

D36

MA_DATA37

132

D37

MA_DATA38

140

D38

MA_DATA39

142

D39

MA_DATA40

147

D40

MA_DATA41

149

D41

MA_DATA42

157

D42

MA_DATA43

159

D43

MA_DATA44

146

D44

MA_DATA45

148

D45

MA_DATA46

158

D46

MA_DATA47

160

D47

MA_DATA48

163

D48

MA_DATA49

165

D49

MA_DATA50

175

D50

MA_DATA51

177

D51

MA_DATA52

164

D52

MA_DATA53

166

D53

MA_DATA54

174

D54

MA_DATA55

176

D55

MA_DATA56

181

D56

MA_DATA57

183

D57

MA_DATA58

191

D58

MA_DATA59

193

D59

MA_DATA60

180

D60

MA_DATA61

182

D61

MA_DATA62

192

D62

MA_DATA63

194

D63

MA_DQS#0

10

DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

VSS31

VSS32

VSS33

GND1

138

139

144

205

206

GND2

MA_DQS#1

27

MA_DQS#2

45

MA_DQS#3

62

MA_DQS#4

135

MA_DQS#5

152

MA_DQS#6

169

MA_DQS#7

186

MA_DATA[63:0] {9}

MA_DQS#[7:0] {9}

C96

1

+

ns

CT7343_19

220uF/2.5V,POSCAP

+V1.5

C208

10uF/6.3V,X5R

Layout note:

+V0.75S

C51

1uF/10V,X7R

C37

C0402

0.1UF/25V,Y5V

2.2UF/10V,X7R

C23

C0402

0.1UF/25V,Y5V

2

C33

C417

ns

C0805

2.2UF/10V,X7R

0.1UF/25V,Y5V

C419

C0805

2.2UF/10V,X7R

电容靠近

DDR slot VDD PIN

C72

1uF/10V,X7R

C26

C0402

2.2UF/10V,X7R

C418

C418 10uF/6.3V,X5R

10uF/6.3V,X5R

2.2UF/10V,X7R

C32

C32 1uF/10V,X7R

1uF/10V,X7R

C22

C0805

0.1UF/25V,Y5V

C213

C0805

0.1UF/25V,Y5V

C36

C49

ns

C0402

C0805

2.2UF/10V,X7R

1, A minimum of 9 high frequency capacitors are recommended to be placed near each SO-DIMM of DDR2. 2, 2.2µF*5 per DIMM,0.1µF*4 per DIMM,330µF*1 per DIMM

C24

C0402

C18

C18 1uF/10V,X7R

1uF/10V,X7R

1

+V1.5

R52

R52 1K,1%

1K,1%

R0402

VREFA_DDR3

R53

R53 1K,1%

1K,1%

R0402

A A

5

VREFA_DDR3 {13}

+V1.5

R435

R435 1K,1%

1K,1%

R0402

R436

R436 1K,1%

1K,1%

R0402

C328

0.1UF/25V,Y5V

C0402

VREFA_CAVREFA_CA

4

C327

2.2UF/10V,X7R

C0805

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

bent DDR3 SODIMM0

DDR3 SODIMM0

C46

1

A

16 59Friday, November 27, 2009

A

of

5

4

3

+V3.3GPU {20,21,33,34,52,57} +VGA_CORE {52} +V1.05GPU {18,19,20,57}

2

1

GR53

GR53 10K

10K

S_Top

GPU_RST#

PM

+V3.3GPU

GR41

GR41 10K

10K

S_Bot

PCIE_CLKREQ

PM

GR16 0

+V3.3GPU

S_Top

ns

GC3

0.1uF/10V,X7R

53

GU2

S_Top

VCC

PEG_RXP15 PEG_RXN15

PEG_NV_RXP15 PEG_NV_RXN15

PEG_RXP14 PEG_RXN14

PEG_NV_RXP14 PEG_NV_RXN14

PEG_RXP13 PEG_RXN13

PEG_NV_RXP13 PEG_NV_RXN13

PEG_RXP12 PEG_RXN12

PEG_NV_RXP12 PEG_NV_RXN12

PEG_RXP11 PEG_RXN11

PEG_NV_RXP11 PEG_NV_RXN11

PEG_RXP10 PEG_RXN10

PEG_NV_RXP10 PEG_NV_RXN10

PEG_RXP9 PEG_RXN9

PEG_NV_RXP9 PEG_NV_RXN9

PEG_RXP8 PEG_RXN8

PEG_NV_RXP8 PEG_NV_RXN8

PEG_RXP7 PEG_RXN7

PEG_NV_RXP7 PEG_NV_RXN7

PEG_RXP6 PEG_RXN6

PEG_NV_RXP6 PEG_NV_RXN6

PEG_RXP5 PEG_RXN5

PEG_NV_RXP5 PEG_NV_RXN5

PEG_RXP4 PEG_RXN4

PEG_NV_RXP4 PEG_NV_RXN4

PEG_RXP3 PEG_RXN3

PEG_NV_RXP3 PEG_NV_RXN3

PEG_RXP2 PEG_RXN2

PEG_NV_RXP2 PEG_NV_RXN2

PEG_RXP1 PEG_RXN1

PEG_NV_RXP1 PEG_NV_RXN1

PEG_RXP0 PEG_RXN0

PEG_NV_RXP0 PEG_NV_RXN0

PCIE_CLKREQ{23} CLK_PCIE_N11M{23}

CLK_PCIE_N11M#{23}

1 2

GND

SN74AHC1G08DBV

ns

SN74AHC1G08DBV

ns

SOT23_5

SOT23_5 S_Top

S_Top

GC1500.1UF/10V,X7R

S_Bot

GC1000.1UF/10V,X7R

S_Top

GC1530.1UF/10V,X7R

S_Bot

GC1050.1UF/10V,X7R

S_Top

GC1570.1UF/10V,X7R

S_Bot

GC1100.1UF/10V,X7R

S_Top

GC1600.1UF/10V,X7R

S_Bot

GC1160.1UF/10V,X7R

S_Top

GC1660.1UF/10V,X7R

S_Bot

GC1200.1UF/10V,X7R

S_Top

GC1710.1UF/10V,X7R

S_Bot

GC1250.1UF/10V,X7R

S_Top

GC1740.1UF/10V,X7R

S_Bot

GC1290.1UF/10V,X7R

S_Top

GC1800.1UF/10V,X7R

S_Bot

GC1330.1UF/10V,X7R

S_Top

4

GC1490.1UF/10V,X7R

S_Bot

PM

GC97 0.1UF/10V,X7R

S_Top

PM

GC1520.1UF/10V,X7R

S_Bot

PM

GC1040.1UF/10V,X7R

S_Top

PM

GC1560.1UF/10V,X7R

S_Bot

PM

GC1080.1UF/10V,X7R

S_Top

PM

GC1610.1UF/10V,X7R

S_Bot

PM

GC1130.1UF/10V,X7R

S_Top

PM

GC1650.1UF/10V,X7R

S_Bot

PM

GC1190.1UF/10V,X7R

S_Top

PM

GC1700.1UF/10V,X7R

S_Bot

PM

GC1240.1UF/10V,X7R

S_Top

PM

GC1760.1UF/10V,X7R

S_Bot

PM

GC1280.1UF/10V,X7R

S_Top

PM

GC1790.1UF/10V,X7R

S_Bot

PM

GC1340.1UF/10V,X7R

S_Top

PM

EC_GPU_RST#{43}

BUF_PLT_RST#{8,26,38,39,40,41,43,44}

GR2 is used for test only, so it can be unstuff for cost saving.

GPU_RST#

GR42

GR42 100K

100K

S_Bot

PCIE_CLKREQ

GR20 200,1% R0402

ns

S_Top

PEG_NV_TXP15 PEG_NV_TXN15

PM

PEG_NV_TXP14 PEG_NV_TXN14

PM

PEG_NV_TXP13 PEG_NV_TXN13

PM

PEG_NV_TXP12 PEG_NV_TXN12

PM

PEG_NV_TXP11 PEG_NV_TXN11

PM

PEG_NV_TXP10 PEG_NV_TXN10

PM

PEG_NV_TXP9 PEG_NV_TXN9

PM

PEG_NV_TXP8 PEG_NV_TXN8

PM

PEG_NV_TXP7 PEG_NV_TXN7

PM

PEG_NV_TXP6 PEG_NV_TXN6

PM

PEG_NV_TXP5 PEG_NV_TXN5

PM

PEG_NV_TXP4 PEG_NV_TXN4

PM

PEG_NV_TXP3 PEG_NV_TXN3

PM

PEG_NV_TXP2 PEG_NV_TXN2

PM

PEG_NV_TXP1 PEG_NV_TXN1

PM

PEG_NV_TXP0 PEG_NV_TXN0

PM

CLOSE TO N10

AM16 AR13

AJ17 AJ18

AR16 AR17

AL17 AM17

AP17 AN17

AM18 AM19

AN19 AP19

AL19 AK19

AR19 AR20

AL20 AM20

AP20 AN20

AM21 AM22

AN22 AP22

AL22 AK22

AR22 AR23

AL23 AM23

AP23 AN23

AM24 AM25

AN25 AP25

AL25 AK25

AR25 AR26

AL26 AM26

AP26 AN26

AM27 AM28

AN28 AP28

AL28 AK28

AR28 AR29

AK29 AL29

AP29 AN29

AM29 AM30

AN31 AP31

AM31 AM32

AR31 AR32

AN32 AP32

AR34 AP34

U3A

PEX_RST# PEX_CLKREQ

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PEX_REFCLK PEX_REFCLK#

PEX_TX0 PEX_TX0#

PEX_RX0 PEX_RX0#

PEX_TX1 PEX_TX1#

PEX_RX1 PEX_RX1#

PEX_TX2 PEX_TX2#

PEX_RX2 PEX_RX2#

PEX_TX3 PEX_TX3#

PEX_RX3 PEX_RX3#

PEX_TX4 PEX_TX4#

PEX_RX4 PEX_RX4#

PEX_TX5 PEX_TX5#

PEX_RX5 PEX_RX5#

PEX_TX6 PEX_TX6#

PEX_RX6 PEX_RX6#

PEX_TX7 PEX_TX7#

PEX_RX7 PEX_RX7#

PEX_TX8 PEX_TX8#

PEX_RX8 PEX_RX8#

PEX_TX9 PEX_TX9#

PEX_RX9 PEX_RX9#

PEX_TX10 PEX_TX10#

PEX_RX10 PEX_RX10#

PEX_TX11 PEX_TX11#

PEX_RX11 PEX_RX11#

PEX_TX12 PEX_TX12#

PEX_RX12 PEX_RX12#

PEX_TX13 PEX_TX13#

PEX_RX13 PEX_RX13#

PEX_TX14 PEX_TX14#

PEX_RX14 PEX_RX14#

PEX_TX15 PEX_TX15#

PEX_RX15 PEX_RX15#

NB10_G128

S_Bot

PM

PCI_EXPRESS

PEX_IOVDD_01 PEX_IOVDD_02 PEX_IOVDD_03 PEX_IOVDD_04 PEX_IOVDD_05

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9

PEX_IOVDDQ_10

PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24 PEX_IOVDDQ_25

PEX_SVDD_3V3_1 PEX_SVDD_3V3_2

VDD_SENSE1 VDD_SENSE2

VDD_SENSE3 GND_SENSE1 GND_SENSE2 GND_SENSE3

PEX_PLLVDD

PEX_CAL_PU_GND/NC

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5

PEX_TERMP

TESTMODE

AK16 AK17 AK21 AK24 AK27

PEX_IOVDD+PEX_IOVDDQ:MAX:2200mA

AG11 AG12 AG13 AG15

0.1uF/10V,X7R

AG16 AG17

S_Top

AG18 AG22 AG23 AG24

AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16

A2

NC_1

AA4

NC_2

AB4

NC_3

AB7

NC_4

AC5

NC_5

AD6

NC_6

AF6

NC_7

AG6

NC_8

AJ5

NC_9

AK15

NC_10

AL7

NC_11

E7

NC_14

H32

NC_16

M7

NC_17

P6

NC_18

U7

NC_21

V6

NC_22

Y4

NC_23

F7 AG19

J10 J11 J12 J13 J9

D35 P7 AD20 AD19

R505 0 R0402

R7 E35

PM

S_Bot

MAX:120mA

AG14

T16 ns

AG20

GR19 2.49K,1% R0402

AG21

PM

GR29 10K R0402

AP35

S_Top

S_Top S_Top

S_Top

GR28 10K R0402

PM

S_Top

S46 VerA:Add reserved pull up resistor on TESTMODE follewed nvidia suggest

Under GPU Near GPU

GC71

GC84

C0402

0.1uF/10V,X7R

0.1uF/10V,X7R 1uF/10V,X5R

1uF/10V,X5R

S_Top

PM

S_Top

PM

Under GPU Near GPU

GC98

GC82

GC69

C0402

0.1uF/10V,X7R

0.1uF/10V,X7R 1uF/10V,X5R

1uF/10V,X5R

S_Top

PM

S_Top

PM

MAX:19.6A

GC26

GC35

C0402

0.047uF/16V,X7R

S_Top

0.047uF/16V,X7R

S_Top

0.01uF/25V,X7R

S_Top

0.01uF/25V,X7R

S_Top

0.22uF/10V,X7R

0.047uF/16V,X7R

S_Top

PM

S_Top

PM

GC56

GC78

C0402

0.022uF/16V,X7R

PM

S_Top

PM

GC70

GC75

C0402

0.01uF/25V,X7R

S_Top

PM

S_Top

PM

GC64

GC72

C0402

4700pF/25V,X7R

S_Top

PM

MAX:120mA

0.1uF/10V,X7R

S_Top

PM

0.1uF/10V,X7R

S_Top

PM

GC13

PM

0.1uF/10V,X7R

S_Top

PM

MAX:180mA

NVVDD_SENSE {52}

Near GPU

1uF/10V,X7R

S_Top

+V3.3GPU

ns

GC73

C0402

1uF/10V,X5R

S_Top

PM

GC65

C0402

1uF/10V,X5R

S_Top

PM

GC66

PM

GC51

C0402

0.022uF/16V,X7R

S_Top

PM

GC59

C0402

PM

GC55

C0402

4700pF/25V,X7R

S_Top

PM

GC32

GC18

GC8

C0603

PM

Under GPU

0.22uF/10V,X7R

S_Top

PM

0.01uF/25V,X7R

S_Top

PM

Near GPUUnder GPU

PM

GC6

4.7uF/10V,X5R

S_Top

PM

+V1.05GPU

GC87

GC93

C0805

4.7uF/10V,X5R

S_Top

GC90

C0805

4.7uF/10V,X5R

S_Top

GC39

C0603

GC62

C0402

0.022uF/16V,X7R

S_Top

GC49

GC23

C0603

1uF/10V,X7R

S_Top

GFB1

1 2

C0805

GC87

C0805

10uF/6.3V,X5R

S_Top

PM

+V1.05GPU

GC91

GC102

C0805

10uF/6.3V,X5R

4.7uF/10V,X5R

S_Top

PM

+VGA_CORE

Near GPU

GC50

GC31

C0805

1uF/10V,X5R

4.7uF/10V,X5R

S_Top

PM

GC60

0.022uF/16V,X7R

S_Top

PM

+V3.3GPU

GC11

C0805

4.7uF/10V,X5R

S_Top

PM

S46 VerA:Delete some caps followed N10M DG 090327

+V1.05GPU

FB0603

120ohm@100MHz,500mA

PM

S_Top

Layout Notice

Under GPU: The total trace length measured from GPU ball to cap is no more than 150 mil Near GPU: The total trace length measured from GPU ball to cap is no more than 750 mil

U3F

+VGA_CORE +VGA_CORE

NVVDD

AB11

VDD_001

AB13

VDD_002

AB15

VDD_003

AB17

VDD_004

AB19

VDD_005

AB21

VDD_006

AB23

VDD_007

AB25

VDD_008

AC11

VDD_009

AC12

VDD_010

AC13

VDD_011

AC14

VDD_012

AC15

VDD_013

AC16

VDD_014

AC17

VDD_015

AC18

VDD_016

AC19

VDD_017

AC20

VDD_018

AC21

VDD_019

AC22

VDD_020

AC23

VDD_021

AC24

VDD_022

AC25

VDD_023

AD12

VDD_024

AD14

VDD_025

AD16

VDD_026

AD18

VDD_027

AD22

VDD_028

AD24

VDD_029

L11

VDD_030

L12

VDD_031

L13

VDD_032

L14

VDD_033

L15

VDD_034

L16

VDD_035

L17

VDD_036

L18

VDD_037

L19

VDD_038

L20

VDD_039

L21

VDD_040

L22

VDD_041

L23

VDD_042

L24

VDD_043

L25

VDD_044

M12

VDD_045

M14

VDD_046

M16

VDD_047

M18

VDD_048

M20

VDD_049

M22

VDD_050

M24

VDD_051

P11

VDD_052

P13

VDD_053

P15

VDD_054

P17

VDD_055

P19

VDD_056

NB10_G128

S_Bot

PM

VDD_057 VDD_058 VDD_059 VDD_060 VDD_061 VDD_062 VDD_063 VDD_064 VDD_065 VDD_066 VDD_067 VDD_068 VDD_069 VDD_070 VDD_071 VDD_072 VDD_073 VDD_074 VDD_075 VDD_076 VDD_077 VDD_078 VDD_079 VDD_080 VDD_081 VDD_082 VDD_083 VDD_084 VDD_085 VDD_086 VDD_087 VDD_088 VDD_089 VDD_090 VDD_091 VDD_092 VDD_093 VDD_094 VDD_095 VDD_096 VDD_097 VDD_098 VDD_099 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 VDD_111

P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24

U3G

GND

E15

GND_096

E18

PM

GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095

NB10_G128

S_Bot

GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191

E24 E27 E30 E6 E9 F2 F31 F34 F5 J2 J31 J34 J5 L9 M11 M13 M15 M17 M19 M2 M21 M23 M25 M31 M34 M5 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R31 R34 R5 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V12 V14 V16 V18 V2 V20 V22 V24 V31 V5 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25

AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19

AA2 AA20 AA21 AA22 AA23 AA24 AA25 AA34

AA5 AB12 AB14 AB16 AB18 AB20 AB22 AB24

AC9 AD11 AD13 AD15 AD17

AD2 AD21 AD23 AD25 AD31 AD34

AD5 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25

AG2 AG31 AG34

AG5

AK2 AK31 AK34

AK5 AL12 AL15 AL18 AL21 AL24 AL27 AL30

AL6

AL9

AN2 AN34 AP12 AP15 AP18 AP21 AP24 AP27

AP3 AP30 AP33

AP6

AP9

B12

B15

B21

B24

B27

B3 B30 B33

B6

B9

C2 C34 E12

D D

C C

B B

+V3.3GPU

PM

PEG_NV_RXP[15:0]{7} PEG_NV_RXN[15:0]{7}

PEG_RXP[15:0]{7}

PEG_RXN[15:0]{7}

VerA: all PCIE singala lane reversal llh0523

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

D

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

1

bent N10M PCIE&PWR&GND

N10M PCIE&PWR&GND

C46

A

17 59Friday, November 27, 2009

of

5

U3B

FBAD_0

L32

FBA_D0

FBAD_1 FBAD_2 FBAD_3 FBAD_4 FBAD_5 FBAD_6 FBAD_7 FBAD_8 FBAD_9 FBAD_10 FBAD_11 FBAD_12

+V1.5GPU

GR11

GR11 1K,1%

1K,1%

ns

GR8

2.49K,1%

ns

FBA_CLK0

FBA_CLK0#

FBAD_13 FBAD_14 FBAD_15 FBAD_16 FBAD_17 FBAD_18 FBAD_19 FBAD_20 FBAD_21 FBAD_22 FBAD_23 FBAD_24 FBAD_25 FBAD_26 FBAD_27 FBAD_28 FBAD_29 FBAD_30 FBAD_31 FBAD_32 FBAD_33 FBAD_34 FBAD_35 FBAD_36 FBAD_37 FBAD_38 FBAD_39 FBAD_40 FBAD_41 FBAD_42 FBAD_43 FBAD_44 FBAD_45 FBAD_46 FBAD_47 FBAD_48 FBAD_49 FBAD_50 FBAD_51 FBAD_52 FBAD_53 FBAD_54 FBAD_55 FBAD_56 FBAD_57 FBAD_58 FBAD_59 FBAD_60 FBAD_61 FBAD_62 FBAD_63

FBADQM_0 FBADQM_1 FBADQM_2 FBADQM_3 FBADQM_4 FBADQM_5 FBADQM_6 FBADQM_7

FBADQS_0 FBADQS_1 FBADQS_2 FBADQS_3 FBADQS_4 FBADQS_5

FBADQS_6

FBADQS_7

FBADQS_0# FBADQS_1# FBADQS_2# FBADQS_3# FBADQS_4# FBADQS_5# FBADQS_6# FBADQS_7#

GC44

0.01uF/16V,X7R

ns

+V1.5GPU

GC80

0.1uF/10V,X7R

PM

GC189

0.1uF/10V,X7R

PM

D D

C C

B B

A A

AG30 AG32 AH31 AF31 AF30 AE30 AC32 AD30 AN33

AL31 AM33 AL33 AK30 AK32

AJ30 AH30 AH33 AH35 AH34 AH32

AJ33 AL35 AM34 AM35 AF33 AE32 AF34 AE35 AE34 AE33 AB32 AC35

AF32 AL32 AL34 AF35

AE31

AJ32

AJ34 AC33

AD32

AJ31

AJ35 AC34

AG29 AH29 AD29 AE29

N33 L33 N34 N35 P35 P33 P34 K35 K33 K34 H33 G34 G33 E34 E33 G31 F30 G30 G32 K30 K32 H30 K31 L31 L30 M32 N30 M30 P31 R32 R30

P32 H34 J30 P30

L34 H35 J32 N31

L35 G35 H31 N32

P29 R29 L29 M29

J27

5

FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_WDS0/NC FBA_WDS0#/NC FBA_WDS1/NC FBA_WDS1#/NC FBA_WDS2/NC FBA_WDS2#/NC FBA_WDS3/NC FBA_WDS3#/NC

FB_VREF

NB10_G128

PM

GC139

0.1uF/10V,X7R

PM

GC92

0.1uF/10V,X7R

PM

FBA_ODT0

GR30

GR30 10K

10K

PM

R558

R558 243,1%

243,1%

PM

FPA

PM

GC135

0.01uF/16V,X7R

GC168

0.01uF/16V,X7R

FBVDDQ0 FBVDDQ1 FBVDDQ2 FBVDDQ3 FBVDDQ4 FBVDDQ5 FBVDDQ6 FBVDDQ7 FBVDDQ8

FBVDDQ9 FBVDDQ10 FBVDDQ11 FBVDDQ12 FBVDDQ13 FBVDDQ14 FBVDDQ15 FBVDDQ16 FBVDDQ17 FBVDDQ18 FBVDDQ19 FBVDDQ20 FBVDDQ21 FBVDDQ22 FBVDDQ23 FBVDDQ24 FBVDDQ25 FBVDDQ26

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9

FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27

FBA_CMD28 FBA_CMD29/NC FBA_CMD30/NC

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

FBA_DEBUG

FB_DLLAVDD0 FB_PLLAVDD0

FBB_ODT0

GR37

GR37 10K

10K

PM

FBA_CLK1

FBA_CLK1#

J23 J24 J29 AA27 AA29 AA31 AB27 AB29 AC27 AD27 AE27 AJ28 B18 E21 G17 G18 G22 G8 G9 H29 J14 J15 J16 J17 J20 J21 J22

V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29

T32 T31 AC31 AC30

T30

AG27 AF27

GC81

0.1uF/10V,X7R

PM

GC88

0.1uF/10V,X7R

PM

MAX:5700mA

FBA_A4 FBA_RAS# FBA_A5 FBA_BA1

FBB_A2 FBB_A4 FBB_A3

FBB_CS# FBA_A11 FBA_CAS#

FBA_WE# FBA_BA0 FBB_A5 FBA_A12 FBA_RST FBA_A7 FBA_A10 FBA_CKE FBA_A0 FBA_A9 FBA_A6 FBA_A2 FBA_A8 FBA_A3 FBA_A1 FBA_A13 FBA_BA2

FBB_ODT0

FBA_CS0#

FBA_ODT0

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

GC190

1uF/10V,X7R

PM

GC144

1uF/10V,X7R

PM

FBB_CKE

T17 nsT17 ns

MAX:100mA

C0603

GC74

0.01uF/16V,X7R

PM

GC83

0.01uF/16V,X7R

0.047uF/16V,X7R

PM

1uF/10V,X5R

GC182

C0603

1uF/10V,X7R

PM

GC140

C0603

1uF/10V,X7R

PM

0.047uF/16V,X7R

PM

Near GPU

GC85

PM

R616

R616 243,1%

243,1%

PM

GC76

GC77

PM

GC86

4.7uF/10V,X5R

C0805

PM

GC79

C0805

4.7uF/10V,X5R

GC131

C0805

4.7uF/10V,X5R

GC53

0.1uF/10V,X7R

GC48

0.1uF/10V,X7R

GFB8

120ohm@100MHz,500mA

1 2

PM

Near GPUUnder GPU

PM

FB0603

+

+V1.5GPU

GC68

4.7uF/10V,X5R

+V1.05GPU

GC138

GC138 150UF/2.5V

150UF/2.5V

CT7343_28

ns

+V1.5GPU

PM

4

GC115

0.1uF/10V,X7R

PM

GC142

0.1uF/10V,X7R

4

PM

GC141

0.1uF/10V,X7R

PM

GC147

0.1uF/10V,X7R

FBB_VREF3

FBB_VREF1

FBAD_6 FBAD_1 FBAD_7 FBAD_4 FBAD_3 FBAD_0 FBAD_5 FBAD_2 FBADQS_0# FBADQS_0

FBAD_60 FBAD_59 FBAD_61 FBAD_56 FBAD_63 FBAD_58 FBAD_62 FBAD_57

FBADQS_7

PM

+V1.5GPU

GC151

0.01uF/16V,X7R

GC187

0.01uF/16V,X7R

A1 C1 F1 D2 H2 A8 C9 E9 H9

N1 R1 B2 K2 G7 K8 D9 N9 R9

B1 D1 G1 E2 D8 E8 B9 F9 G9

E1 M1 P1 T1 J2 B3 G8 J8 A9 M9 P9 T9

H1 M8

D7 C3 C8 C2 A7 A2 B8 A3 B7 C7

A1 C1 F1 D2 H2 A8 C9 E9 H9

N1 R1 B2 K2 G7 K8 D9 N9 R9

B1 D1 G1 E2 D8 E8 B9 F9 G9

E1 M1 P1 T1 J2 B3 G8 J8 A9 M9 P9 T9

H1 M8

D7 C3 C8 C2 A7 A2 B8 A3 B7 C7

PM

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

VREFDQ VREFCA

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU# DQSU

VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

VREFDQ VREFCA

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DQSU# DQSU

GC148

0.1uF/10V,X7R

GC186

0.1uF/10V,X7R

3

+V1.05GPU {17,19,20,57} +V1.5GPU {19,57}

U11

DDR3

U29

DDR3

1uF/10V,X7R

PM

GC137

GC137 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

FBA_A0

N3

A0

FBA_A1

P7

A1

FBA_A2

P3

A2

FBA_A3

N2

A3

FBA_A4

P8

A4

FBA_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

A15/BA3

FBA_ODT0

K1

ODT0

J1

ODT1

FBA_CS0#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

RESET#

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_0

D3

DMU

FBADQM_3

E7

DML

FBA_CLK0

J7

CK

FBA_CLK0#

K7

CK#

FBA_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_25

E3

DQL0

FBAD_27

F7

DQL1

FBAD_28

F2

DQL2

FBAD_29

F8

DQL3

FBAD_26

H3

DQL4

FBAD_30

H8

DQL5

FBAD_24

G2

DQL6

FBAD_31

H7

DQL7

FBADQS_3#

G3

DQSL#

FBADQS_3

F3

DQSL

FBA_A0

N3

A0

FBA_A1

P7

A1

FBB_A2

P3

A2

FBB_A3

N2

A3

FBB_A4

P8

A4

FBB_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

A15/BA3

FBB_ODT0

K1

ODT0

J1

ODT1

FBB_CS#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

RESET#

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_7

D3

DMU

FBADQM_4

E7

DML

FBA_CLK1

J7

CK

FBA_CLK1#

K7

CK#

FBB_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_32

E3

DQL0

FBAD_36

F7

DQL1

FBAD_33

F2

DQL2

FBAD_37

F8

DQL3

FBAD_35

H3

DQL4

FBAD_39

H8

DQL5

FBAD_34

G2

DQL6

FBAD_38

H7

DQL7

FBADQS_4#FBADQS_7#

G3

DQSL#

FBADQS_4

F3

DQSL

GC175

GC122

GC122 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

GC95

GC114

1uF/10V,X7R

4.7uF/10V,X5R

C0603

C0805

PM

GC99

4.7uF/10V,X5R

C0805

GR48

GR48 243,1%

243,1%

PM

GR39

GR39 243,1%

243,1%

PM

FBB_CKE

FBA_CKE FBA_RST

待确定

3

GR31

GR38

10K

PM

+V1.5GPU

PM

+V1.5GPU +V1.5GPU

GR51

GR51 1K,1%PM

1K,1%PM

FBB_VREF3 FBB_VREF4

GR50

GR50 1K,1%

1K,1%

PM

GR26

GR26 1K,1%

1K,1%

FBB_VREF1

GR25

GR25 1K,1%

1K,1%

PM

GC188

0.01uF/16V,X7R

GR33

GR33 10K

10K

GC89

0.01uF/16V,X7R

+V1.5GPU

PM

GR46

GR46 1K,1%

1K,1%

FBB_VREF2

GR47

GR47 1K,1%

1K,1%

PM

GC163

0.01uF/16V,X7R

PM

GR34

GR34 1K,1%

1K,1%

GR36

GR36 1K,1%

1K,1%

GC136

0.01uF/16V,X7R

PM

2

FBB_VREF2

FBB_VREF4

2

FBAD_13 FBAD_11 FBAD_14 FBAD_8 FBAD_12 FBAD_10 FBAD_15 FBAD_9 FBADQS_1# FBADQS_1

FBAD_48 FBAD_52 FBAD_50 FBAD_54 FBAD_51 FBAD_55 FBAD_49 FBAD_53 FBADQS_6# FBADQS_6

+V1.5GPU

1

U26

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

PM

U13

A1

VDDQ0

C1

VDDQ1

F1

VDDQ2

D2

VDDQ3

H2

VDDQ4

A8

VDDQ5

C9

VDDQ6

E9

VDDQ7

H9

VDDQ8

N1

VDD1

R1

VDD2

B2

VDD3

K2

VDD4

G7

VDD5

K8

VDD6

D9

VDD7

N9

VDD8

R9

VDD9

B1

VSSQ0

D1

VSSQ1

G1

VSSQ2

E2

VSSQ3

D8

VSSQ4

E8

VSSQ5

B9

VSSQ6

F9

VSSQ7

G9

VSSQ8

E1

VSS0

M1

VSS1

P1

VSS2

T1

VSS3

J2

VSS4

B3

VSS5

G8

VSS6

J8

VSS7

A9

VSS8

M9

VSS9

P9

VSS10

T9

VSS11

H1

VREFDQ

M8

VREFCA

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B7

DQSU#

C7

DQSU

DDR3

PM

A15/BA3

RESET#

A15/BA3

RESET#

FBA_A0

N3

A0

FBA_A1

P7

A1

FBA_A2

P3

A2

FBA_A3

N2

A3

FBA_A4

P8

A4

FBA_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBA_ODT0

K1

ODT0

J1

ODT1

FBA_CS0#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_1

D3

DMU

FBADQM_2

E7

DML

FBA_CLK0

J7

CK

FBA_CLK0#

K7

CK#

FBA_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_23

E3

DQL0

FBAD_19

F7

DQL1

FBAD_20

F2

DQL2

FBAD_16

F8

DQL3

FBAD_22

H3

DQL4

FBAD_17

H8

DQL5

FBAD_21

G2

DQL6

FBAD_18

H7

DQL7

FBADQS_2#

G3

DQSL#

FBADQS_2

F3

DQSL

FBA_A0

N3

A0

FBA_A1

P7

A1

FBB_A2

P3

A2

FBB_A3

N2

A3

FBB_A4

P8

A4

FBB_A5

P2

A5

FBA_A6

R8

A6

FBA_A7

R2

A7

FBA_A8

T8

A8

FBA_A9

R3

A9

FBA_A10

L7

A10

FBA_A11

R7

A11

FBA_A12

N7

A12

FBA_A13

T3

A13

T7

A14

M7

FBB_ODT0

K1

ODT0

J1

ODT1

FBB_CS#

L2

CS0#

L1

CS1#

FBA_BA0

M2

BA0

FBA_BA1

N8

BA1

FBA_BA2

M3

BA2

FBA_RST

T2

FBA_RAS#

J3

RAS#

FBA_CAS#

K3

CAS#

FBA_WE#

L3

WE#

FBADQM_6

D3

DMU

FBADQM_5

E7

DML

FBA_CLK1

J7

CK

FBA_CLK1#

K7

CK#

FBB_CKE

K9

CKE0

J9

CKE1

L8

ZQ0

L9

ZQ1

FBAD_47

E3

DQL0

FBAD_43

F7

DQL1

FBAD_46

F2

DQL2

FBAD_41

F8

DQL3

FBAD_45

H3

DQL4

FBAD_42

H8

DQL5

FBAD_44

G2

DQL6

FBAD_40

H7

DQL7

FBADQS_5#

G3

DQSL#

FBADQS_5

F3

DQSL

GR27

GR27 243,1%

243,1%

PM

待确定

GR49

GR49 243,1%

243,1%

PM

待确定

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

D

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

bent N10M memory1

N10M memory1

C46

A

18 59Friday, November 27, 2009

of

5

U3C

B13

FBC_D0

D13

FBC_D1

A13

FBC_D2

A14

FBC_D3

C16

FBC_D4

B16

FBC_D5

A17

FBC_D6

D16

FBC_D7

C13

FBC_D8

B11

FBC_D9

D D

C C

B B

A A

C11 A11 C10

F10 F12 D11

E11 D12 E13 F13 F14 F15 E16 F16 F17 D29 F27 F28 E28 D26 F25 D24 E25 E32 F32 D33 E31 C33 F29 D30 E29 B29 C31 C29 B31 C32 B32 B35 B34 A29 B28 A28 C28 C26 D25 B25 A25

A16 D10 F11 D15 D27 D34 A34 D28

C14 A10 E10 D14 E26 D32 A32 B26

B14 B10

E14 F26 D31 A31 A26

G14 G15 G11 G12 G27 G28 G24 G25

C8

B8 A8 E8 F8

F9

D8

D9

PM

FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

FBC_WDS0/NC FBC_WDS0#/NC FBC_WDS1/NC FBC_WDS1#/NC FBC_WDS2/NC FBC_WDS2#/NC FBC_WDS3/NC FBC_WDS3#/NC

NB10_G128

S_Bot

5

FPC

FBC_CMD29/NC FBC_CMD30/NC

FB_DLLAVDD1 FB_PLLAVDD1

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBCAL_TERM_GND

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8

FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28

FBC_CLK0# FBC_CLK1#

FBC_DEBUG

FBVDDQ27 FBVDDQ28 FBVDDQ29 FBVDDQ30 FBVDDQ31 FBVDDQ32 FBVDDQ33 FBVDDQ34 FBVDDQ35 FBVDDQ36 FBVDDQ37

FBC_CLK0 FBC_CLK1

N27 P27 R27 T27 U27 U29 V27 V29 V34 W27 Y27

C17 B19 D18 F21 A23 D21 B23 E20 G21 F20 F19 F23 A22 C22 B17 F24 C25 E22 C20 B22 A19 D22 D20 E19 D19 F18 C19 F22 C23 B20 A20

E17 D17 D23 E23

GR6 60.4,1%

G19

J19 J18

GR13 40.2,1%

K27

PM

GR14 40.2,1%

L27

PM

GR15 40.2,1%

M27

R0402

ns

S_Top

PM

R0402

R0402 S_Top

S_Top R0402

R0402 S_Top

S_Top R0402

R0402 S_Top

S_Top

GC45

0.01uF/25V,X7R

S_Top

GC16

0.01uF/25V,X7R

S_Top

+V1.5GPU

4

Under GPU Near GPU

GC109

0.047uF/16V,X7R

S_Top

PM

0.047uF/16V,X7R

S_Top

PM

0.1uF/10V,X7R

S_Top

Place close to balls

40.2 in DG

4

GC28

GC19

ns

GC57

0.1uF/10V,X7R

S_Top

PM

GC143

0.1uF/10V,X7R

S_Top

PM

GC25

0.1uF/10V,X7R

ns

S_Top

MAX:35mA

GC38

4.7uF/10V,X5R

S_Top

PM

GC22

4.7uF/10V,X5R

S_Top

PM

+V1.5GPU

GFB5

120ohm@100MHz,500mA

1 2

S_Top

GC12

C0805

10UF/6.3V,X5R

ns

S_Top

FB0603

ns

+V1.05GPU

3

2

+V1.05GPU {17,18,20,57} +V1.5GPU {18,57}

Page Name

Page Name Size

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

1

TOPSTAR TECHNOLOGY

bent

bent N10M memory2

N10M memory2

C46

1

A

19 59Friday, November 27, 2009

A

of

+V3.3GPU

5

4

3

2

+V3.3GPU {17,21,33,34,52,57} +V1.05GPU {17,18,19,57} +V1.8GPU {57}

1

R44

R41

R40

R40 10K,1%

10K,1%

S_Top

27M_SSC{6}

27M_nonSSC{6}

R41

2.2K

15K,1%

R0402

ns

S_Top

ROM_SI_GPU

ROM_SCLK_GPU

ROM_SO_GPU

R45

R43

15K,1%

R0402

S_Top

PM

ns

Rom_SI: -Hynix 32Mx32 (pull-down 15K)

-Samsung 32MX32 (pull-down 20K)

33 GR32

PM/SSC

PM

ADD pull low by bent 091022

5

S_Top

33GR35

S_Top

XTALOUTBUFF_T12XTALOUTBUFF_T12

GR40

GR40 10K

10K

S_Bot

27M_nonSSC_GPU

GR52

GR52 10K

10K

S_Bot

+V3.3GPU

GR1 10K

GR2 10K

PM

+V1.05GPU

ROM_SI_GPU ROM_SCLK_GPU ROM_CS#_GPU

S_Top

GR3

GR3 10K

10K

ns

S_Top

FB5 120ohm@100MHz,500mA

1 2

PM

FB0603

FB0603 S_Top

S_Top

GC1

0.1UF/10V,X7R

PM

S_Top

PM

GC4

C0805

4.7uF/10V,X5R

Near GPU

S_Top

+V1.05GPU

+V3.3GPU

PM

CRT_HSYNC{34} CRT_VSYNC{34}

CRT_GREEN{34}

GU1

5 6 1 7 3 8

D C S HOLD W VCC

PM25LV010A

S_Top

ns

Q

VSS

MAX:60+45 mA

PM

GC10

GC10 1uF/10V,X5R

1uF/10V,X5R

C0402

C0402 S_Top

S_Top

FB4 120ohm@100MHz,500mA

1 2

PM

12

4.7UF/10V,X5R

4.7UF/10V,X5R GC21

GC21

C0805PM

S_Top

GC14

0.1UF/10V,X7R

S_Top

Under GPU

FB0603

FB0603 S_Top

S_Top

GC9

C0805

4.7uF/10V,X5R

PM

4.7uF/10V,X5R

PM

Near GPU

S_Top

GFB4

GFB4 120ohm@100MHz,500mA

120ohm@100MHz,500mA

FB0603

FB0603 S_Top

S_Top

1uF/10V,X5R

GC33

C0402PM

S_Top

Near GPU

CRT_RED{34}

CRT_BLUE{34}

S_Top

S_Top S_Top

S_Top

Place close to balls

4

ROM_SO_GPU

2

4

R657

2.2K

R0402

PM

PLLVDD

PM

GC42

0.1UF/10V,X7R

S_Top

PM

0.1UF/10V,X7R

0.1UF/10V,X7R GC30

GC30

S_Top

PM

Under GPU

CRT_DDC_CLK{34}

CRT_DDC_DATA{34}

GR24150,1%

PM

GR23150,1%

PM

GR22150,1%

PM

+V3.3GPU

MAX:45mA

GC46

GC46 1uF/10V,X5R

1uF/10V,X5R

C0402

C0402 S_Top

S_Top

MAX:120mA

PM

4700PF/25V,X7R

S_Top

CRT_RED

CRT_GREEN

CRT_BLUE

+V3.3GPU

ROM_CS#_GPU

R658

ROM_SI_GPU

2.2K

ROM_SO_GPU ROM_SCLK_GPU

R0402

PM

GC17

0.1UF/10V,X7R

S_Top

PM

GC58

T52ns

T52ns T50ns

T50ns

R481 10K R0402

PM

S_Bot

R137

ns

R137

ns

10K R0402

S_Top

PM

R157 40.2K,1%

R0402

R152 40.2K,1%

S_Top

R0402

PM

S_Top

T46ns

T45ns

T45ns T47ns

T47ns

R145 0

R0402 ns

S_Top

PLLVDD SP_PLLVDD

XTALOUTBUFF_T12 27M_nonSSC_GPU

ns

T43

T43 T41 ns

T41 ns

GC37

470pF/25V,X7R

PM

S_Top

GC63 0.1UF/10V,X7R

R208

S_Top

124,1%R0402 PM

R449 33 R0402

R449 33 R0402 R454 33 R0402

R454 33 R0402

124,1%R0402 PM

S_Top

PM

S_Bot

PM

S_Bot

S_Bot S_Bot

S_Bot

S_Bot S_Bot

S_Bot

AK14

S_Bot

AJ12 AK12 AK13

AM13

AL13

AM15 AM14

AL14

J26 J25

AB5

D7 D6 C7 B7 A7

N9

M9

C3 D3 C4 D4

F6

G6

A5

A4 C5

K9

AE9 AD9 AF9

D2 B1

D1 B2

G1 G4

U3D

NC_19 NC_20

CEC

RFU1 RFU2 RFU3

MISC

RFU4 RFU5

MULTI_STRAP_REFO_GND MULTI_STRAP_REF1_GND

ROM_CS# ROM_SI ROM_SO ROM_SCLK

I2CH_SCL I2CH_SDA

SPDIF

BUFRST# RFU

GND_192 GND_193

PLLVDD VID_PLLVDD SP_PLLVDD

XTAL_SSIN

XTAL_PLL

XTAL_IN

XTAL_OUTBUFF XTAL_OUT

DACA_VDD DACA_VREF DACA_RSET

I2CA_SCL I2CA_SDA

DACA_HSYNC DACA_VSYNC

DACA_RED DACA_GREEN DACA_BLUE

NB10_G128

S_Bot

PM

3

DACA

TBD

IFPAB

DACC

IFPCD

IFPAB_PLLVDD

IFPAB_RSET

IFPA_IOVDD IFPB_IOVDD

IFPA_TXC#

IFPA_TXC

IFPA_TXD0#

IFPA_TXD0

IFPA_TXD1#

IFPA_TXD1

IFPA_TXD2#

IFPA_TXD2

IFPA_TXD3#

IFPA_TXD3

IFPB_TXC#

IFPB_TXC

IFPB_TXD4#

IFPB_TXD4

IFPB_TXD5#

IFPB_TXD5

IFPB_TXD6#

IFPB_TXD6

IFPB_TXD7#

IFPB_TXD7

IFPC_PLLVDD

IFPC_RSET IFPC_IOVDD IFPD_IOVDD

IFPD_PLLVDD

IFPD_RSET

IFPC_AUX#

IFPC_AUX

IFPC_L3#

IFPC_L3

IFPC_L2#

IFPC_L2

IFPC_L1#

IFPC_L1

IFPC_L0#

IFPC_L0

IFPD_AUX#

IFPD_AUX

IFPD_L3#

IFPD_L3

IFPD_L2#

IFPD_L2

IFPD_L1#

IFPD_L1

IFPD_L0#

IFPD_L0

DACB_VDD DACB_VREF DACB_RSET

I2CB_SCL

I2CB_SDA DACB_HSYNC DACB_VSYNC

DACB_RED

DACB_GREEN

DACB_BLUE

R42

4.99K,1%

R0402

ns

S_Top

D D

PM

C46P change 35K to 15k to support internal VBIOS ROM 091022 BENT

C C

B B

A A

ADD 1K pull low by bent 091022

IFPAB_PLLVDD

AK9

R191 1K,1%

AJ11

IFPAB_IOVDD

AG9 AG10

AM12 AM11

AL8 AM8

AM9 AM10

AL10 AK10

R206 100,1%ns

AL11 AK11

AN13 AP13

AP8 AN8

AN10 AP10

AR10 AR11

R210 100,1%ns

AP11 AN11

IFPCD_PLLVDD

AJ9

R503 1K,1%

AK7 AJ8

IFPCD_IOVDD

AK8

IFPCD_PLLVDD

AC6

R484 1K,1%

AB6

R525 33 R0402 PM/HDMI

AN3

R526 33 R0402 PM/HDMI

AP2

AR2 AP1

AM4 AM3

AM5 AL5

AM6 AM7

AN4 AP4

AR4 AR5

AP5 AN5

AN7 AP7

AR7 AR8

R490 10K R0402

AG7 AK6 AH7

G3 G2 AM1 AM2 AK4 AL4 AJ4

PM

R459 2.2KR0402

R459 2.2KR0402 R457 2.2KR0402

R457 2.2KR0402

PM

PM PM

PM

1K is not-stuffed in DG V02

S_Top

+V3.3GPU

IFPAB_PLLVDD

IFPAB_IOVDD

IFPCD_PLLVDD

IFPCD_IOVDD

IFPC_TXC# IFPC_TXC IFPC_TXD0N IFPC_TXD0P IFPC_TXD1N IFPC_TXD1P IFPC_TXD2N IFPC_TXD2P

R0402

R0402 S_Top

S_Top

GPU_LVDS_CLKAM {31} GPU_LVDS_CLKAP {31}

GPU_LVDS_YAM0 {31} GPU_LVDS_YAP0 {31}

GPU_LVDS_YAM1 {31} GPU_LVDS_YAP1 {31}

GPU_LVDS_YAM2 {31} GPU_LVDS_YAP2 {31}

S_Top

PM/HDMI

S_Bot

PM/HDMI

S_Bot

S_Bot S_Bot

S_Bot

C182 0.1uF/10V,X7RPM/HDMI

C180 0.1uF/10V,X7RPM/HDMI

S_Top

C177 0.1uF/10V,X7RPM/HDMI

C167 0.1uF/10V,X7RPM/HDMI

S_Top

C163 0.1uF/10V,X7RPM/HDMI

C158 0.1uF/10V,X7RPM/HDMI

S_Top

C157 0.1uF/10V,X7RPM/HDMI

C144 0.1uF/10V,X7RPM/HDMI

S_Top

S_Bot

S_Bot S_Bot

S_Bot

2

MAX:220 mA

GC61

GC61 1uF/10V,X5R

PM

1uF/10V,X5R

PM

C0402

C0402 S_Top

S_Top

MAX:220 mA

PM

GC27

0.1uF/10V,X7R

C0402

Under GPU

S_Top

PM

GC41

0.1uF/10V,X7R

C0402

S_Top

PM

GC52

GC52 1uF/10V,X5R

1uF/10V,X5R

C0402

Near GPU

S_Top

MAX:220 mA

GC24

0.1uF/10V,X7R

C0402

PM/HDMI

S_Top

GC47

0.1uF/10V,X7R

C0402

PM/HDMI

S_Top

Under GPU Near GPU

GC20

0.1uF/10V,X7R

C0402

PM/HDMI

S_Top

MAX:285 mA

GC43

0.1uF/10V,X7R

C0402

PM/HDMI

S_Top

HDMI_DDC_DATA {33} HDMI_DDC_CLK {33}

IFPC_TXC# {33} IFPC_TXC {33}

IFPC_TXD2N {33} IFPC_TXD2P {33}

IFPC_TXD1N {33} IFPC_TXD1P {33}

IFPC_TXD0N {33} IFPC_TXD0P {33}

R211 499,1% PM/HDMI

R211 499,1% PM/HDMI R207 499,1% PM/HDMI

R207 499,1% PM/HDMI

S_Top

R203 499,1% PM/HDMI

S_Top

R200 499,1% PM/HDMI

S_Top

R194 499,1% PM/HDMI

S_Top

R189 499,1% PM/HDMI

S_Top

R186 499,1% PM/HDMI

S_Top

R184 499,1% PM/HDMI

S_Top

S_Top S_Top

S_Top

GC67

0.1uF/10V,X7R

C0402

PM/HDMI

S_Top

S46P VerB:HDMI_DDC_CLK and DATA is wrongl link,swap them to correct link 090626

Q12

BSS138

SOT23

PM/HDMI

S_Top

Page Name

Page Name Size

Size

Project Name Rev

Custom

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1 2

PM

GC40

C0805

4.7uF/10V,X5R

S_Top

PM

120ohm@100MHz,500mA

GC15

C0805

S_Top

4.7uF/10V,X5R

S_Top

GC29

GC29 1uF/10V,X5R

1uF/10V,X5R

C0402

PM/HDMI

S_Top

GC54

GC54 1uF/10V,X5R

1uF/10V,X5R

C0402

PM/HDMI

S_Top

3

1

2

TOPSTAR TECHNOLOGY

bent

bent N10M IO_1

N10M IO_1

C46

1

+V1.05GPU

GFB7

PM

GFB7

PM

FB0603

120ohm@100MHz,500mA

S_Top

GFB3

12

FB0603

GFB2

1 2

120ohm@100MHz,500mA

FB0603

GC7

PM/HDMI

S_Top

C0805

4.7uF/10V,X5R

PM/HDMI

S_Top

1 2

GC34

C0805

4.7uF/10V,X5R

PM/HDMI

S_Top

+V3.3GPU

R197

10KPM/HDMI

S_Top

+V1.8GPU

GC5

C0805

4.7uF/10V,X5R

PM

4.7uF/10V,X5R

PM

S_Top

+V3.3GPU

+V1.05GPU

GFB6

FB0603

120ohm@100MHz,500mA

PM/HDMI

S_Top

y

A

20 59Friday, November 27, 2009

A

of

5

+V3.3GPU {17,20,33,34,52,57}

U3E

PM

R500 10K R0402

R500 10K R0402 R488 10K R0402

R488 10K R0402

PM

D D

+V3.3GPU

C138

0.1uF/10V,X5R

C0402PM

C C

N10M-GS:0xA74(strap2 pull-down 25K, rom_sclk pull-up 15K) N10M-GE:0xA68(strap2 pull-up 5K, rom_sclk pull-down 15K)

B B

A A

+V3.3GPU

R167

R473

34.8K,1%

4.99K,1%

R0402

ns

R475

30.1K,1%

R0402

PM

S46P VerB:Ns R579,stuff R562 and change R562 to 35k followed nvidia PUN 090619

R0402

R164

34.8K,1%

R0402

ns

45.3K,1%

R0402

PM

R480

PM

R477

R477 15K,1%

15K,1%

R0402

ns

5

R486 10K R0402PM R486 10K R0402PM

+V3.3GPU

C141

0.1uF/10V,X5R

T11ns T11ns T8ns T8ns

T48ns T48ns

STRAP0_GPU STRAP1_GPU STRAP2_GPU

C0402

AJ6

IFPEF_PLLVDD

AL1

IFPEF_RSET

AE7

IFPE_IOVDD

AD7

IFPF_IOVDD

AD4

IFPE_AUX#

AE4

IFPE_AUX

AE5

IFPE_L3#

AE6

IFPE_L3

AF5

IFPE_L2#

AF4

IFPE_L2

AG4

IFPE_L1#

AH4

IFPE_L1

AH5

IFPE_L0#

AH6

IFPE_L0

AF2

IFPF_AUX#

AF3

IFPF_AUX

AH3

IFPF_L3#

AH2

IFPF_L3

AH1

IFPF_L2#

AJ1

IFPF_L2

AJ2

IFPF_L1#

AJ3

IFPF_L1

AL3

IFPF_L0#

AL2

IFPF_L0

AA9

MIOB_VDDQ1

AB9

MIOB_VDDQ2

W9

MIOB_VDDQ3

Y9

T13ns T13ns T49ns T49ns

T51ns T51ns

PM

MIOB_VDDQ4

AA7

MIOB_CAL_PD_VDDQ

AA6

MIOB_CAL_PU_GND

AF1

MIOB_VREF

Y1

MIOB_D0

Y2

MIOB_D1

Y3

MIOB_D2

AB3

MIOB_D3

AB2

MIOB_D4

AB1

MIOB_D5

AC4

MIOB_D6

AC1

MIOB_D7

AC2

MIOB_D8

AC3

MIOB_D9

AE3

MIOB_D10

AE2

MIOB_D11

U6

MIOB_D12/NC

W6

MIOB_D13/NC

Y6

MIOB_D14/NC

W5

STRAP0

W7

STRAP1

V7

STRAP2

W3

MIOB_CTL3

W1

MIOB_HSYNC

W2

MIOB_VSYNC

Y5

MIOB_DE

V4

MIOB_CLKOUT

W4

MIOB_CLKOUT#

AE1

MIOB_CLKIN

P9

MIOA_VDDQ1

R9

MIOA_VDDQ2

T9

MIOA_VDDQ3

U9

MIOA_VDDQ4

U5

MIOA_CAL_PD_VDDQ

T5

MIOA_CAL_PU_GND

N5

MIOA_VREF

PM

GR4

GR4 10K

10K

R0402

NB10_G128

PM

+V3.3GPU

IFPEF

MIOB

THER_ALERT#

MIOA

MIOA_D12/NC MIOA_D13/NC MIOA_D14/NC

MIOA_HSYNC MIOA_VSYNC

MIOA_CLKOUT

MIOA_CLKOUT#

MIOA_CLKIN

JTAG_TRST#

MISC1

4

MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8

MIOA_D9 MIOA_D10 MIOA_D11

MIOA_CTL3

MIOA_DE

THERMDN THERMDP

JTAG_TCK JTAG_TMS

JTAG_TDI

JTAG_TDO

I2CS_SCL I2CS_SDA I2CC_SCL

I2CC_SDA

RFU_1 RFU_2 RFU_3 RFU_4

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23

4

N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6

P5 N3 L3 N2

R4 T4

R470 10K R0402

N4

B4 B5

AP14 AR14 AN14 AN16 AP16

E2 E1 E3 E4 F4 G5 D5 E5

K1 K2

GPU_LVDS_BKLTCTL

K3 H3

GPU_LVDS_BKLTEN_R

H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6

PM

R541 10K R0402ns R541 10K R0402ns R540 10K R0402ns R540 10K R0402ns R533 10K R0402ns R533 10K R0402ns

R546 1K R0402ns R546 1K R0402ns

R445 2.2K R0402PM R445 2.2K R0402PM R448 2.2K R0402PM R448 2.2K R0402PM

R450 33 R0402PM R450 33 R0402PM R126 33 R0402PM R126 33 R0402PM

I2CD_SCL_GPU I2CD_SDA_GPU

GPIO0_GPU

GPU_VID2

GPU_OVT#

THER_ALERT#

SLI_SYNC

PWR_LEVEL

HPD_E_GPU

+V3.3GPU

T53nsT53

+V3.3GPU

G_SMB_CLK {31} G_SMB_DATA {31}

GPU_HDMI_HPD {33,43}

GPU_LVDS_BKLTCTL {32}

GPU_LVDS_VDDEN {31} GPU_VID0 {52}

GPU_VID1 {52}

GPU_OVT# {38}

R140 33 R0402ns R140 33 R0402ns

GPU_LVDS_BKLTEN_R

3

ITEM

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

+V3.3GPU

GC191

C0402

GPIO23

需要用

DDR3

的

ns

G_SMB_CLK G_SMB_DATA I2CD_SCL_GPU I2CD_SDA_GPU GPU_VID2 GPU_OVT# SLI_SWAPRDY

PWR_LEVEL

AC_IN {43,46}

Nvidia advise: For used GPIO1,2,3,4,5,6: please use 10K pull-down for initial value. For used GPIO8,12: please use 10K pull-up for initial value. For the unused GPIO, no need external HW pull-up/down.

R663

R663 10K

10K

R0402

GPU_HDMI_HPD GPIO0_GPU GPU_LVDS_BKLTCTL SLI_SYNC GPU_LVDS_VDDEN HPD_E_GPUGPU_FAN_PWM GPU_FAN_PWMGPU_GPIO17 GPU_GPIO17GPU_GPIO18 GPU_GPIO18HPD_D_GPU HPD_D_GPUGPU_GPIO20 GPU_GPIO20HPD_F_GPU HPD_F_GPUSLI_SWAPRDY

GR54

R0402

GU5

1 2

SN74AHC1G08DBV

SOT23_5

3

R30 2.2K R0402 PMR30 2.2K R0402 PM R28 2.2K R0402 PMR28 2.2K R0402 PM R128 2.2K R0402 PMR128 2.2K R0402 PM R131 2.2K R0402 PMR131 2.2K R0402 PM R132 10K R0402 nsR132 10K R0402 ns R148 10K R0402 PMR148 10K R0402 PM R155 10K R0402 nsR155 10K R0402 ns

R142 10K R0402 nsR142 10K R0402 ns

R458 10K nsR0402R458 10K nsR0402 R463 10K R0402 PMR463 10K R0402 PM R455 10K R0402R455 10K R0402 R460 10K R0402 nsR460 10K R0402 ns R135 10K R0402 PMR135 10K R0402 PM R465 10K R0402 nsR465 10K R0402 ns R462 10K R0402 nsR462 10K R0402 ns R466 10K R0402 nsR466 10K R0402 ns R468 10K R0402 nsR468 10K R0402 ns R150 10K R0402 nsR150 10K R0402 ns R472 10K R0402 nsR472 10K R0402 ns R451 10K R0402 nsR451 10K R0402 ns

+V3.3GPU

0

0.1UF/10V,X7R

53

VCC

4

GND

FUNC

GPIO

HPD-C

Panel backlight brightness

Panel Power enable , active high

Panel backlight On , active high

GPU vid0

GPU vid1

GPU vid2

Thermal trip of GPU , active low

Thermal alert input

Memory Vref switch

SLI_SYNC , host GPU output , slave input

PWR_LEVEL

Dynamic NVVDD control 0

HPD-E

FAN_PWM

Reserved

HPD_D

Reserved

HPD-F

SWAPRDY

GPIO

GPU_LVDS_BKLTEN {31}

2

Action

no using , PD 10K

connect to HDMI conn with level shifter

reserved associated with EC PWM , then connect to LVDS conn , reserved PD 10K

connect LCDVDD_ON

connect LCDVDD backlight on

Reserved routing to GPU power controller

no using , reserved 10K PU V3.3S

Connect to Hardware shut down circuit , parallel with CPU thermaltrip , 10K PU V3.3S

connect to thermal sensor IC alert with 10K PU V3.3S

no using , NC

No using , PD 10K followed DEMO

no using , 10K PU V3.3S followed DEMO

no using , NC

no using , PD 10K

10K PU V3.3S

no using , NC

NOTE: 1, XCLK_277 set 0

，

FB_0_BAR_SIZE 0 system frame buffer 256M

2

，

PCI_DEVID[4:0] N10M-GS set 0x0A74 PCI_DEVID[4:0] set 10100

3 4, USER[3:0] set 1111 , using EDID method to detect panel 5, 3GIO_PADCFG[3:0] set 0001 , using NOTEBOOK configuration 6, RAMCFG[3:0] need follow latest PUN 7, PEX_PLL_EN_TERM100 set 0 , using PEX PLL termination disable configuration 8, SLOT_CLK_CFG set 1 , GPU MCH using the same clk chip 9, SUB_VENDOR set 0 , no VIDEO BIOS ROM

10.SMBUS_ALT_ADDR Set 0

11.0 3D Device 1VGA Device(default)

2

，

using 27MHz clock

Page Name

Page Name Size

Size

Project Name Rev

Custom

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

TOPSTAR TECHNOLOGY

bent

bent N10M IO_2

N10M IO_2

C46

1

21 59Friday, November 27, 2009

A

of

5

SPONGE_RTC1

SPONGE_RTC1 RTCBAT GLUE

RTCBAT GLUE

assembly

RTC_BAT1

D D

根据机构定

C C

B B

A A

RTCBAT with Cable

assembly

Cable

+

-

尺寸

RTCBAT1

RTCBAT1 CONN2_R

CONN2_R

3 CNS2_R

CNS2_R

3

1 2

4

EC_RTC

D4

D4 BAT54C

BAT54C

SOT23

1

3

2

R121

R121 1K

1K

R0402

1 2

+V3.3S

R3980R398

0

R397 3.3KR397 3.3K R396 3.3KR396 3.3K

R447 20K R0402R447 20K R0402

R110 20K R0402R110 20K R0402

R453

R453 1M

1M

R0402

PCH_EC_RTC

R399

10K R0402

8 3 7

4

C329

C329 1uF/10V,X7R

1uF/10V,X7R

C0603

C98

C98 1uF/10V,X7R

1uF/10V,X7R

C0603

ns

U8

VDD WP# HOLD#

8M

SOIC8_50_208

CMOS Settings J1 Clear CMOS Short Keep CMOS Open

C331

1uF/10V,X7R

C0603

5

SI

2

SO

1

CE#

6

SCK

4

VSS

12

J4

JOPEN

JOPEN RESISTOR_1

RESISTOR_1

ns

AZALIA_CODEC_SDOUT{37}

3

Voltage Swing on RTCX1 pin should not exceed 1.0V.

U4A

32XCLK0 32XCLK1

RTC_RST# SRTC_RST#

SM_INTRUDER#

ICH_INTVRMEN

R461 33 R0402R461 33 R0402

R134

4.7K

R0402

R411 0R411 0 R400 0R400 0

R412 0R412 0 R413 0R413 0

PCH_EC_RTC

R99

HDA_BCLK HDA_SYNC

HDA_RST#

R102

R102 332K,1%

332K,1%

R0402

0

ns

R0402

HDA_SDO

SPI_CLK_RSPI_CLK SPI_CS0#_R

SPI_MOSI_R SPI_MISO_R

AZALIA_CODEC_BITCLK{37} AZALIA_CODEC_SYNC{37}

SPKR{37}

AZALIA_CODEC_RST#{37}

AZALIA_SDATAIN0{37}

For ME

SPI_MOSI SPI_MISO SPI_CS0# SPI_CLK

R467 33 R0402R467 33 R0402

R464 33 R0402R464 33 R0402

R469 33 R0402R469 33 R0402

ns

ICTPns

T35

ICTPns

T32

ICTPns

T36

ICTPns

T33

ICTPns

T34

SPI_CS0#

SPI_MOSI SPI_MISO

B13 D13

C14 D17 A16 A14

A30 D29

C30

G30

F30 E32 F32

B29

H32 J30

BA2 AV3 AY3

AY1 AV1

ICH_INTVRMEN

U4A

RTCX1 RTCX2

RTCRST# SRTCRST# INTRUDER# INTVRMEN

HDA_BCLK HDA_SYNC

P1

SPKR HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33 HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

IbexPeak-M_Rev1_0

332K 1% PULL HIGH TO VBAT_RTC FOR ICH8M INTRNAL VR ENABLE(PULL LOW DISABLE)

RTCIHDA

SPI JTAG

32XCLK0

32XCLK1

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21 SATA1GP / GPIO19

R440

R440 10M

10M

R0402

LDRQ0#

SERIRQ

R441 0

R0402

D33 B33 C32 A32

C34 A34

F34 AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16 AF15

T3

Y9 V1

SATA_TXN0_C SATA_TXP0_C

SATA_TXN1_C SATA_TXP1_C

R95 1K R0402 nsR95 1K R0402 ns R88 1K R0402 nsR88 1K R0402 ns

R416 1K R0402 nsR416 1K R0402 ns R415 1K R0402 nsR415 1K R0402 ns

R62 1K R0402 nsR62 1K R0402 ns R63 1K R0402 nsR63 1K R0402 ns

R418 1K R0402 nsR418 1K R0402 ns R417 1K R0402 nsR417 1K R0402 ns

R76 10K R0402R76 10K R0402 R421 10K R0402R421 10K R0402

12

2

LPC_AD0 {38,40,43} LPC_AD1 {38,40,43} LPC_AD2 {38,40,43} LPC_AD3 {38,40,43}

LPC_FRAME# {38,40,43}

INT_SERIRQ {38,43}

C66 0.01uF/25V,X7R

C65

0.01uF/25V,X7RC0402

C63 0.01uF/25V,X7R

C64

0.01uF/25V,X7RC0402

R113 37.4,1%

Y4

32.768KHz

xd3_2X6

3

ASSY

C0402

+V1.05S

R0402

OD output need pullup

C333

C0402

15pF/50V,NPO

C332

C0402

15pF/50V,NPO

R0402

R423

10K

1

+V1.05S {23,24,28,29,50,56,57,58} +V3.3S {6,8,15,16,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58}

EC_RTC {48} PCH_EC_RTC {29}

+V3.3S

INT_SERIRQ

+V3.3S

R78

R78 10K

10K

R0402

R471

R471 10K

10K

R0402

ns

SATA_RXN0 {35} SATA_RXP0 {35}

SATA_TXN0 {35} SATA_TXP0 {35}

SATA_RXN1 {35} SATA_RXP1 {35}

SATA_TXN1 {35}

SATA_TXP1 {35}

R136

R136 10K

10K

R0402

ns

HM55 don't support SATA port 2and3

+V3.3S

SATA_LED# {45}

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

22 59Thursday, December 17, 2009

A

of

5

D D

PCIE_RXN1_LAN{44} PCIE_RXP1_LAN{44} PCIE_TXN1_LAN{44} PCIE_TXP1_LAN{44}

PCIE_RXN2_3G{40}

PCIE_RXP2_3G{40} PCIE_TXN2_3G{40} PCIE_TXP2_3G{40}

PCIE_RXN3_EXP{41} PCIE_RXP3_EXP{41} PCIE_TXN3_EXP{41} PCIE_TXP3_EXP{41}

C C

+V3.3AL

R402

R402 10K

10K

R0402

+V3.3AL

R422

R422 10K

10K

R0402

MiniPCIE_REQ#MiniPCIE_REQ#

+V3.3AL

B B

A A

R0402

R424

R424 10K

10K

minicard_CLKREQ#

5

PCIE_RXN4_WLAN{39} PCIE_RXP4_WLAN{39} PCIE_TXN4_WLAN{39} PCIE_TXP4_WLAN{39}

HM55 doesn't contain port7 and port8

Change to pull up follow intel design guide

C343

C348

C351

C346

+V3.3AL

CLK_PCIE_MINICARD#{39} CLK_PCIE_MINICARD{39}

+V3.3AL

C0402

PCIE_TXN1_LAN_C

C340

0.1UF/10V,X7R

C0402

C349

0.1UF/10V,X7R

C0402

C350

0.1UF/10V,X7R

C0402

C347

0.1UF/10V,X7R

CLK_PCIE_3G#{40} CLK_PCIE_3G{40}

MiniPCIE_REQ#{40}

R83 8.2K R0402R83 8.2K R0402

R84 8.2K R0402R84 8.2K R0402

R57 8.2K R0402R57 8.2K R0402

PCIE_TXP1_LAN_C

PCIE_TXN2_3G_C PCIE_TXP2_3G_C

PCIE_TXN3_EXP_C PCIE_TXP3_EXP_C

PCIE_TXN4_WLAN_C PCIE_TXP4_WLAN_C

C0402C343

C0402

0.1UF/10V,X7R

C0402C348

C0402

0.1UF/10V,X7R

C0402C351

C0402

0.1UF/10V,X7R

C0402C346

C0402

0.1UF/10V,X7R

PCIE_GLAN_CLKN{44} PCIE_GLAN_CLKP{44}

R425 0 R0402R425 0 R0402

minicard_CLKREQ#{39}

CLK_PCIE_EXPCARD#{41}

CLK_PCIE_EXPCARD{41}

EXPCARD_CLKREQ#{41} PCI_CLKFB {26}

4

U4B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IbexPeak-M_Rev1_0

4

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1 CL_DATA1 CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

SMBCLK

SMBDATA

B9 H14 C8

J14 C6 G8

M14 E10 G12

T13 T11 T9

H1

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

R311 0 R0402

Q18

Q18 2N7002E-T1

2N7002E-T1

3

R301 0 R0402

2N7002E-T1

3

Q23

3

GPIO11 SMBCLK SMBDATA

GPIO60 SML0CLK SML0DATA

GPIO74

PEG_A_CLKRQ#

CLKOUT_PEG# CLKOUT_PEG

R144

90.9,1%

R0402

ns

2

1

ns

2

1

3

R652 0 R0402R652 0 R0402 R653 0 R0402R653 0 R0402

CL_CLK1 {39} CL_DATA1 {39} CL_RST1# {39}

R427 0 R0402

R174 0 R0402R174 0 R0402 R173 0 R0402R173 0 R0402

R414 0 R0402R414 0 R0402

CLK_BUF_SATA_N {6} CLK_BUF_SATA_P {6}

CLK_BUF_BCLK_N {6} CLK_BUF_BCLK_P {6}

CLK_BUF_DOT96_N {6} CLK_BUF_DOT96_P {6}

CLK_BUF_EXP_N {6} CLK_BUF_EXP_P {6}

CLK_BUF_REF14 {6}

R51533 R51533

+V5S

ns

CLK_PCIE_N11M# {17} CLK_PCIE_N11M {17}

CLK_EXP_N {8} CLK_EXP_P {8}

+V1.05S

CLK_CR_48M {42}

+V3.3S

R305

2.2K

+V3.3S

SML1CLK {43} SML1DATA {43}

PCIE_CLKREQ {17}

R0402

25MHz XS2_3d3

C164

C164 27pF/50V,NPO

27pF/50V,NPO

C0402

R297

2.2K

Add 0 ohm

R1950 R1950 R19610M

R19610M

Y5

12

SMB_CLK_S {6,15,16,40,41}

SMB_DATA_S {6,15,16,40,41}

2

C168

C168 27pF/50V,NPO

27pF/50V,NPO

C0402

2

SMBCLK SMBDATA GPIO11

GPIO60

SML0CLK

SML0DATA

GPIO74

SML1CLK

SML1DATA

PEG_A_CLKRQ#

1

+V3.3AL {6,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V1.05S {22,24,28,29,50,56,57,58} +V3.3S {6,8,15,16,22,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V5S {25,29,32,33,34,35,36,37,38,43,51,52,55,56}

+V3.3AL

R124 2.2KR124 2.2K R430 2.2KR430 2.2K

10K

R431

R0402 R431

R0402

10K

R0402

R103

R103 10K

10K

R0402

R429

R429 10K

10K R89

R89

R0402

10K

10K R428

R428

R0402

R97 2.2K

R0402

R100 2.2K

R0402

R426

10K

R0402

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

23 59Friday, November 27, 2009

A

of

5

D D

C C

This is suspend power pin

PM_RSMRST#{43,53}

+V3.3AL

C282

0.1UF/25V,Y5V

ns

Main_PWROK{43,53}

EC_IMVP_PWRGD{43}

B B

R347 0R347 0

U19

53

74AHCT1G08GV

VCC

1 2

SOT23_5

4

GND

ns

这个信号在有M3的时候用。

SYS_PWROK

R346

R346 10K

10K

R0402

+V1.05S

+V3.3AL

4

PM_DRAM_PWRGD{8}

R444

R444 10K

10K

R0402

R456

49.9,1%

R0402

SYS_PWROK

PM_PWRBTN#{43}

ALW_ACK

R111 1K

R56

R0402

R119

R0402

R432 0 R0402R432 0 R0402

ALW_ACK{43}

R401

10K

R0402

10K

PM_PWRBTN#

10K

DMI_RXN0{7} DMI_RXN1{7} DMI_RXN2{7} DMI_RXN3{7}

DMI_RXP0{7} DMI_RXP1{7} DMI_RXP2{7} DMI_RXP3{7}

DMI_TXN0{7} DMI_TXN1{7} DMI_TXN2{7} DMI_TXN3{7}

DMI_TXP0{7} DMI_TXP1{7} DMI_TXP2{7} DMI_TXP3{7}

DMI_COMP_R

+V3.3S

R70 0 R0402R70 0 R0402

R446 0 R0402R446 0 R0402

R69 0 R0402R69 0 R0402

R71 0 R0402R71 0 R0402

+V3.3AL

RI#

PCIE_WAKE#

R60

R60 10K

10K

R0402

DRAM_PWRGD_R

AC_IN_PCH{43}

BAT_LOW#{43}

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

SYS_PWROK_R

PWROK_R

ME_PWRGD_R

LAN_RST#

RI#

U4C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IbexPeak-M_Rev1_0

+V3.3S

3

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_M#

System Power Management

R405

10K

R0402

TP23

PMSYNCH

SLP_LAN# / GPIO29

CLKRUN#

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14 BF13 BH13 BJ12 BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

SLP_S5#

SLP_S4#

SLP_S3#

CLKRUN#

SUSCLK

R81 0 R0402R81 0 R0402

R86 0 R0402R86 0 R0402

R67 0 R0402R67 0 R0402

SLP_M#

T37 nsT37 ns

2

FDI_TXN[7:0] {7}

FDI_TXP[7:0] {7}

FDI_INT {7} FDI_FSYNC0 {7} FDI_FSYNC1 {7} FDI_LSYNC0 {7} FDI_LSYNC1 {7}

PCIE_WAKE# {39,40,41,43,44}

PM_SUS_STAT# {43}

T39 ICTPnsT39 ICTPnsR434 10K R0402R434 10K R0402

T1 nsT1 ns

PM_SLP_S4# {41,43,56}

PM_SLP_S3# {41,43,53}

M

电就用S电。此信号不用

H_PM_SYNC {8}

+V3.3AL {6,23,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V3.3S {6,8,15,16,22,23,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.05S {22,23,28,29,50,56,57,58}

+V3.3AL

R82

R82 10K

10K

ns

1

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

24 59Friday, November 27, 2009

A

of

5

CRT_BLUE_R{34}

CRT_RED_R{34}

PCH_LVDS_CLKAM{31} PCH_LVDS_CLKAP{31}

C435

5.6pF/50V,NPO

ns

C436

5.6pF/50V,NPO

ns

C437

5.6pF/50V,NPO

ns

PCH_LVDS_BKLTEN{31}

PCH_LVDS_VDDEN{31}

R147

2.37K,1%

PCH_LVDS_YAM0{31} PCH_LVDS_YAM1{31} PCH_LVDS_YAM2{31}

PCH_LVDS_YAP0{31} PCH_LVDS_YAP1{31} PCH_LVDS_YAP2{31}

+V3.3S

R178

R175

10K

CRT_DDC_CLK_R{34} CRT_DDC_DATA_R{34}

R508

R508 150,1%

150,1%

GM

CRT_HSYNC_R{34} CRT_VSYNC_R{34}

R506

10K

LCTL_DATA LCTL_CLK

PCH_DDC_DATA {31} PCH_DDC_CLK {31}

R507

150,1%

GM

150,1%GM

CRT_GREEN_R{34}

CRT_BLUE_R

CRT_GREEN_R

CRT_RED_R

D D

+V3.3S

R176

R177

2.2K

C C

B B

LVDS_BKLTCTL{32}

T10nsT10

ns

T12nsT12

ns

CRT_BLUE_R CRT_GREEN_R CRT_RED_R

4

PCH_DDC_CLK PCH_DDC_DATA

LCTL_CLK LCTL_DATA

T7nsT7

ns

CRT_DDC_CLK_R CRT_DDC_DATA_R

CRT_HSYNC_R

CRT_VSYNC_R

R179

R179 1K,1%

1K,1%

R166

R166 100K

100K

U4D

T48 T47

Y48

AB48

Y45

AB46

V48

AP39 AP41

AT43 AT42

AV53 AV51

BB47 BA52 AY48 AV47

BB48 BA50 AY49 AV48

AP48 AP47

AY53 AT49 AU52 AT53

AY51 AT48 AU50 AT51

AA52 AB53 AD53

V51 V53

Y53 Y51

AD48 AB51

IbexPeak-M_Rev1_0

L_BKLTEN L_VDD_EN

L_BKLTCTL L_DDC_CLK

L_DDC_DATA L_CTRL_CLK

L_CTRL_DATA LVD_IBG

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

3

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

IN_D2- {33}

IN_D2+ {33}

IN_D1- {33}

IN_D1+ {33}

IN_D0- {33}

IN_D0+ {33}

MCH_CLK_D4- {33}

MCH_CLK_D4+ {33}

GM_HDMI_DDC_CLK {33} GM_HDMI_DDC_DATA {33}

R532

GMR532

GM

0

R0402

R527

R527 100K

100K

GM

2

+V3.3S {6,8,15,16,22,23,24,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58}

+V5S {23,29,32,33,34,35,36,37,38,43,51,52,55,56}

+V5S

1

2N7002

GM

3

2

R662

nsR662

ns

0

Q29

R0402

MCH_HDMI_HPD {33}

1

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

25 59Friday, November 27, 2009

A

of

5

D D

4

3

2

+V3.3AL {6,23,24,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57}

+V3.3S {6,8,15,16,22,23,24,25,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.8S {11,28,29,31,49,56,57}

1

C313

0.1UF/25V,Y5V

C0402

4

R389

R389 100K

100K

R0402

PCI_GNT#3

4.7K in checklist

+V3.3S

LVDS_SEL_PCH

+V3.3AL+V3.3S

R388

R387

0

R0402

ns

53

VCC

GND

11 SPI 0

R517

1K

R0402

PCI_CLK_DEBUG{40}

0

1 2

U22

U22 74AHCT1G08GV

74AHCT1G08GV

SOT23_5

PCI LPC

ns

CLK_591PCI{43} CLK_TCMPCI{38}

PCI_CLKFB{23}

PLT_RST#

LVDS_BLT_SEL{31}

LVDS_DDC_SEL{31}

T9

ICTP nsT9ICTP ns

T2

ICTP nsT2ICTP ns

+V1.8S

R32

R32 1K,1%

1K,1%

R0402

1

Q7

2 3

MMBT3904-FSOT23

PM

4

PM

R66

R66 10K

10K

R0402

R51347 R51347R143 8.2K R0402R143 8.2K R0402 R51247 R51247

R51147 R51147

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI_REQ#0 LVDS_SEL_PCH

PCI_REQ#3 PCI_GNT#0

PCI_GNT#1 GNT2# PCI_GNT#3

INT_PIRQE# INT_PIRQF# INT_PIRQG#

PCI_RST# PCI_SERR#

PCI_PERR#

PCI_IRDY# PCI_PAR PCI_DEVSEL# PCI_FRAME#

PCI_LOCK# PCI_STOP#

PCI_TRDY# PCI_PME PLT_RST# CLK_591PCI_R

CLK_TCMPCI_R PCI_CLKFB_R PCI_CLK_DEBUG_R

+V1.8S

R33

R33 10K

10K

R0402

PM

PLTRST buffer

C C

PCI_GNT#0

PCI_GNT#1

Default high(SPI)

PCI_GNT#3 Top Block Swap Mode

B B

Strap

BUF_PLT_RST#{8,17,38,39,40,41,43,44}

R159

R170

1K

R0402

ns

Low=A16 swap override/ Topblock Swap Override enable High=Default

PCI_GNT1# PCI_GNT0# Boot BIOS

1 00

PCI pullup

PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_REQ#0 LVDS_SEL_PCH LVDS_BLT_SEL PCI_REQ#3 LVDS_DDC_SEL GNT2# INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG#

A A

PCI_RST#

5

R501 8.2K R0402R501 8.2K R0402 R482 8.2K R0402R482 8.2K R0402 R504 8.2K R0402R504 8.2K R0402 R478 8.2K R0402R478 8.2K R0402 R162 8.2K R0402R162 8.2K R0402 R165 8.2K R0402R165 8.2K R0402 R171 8.2K R0402R171 8.2K R0402 R168 8.2K R0402R168 8.2K R0402 R519 8.2K R0402R519 8.2K R0402 R491 8.2K R0402R491 8.2K R0402 R487 8.2K R0402R487 8.2K R0402 R514 8.2K R0402R514 8.2K R0402 R25 8.2K R0402R25 8.2K R0402 R141 8.2K R0402R141 8.2K R0402

R518 8.2K R0402R518 8.2K R0402 R156 8.2K R0402R156 8.2K R0402 R16122 R16122 R485 8.2K R0402R485 8.2K R0402 R476 8.2K R0402R476 8.2K R0402 R516 8.2K R0402R516 8.2K R0402 R474 8.2K R0402R474 8.2K R0402

R55 8.2K R0402 nsR55 8.2K R0402 ns

LVDS_SEL_PCH{26}

U4E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IbexPeak-M_Rev1_0

LVDS_SEL {31}

PCI

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_RCOMP

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USB

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

3

NV_ALE NV_CLE

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2 AV7 AY8

AY5 AV11

BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25 D25

N16 J16 F16 L16 E14 G16 F12 T15

OC0# OC1#

OC3# OC4#

OC6# OC7#

EXPCARD_USB_PN0 {41} EXPCARD_USB_PP0 {41} MINICARD_USB_PN1 {39} MINICARD_USB_PP1 {39}

BT_USB_PN2 {38}

BT_USB_PP2 {38} CAM_USB_PN3 {32} CAM_USB_PP3 {32}

USB_PN4 {36}

USB_PP4 {36}

USB_PN5 {36}

USB_PP5 {36}

USB_CR_PN8 {42} USB_CR_PP8 {42}

USB_PN10 {36}

USB_PP10 {36}

USB_PN11 {36}

USB_PP11 {36}

T4 nsT4 ns T3 nsT3 ns T44 nsT44 ns T42 nsT42 ns

USB_BIAS

USB_OC#2 {36}

USB_OC#5 {36}

OC0# OC1# OC3# OC4# OC6# OC7#

BT

CAMERA

IOUSB PORT

MINICARD_USB_PN2 {40} MINICARD_USB_PP2 {40}

CARD READER

IOUSB PORT

Attribution TBD

R12010KR0402 R12010KR0402 R10610KR0402 R10610KR0402 R11410KR0402 R11410KR0402 R11610KR0402 R11610KR0402 R10410KR0402 R10410KR0402 R5810KR0402 R5810KR0402

EXPRESS Card

Change port5 to port2 by bent 091022

MINICARD

R452

22.6,1%

R0402

+V3.3AL

2

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

26 59Friday, November 27, 2009

of

A

5

D D

+V3.3S

GPIO0 EXTSMI# GPIO6 EC_RUNTIME_SCI# SATA2GP SATA4GP GPIO17 GPIO22 STP_PCI#

SATA5GP

GPIO48

C C

H_RCIN#

R420 10KR420 10K R149 10KR149 10K R151 10KR151 10K R138 10KR138 10K

R77 10K R0402

R419 10KR419 10K

ns

R160 10KR160 10K R75 10KR75 10K R80 10KR80 10K R79 10K R0402

R403 10K R0402R403 10K R0402

R61 10KR61 10K

R408 10KR408 10K

注意工板要求下拉

+V3.3AL

GPIO8 LAN_PHY GPIO15 GPIO24 GPIO28

GPIO57

B B

GPIO37 GPIO38 GPIO39

R87 10KR87 10K

R85 10KR85 10K R72 1KR72 1K R94 10KnsR94 10K R59 10KR59 10K

R92 10KR92 10K

R112

R112 10K

10K

ns

+V3.3S

R406

R406 10K

10K

R117

R117 10K

10K

确认是否上

R73

R73 10K

10K

ns

R409

R407

10K

4

EC_RUNTIME_SCI#{43}

EXTSMI#{43}

SATA_CLKREQ#

T38

ICTP ns

T40

ICTP ns

GPIO0

GPIO6

GPIO8 LAN_PHY GPIO15 SATA4GP GPIO17 GPIO22 GPIO24 GPIO27 GPIO28 STP_PCI#

SATA2GP GPIO37 GPIO38 GPIO39

GPIO48 SATA5GP GPIO57

GPIO45 GPIO46

U4F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IbexPeak-M_Rev1_0

3

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

CPU

NCTF

RSVD

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N

CLKOUT_PCIE7P

A20GATE

RCIN#

PROCPWRGD

THRMTRIP#

TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 NC_1 NC_2 NC_3 NC_4 NC_5

INIT3_3V#

TP24

PECI

2

+V1.1S_VTT {8,10,11,28,29,38,50,51,55} +V3.3AL {6,23,24,26,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V3.3S {6,8,15,16,22,23,24,25,26,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58}

AH45 AH46

AF48 AF47

U2

AM3 AM1 BG10 T1 BE10 BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39

P6 C10

THERMTRIP_R#

H_A20GATE {43}

BCLK_CPU_N {8} BCLK_CPU_P {8}

H_PECI {8} H_RCIN# {43}

VCCPWRGD_0 {8}

R96 54.9,1%R0402R96 54.9,1%R0402

+V1.1S_VTT

R190

R190 56

56

R0402

GPIO24

SATA4GP

SATA_CLKREQ# GPIO27

internal pull up. default to use internal VccVRM

THERMTRIP# {8,38}

R404 10K R0402

R74 10K R0402 nsR74 10K R0402 ns R79 10K R0402

R93 10KnsR93 10K

ns

1

For differentiate BIOS version

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

27 59Friday, November 27, 2009

A

of

5

D D

+V1.05S

1629mA

C134

C134 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.05S

FB18

1 2

120ohm@100MHz,500mA

ns

C C

+V1.05S

ns

FB0603

C336

1uF/10V,X7R

ns

C122

C122 1uF/10V,X7R

1uF/10V,X7R

VCCAPLL

3251mA

C345

C345 10uF/6.3V,X5R

10uF/6.3V,X5R

+V1.05S

B B

FB19

1 2

120ohm@100MHz,500mA

C128

1uF/10V,X7R

+V1.8S

ns

FB0603

C339

1uF/10V,X7R

+V3.3S

ns

C341

C341 1uF/10V,X7R

1uF/10V,X7R

VCCFDIPLL

C335

1uF/10V,X7R

C337

C337 1uF/10V,X7R

1uF/10V,X7R

4

AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31

AJ30 AJ31

AK24

BJ24

AN20 AN22 AN23 AN24 AN26 AN28

BJ26

BJ28 AT26 AT28 AU26 AU28 AV26 AV28

AW26 AW28

BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27

AN30 AN31

AN35

AT22

BJ18

AM23

U4G

VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15]

VCCIO[24]

VCCAPLLEXP

VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53]

VCCIO[54] VCCIO[55]

VCC3_3[1]

VCCVRM[1] VCCFDIPLL VCCIO[1]

IbexPeak-M_Rev1_0

POWER

VCC CORE

DMI

PCI E*

NAND / SPI

FDI

CRTLVDS

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

HVCMOS

VCCADAC[1]

VCCADAC[2] VSSA_DAC[1] VSSA_DAC[2]

VCCALVDS

VSSA_LVDS

VCC3_3[2] VCC3_3[3] VCC3_3[4]

VCCVRM[2]

VCCDMI[1] VCCDMI[2]

VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]

VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]

AE50 AE52 AF53 AF51

AH38 AH39

AP43 AP45 AT46 AT45

AB34 AB35 AD35

AT24

AT16 AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

86mA

C79

0.1UF/10V,X7R

3

C366

0.01uF/16V,X7R

C137

0.01uF/16V,X7R

C93

C93 1uF/10V,X7R

1uF/10V,X7R

C87

1uF/10V,X7R

+V3.3S

0.1UF/10V,X7R

C130

0.1UF/10V,X7R

+V1.1S_VTT

156mA

VCCADAC

C367

C135

+V1.8S

C102

C102 1uF/10V,X7R

1uF/10V,X7R

+V1.8S

C357

1uF/10V,X7R

VCCTX_LVDS

C139

1uF/10V,X7R

+V3.3S

FB22

1 2

120ohm@100MHz,500mA

+V3.3S

FB7

FB0603FB7

FB0603

1 2

120ohm@100MHz,500mA

+V3.3S

FB0603FB22

FB0603

2

+V1.1S_VTT {8,10,11,27,29,38,50,51,55} +V1.05S {22,23,24,29,50,56,57,58} +V3.3S {6,8,15,16,22,23,24,25,26,27,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.8S {11,26,29,31,49,56,57}

+V1.8S

1

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

28 59Friday, November 27, 2009

A

of

5

+V1.05S

D D

If internal LAN is not used connect to GND directly

FB24

FB24 120ohm@100MHz,500mA

120ohm@100MHz,500mA

+V1.05S

1 2

ns

FB0603

ns

C370

C370 10uF/6.3V,X5R

10uF/6.3V,X5R

C356

C356 1uF/10V,X7R

1uF/10V,X7R

ns

C95

0.1UF/10V,X7R

2222mA

C352

C352 10uF/6.3V,X5R

10uF/6.3V,X5R

C C

0.1UF/10V,X7R

+V1.05S

FB23 120ohm@100MHz,500mA

120ohm@100MHz,500mA

+V1.05S

FB21 120ohm@100MHz,500mA

B B

120ohm@100MHz,500mA

1 2

FB0603FB23

FB0603

FB0603FB21

FB0603

C369

C369 10uF/6.3V,X5R

10uF/6.3V,X5R

C353

C353 10uF/6.3V,X5R

10uF/6.3V,X5R

C355

C355 1uF/10V,X7R

1uF/10V,X7R

C354

1uF/10V,X7R

VCCADPLLB

C81

VCCADPLLA

+V1.8S

C132

C132 10uF/6.3V,X5R

10uF/6.3V,X5R

C105

C105 1uF/10V,X7R

1uF/10V,X7R

C124

1uF/10V,X7R

+V3.3AL

0.1UF/10V,X7R

C88

0.1UF/10V,X7R

C118

+V3.3S

0.1UF/10V,X7R

PCH_EC_RTC

C325

0.1UF/10V,X7R

C127

C127 1uF/10V,X7R

1uF/10V,X7R

C113

1uF/10V,X7R

0.1UF/10V,X7R

C89

VCCADPLLA

VCCADPLLB

C100

+V1.1S_VTT

4.7UF/10V,Y5V

VCCACLK

R98 0 R0402R98 0 R0402

75mA

C123

C123 1uF/10V,X7R

1uF/10V,X7R

C90

C0805

0.1UF/10V,X7R

4

C112

C112 1uF/10V,X7R

1uF/10V,X7R

C94

U4J

AP51 AP53

AF23 AF24

Y20

AD38 AD39 AD41 AF43 AF41 AF42

V39 V41 V42 Y39 Y41 Y42

V9

AU24

BB51 BB53

BD51 BD53

AH23

AJ35

AH35 AF34 AH34 AF32

V12

Y22

P18 U19 U20 U22

V15 V16 Y16

AT18

AU18

A12

IbexPeak-M_Rev1_0

VCCACLK[1] VCCACLK[2]

VCCLAN[1] VCCLAN[2]

DCPSUSBYP

VCCME[1] VCCME[2] VCCME[3] VCCME[4] VCCME[5] VCCME[6] VCCME[7] VCCME[8] VCCME[9] VCCME[10] VCCME[11] VCCME[12]

DCPRTC

VCCVRM[3]

VCCADPLLA[1] VCCADPLLA[2]

VCCADPLLB[1] VCCADPLLB[2]

VCCIO[21] VCCIO[22] VCCIO[23]

VCCIO[2] VCCIO[3] VCCIO[4] DCPSST

DCPSUS

VCCSUS3_3[29] VCCSUS3_3[30] VCCSUS3_3[31] VCCSUS3_3[32]

VCC3_3[5] VCC3_3[6] VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

VCCRTC

POWER

VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13]

USB

VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]

VCCSUS3_3[28]

Clock and Miscellaneous

PCI/GPIO/LPC

VCCSATAPLL[1] VCCSATAPLL[2]

SATA

PCI/GPIO/LPC

CPU

RTC

HDA

VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]

VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]

VCC3_3[14]

VCCIO[9]

VCCVRM[4]

VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13]

VCCIO[14] VCCIO[15] VCCIO[16]

VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20]

VCCME[13] VCCME[14] VCCME[15] VCCME[16]

VCCSUSHDA

V24 V26 Y24 Y26

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23 V23 F24

K49

J38 L38 M36 N36 P36 U35

AD13

AK3 AK1

AH22

AT20

AH19 AD20 AF22 AD19

AF20 AF19 AH20

AB19 AB20 AB22 AD22

AA34 Y34 Y35 AA35

L30

3

C119

0.1UF/10V,X7R

+V1.05S

C140

1uF/10V,X7R

168mA

C129

0.1UF/10V,X7R

C116

0.1UF/10V,X7R

+V3.3AL

+V3.3S

C104

C104 1uF/10V,X7R

1uF/10V,X7R

375mA

VCCSATAPLL

+V1.8S

C114

1uF/10V,X7R

12

D5

12

D7

+V1.05S

+V3.3AL

C117

0.1UF/10V,X7R

1N4148WS

SOD323

1N4148WS

SOD323

C131

0.1UF/10V,X7R

ns

C338

1uF/10V,X7R

R127

10

R0603

R172

10

R0603

C320

10uF/6.3V,X5R

+V1.05S

+V5AL

+V5S

FB17

1 2

120ohm@100MHz,500mA

ns

C321

C321 1uF/10V,X7R

1uF/10V,X7R

ns

C101

C101 1uF/10V,X7R

1uF/10V,X7R

+V3.3AL

+V3.3S

FB0603

2

+V1.1S_VTT {8,10,11,27,28,38,50,51,55} +V1.05S {22,23,24,28,50,56,57,58} +V5AL {32,36,48,49,50,53,56} +V3.3AL {6,23,24,26,27,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V5S {23,25,32,33,34,35,36,37,38,43,51,52,55,56} +V3.3S {6,8,15,16,22,23,24,25,26,27,28,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} PCH_EC_RTC {22} +V1.8S {11,26,28,31,49,56,57}

+V1.05S

1

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

29 59Friday, November 27, 2009

A

of

5

U4H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

D D

C C

B B

AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47

AB5 AB8

AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49

AD7

AE2

AE4

AF12

Y13

AH49

AU4

AF35 AP13 AN34

AF45

AF46

AF49

AF5 AF8

AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47

AH7

AJ19

AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34

AT5

AJ4

AK12 AM41 AN19 AK26 AK22 AK23 AK28

IbexPeak-M_Rev1_0

S_Bot

VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

4

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

3

U4I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

VSS[168]

B7

VSS[169]

BG12

VSS[170]

BB12

VSS[171]

BB16

VSS[172]

BB20

VSS[173]

BB24

VSS[174]

BB30

VSS[175]

BB34

VSS[176]

BB38

VSS[177]

BB42

VSS[178]

BB49

VSS[179]

BB5

VSS[180]

BC10

VSS[181]

BC14

VSS[182]

BC18

VSS[183]

BC2

VSS[184]

BC22

VSS[185]

BC32

VSS[186]

BC36

VSS[187]

BC40

VSS[188]

BC44

VSS[189]

BC52

VSS[190]

BH9

VSS[191]

BD48

VSS[192]

BD49

VSS[193]

BD5

VSS[194]

BE12

VSS[195]

BE16

VSS[196]

BE20

VSS[197]

BE24

VSS[198]

BE30

VSS[199]

BE34

VSS[200]

BE38

VSS[201]

BE42

VSS[202]

BE46

VSS[203]

BE48

VSS[204]

BE50

VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]

BF49

VSS[209]

BF51

VSS[210]

BG18

VSS[211]

BG24

VSS[212]

BG4

VSS[213]

BG50

VSS[214]

BH11

VSS[215]

BH15

VSS[216]

BH19

VSS[217]

BH23

VSS[218]

BH31

VSS[219]

BH35

VSS[220]

BH39

VSS[221]

BH43

VSS[222]

BH47

VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]

AF39

VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

2

1

IbexPeak-M_Rev1_0

S_Bot

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent PCH

PCH

C46

1

30 59Friday, November 27, 2009

A

of

5

D D

4

3

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.8S {11,26,28,29,49,56,57}

2

1

+V1.8S +V1.8S

U10

1

VSS

2

VDD

10 11 12 13 14 15 16 17 18 19 20 21

3 4 5 6 7 8 9

TMDS2+ TMDS2VSS1 TMDS1+ TMDS1VDD1 SEL VSS2 TMDS0+ TMDS0VSS3 TMDSCLK+ TMDSCLKVDD2 VSS4 VDD3 VSS5 VDD4 VSS6

TS3DV421

PM

LVDS_CLKAP{32} LVDS_CLKAM{32}

LVDS_YAP2{32}

LVDS_YAM2{32} LVDS_SEL{26}

LVDS_YAP1{32}

LVDS_YAM1{32}

LVDS_YAP0{32}

LVDS_YAM0{32}

+V3.3S

C C

LVDS_DDC_SEL{26}

G_SMB_CLK{21}

G_SMB_DATA{21}

1 2 3 4 5

U6

IN1 NO1 GND NO2 IN2

TS5A23157

PM

COM1

COM2

10

EDID_CLK {32}

9 8 7 6

PCH_DDC_CLK {25}

PCH_DDC_DATA {25}

EDID_DATA {32}

NC1

V+

NC2

GND

VDD7

VSS8

VDD6

VSS7

ATMDS2+

ATMDS2-

ATMDS1+

ATMDS1-

ATMDS0+

ATMDS0ATMDSCLK+ ATMDSCLK-

VDD5

BTMDS2+

BTMDS2-

BTMDS1+

BTMDS1-

BTMDS0+

BTMDS0BTMDSCLK+ BTMDSCLK-

43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

PCH_LVDS_CLKAP {25}

PCH_LVDS_CLKAM {25} PCH_LVDS_YAP2 {25} PCH_LVDS_YAM2 {25} PCH_LVDS_YAP1 {25} PCH_LVDS_YAM1 {25} PCH_LVDS_YAP0 {25}

PCH_LVDS_YAM0 {25} GPU_LVDS_CLKAP {20}

GPU_LVDS_CLKAM {20} GPU_LVDS_YAP2 {20} GPU_LVDS_YAM2 {20} GPU_LVDS_YAP1 {20} GPU_LVDS_YAM1 {20} GPU_LVDS_YAP0 {20} GPU_LVDS_YAM0 {20}

+V3.3S

U5

1

GPU_LVDS_BKLTEN{21}

PCH_LVDS_BKLTEN{25}

6

NO

IN

2

5

GND

V+

3

4

NC

COM

ts5a3157

PM

LVDS_BLT_SEL {26}

LVDS_BKLTEN {32}

footprint need to change

+V3.3S

U1

1

6

NO

IN

2

5

GND

V+

3

PCH_LVDS_VDDEN{25}

B B

RN4 0

RA0402_4 GM

RN5 0

RN7

RA0402_4

0

GM

0

GM

RA0402_4

1 2 3 4

GM

4

RN6

1 2 3 4

R24 0 R0402

R23 0 R0402

0RA0402_4

GM

PCH_LVDS_CLKAP{25}

PCH_LVDS_CLKAM{25}

PCH_LVDS_YAP2{25} PCH_LVDS_YAM2{25} PCH_LVDS_YAP1{25} PCH_LVDS_YAM1{25} PCH_LVDS_YAP0{25} PCH_LVDS_YAM0{25}

PCH_LVDS_BKLTEN{25} LVDS_BKLTEN {32}

PCH_LVDS_VDDEN{25} LVDS_VDDEN {32}

A A

5

LVDS_CLKAP {32} LVDS_CLKAM {32} LVDS_YAP2 {32} LVDS_YAM2 {32} LVDS_YAP1 {32} LVDS_YAM1 {32} LVDS_YAP0 {32} LVDS_YAM0 {32}

3

NC

ts5a3157

PM

COM

4

EDID_DATA{32}

LVDS_SEL_PCH {26}GPU_LVDS_VDDEN{21}

LVDS_VDDEN {32}

R29 0 R0402

GM

R27 0 R0402

GM

2

PCH_DDC_CLK {25}EDID_CLK{32}

PCH_DDC_DATA {25}

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent LVDS Switch

LVDS Switch

C46

1

31 59Friday, November 27, 2009

of

A

5

F1 1.5A T-Fuse

nsF1 1.5A T-Fuse

ns

FB1 0 R0805FB1 0 R0805

C9

C0402

LVDS_VDDEN

+V3.3S

R15

R15 1K

1K

R0402

R0603

0.1UF/25V,Y5V

Q4

SC70_6

2N7002DW

C8

C8 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C3

C0402

2

D1 1N4148WS

LIDR#{36,43}

D1 1N4148WS

SOD323

LVDS_BKLTEN{31}

HW_OFF_BKLT#{43}

D D

+V3.3S

+V3.3AL

R17

C10

LCDVDD_EN#

3

2

100K

R0402

ns

R18

R18 100K

100K

R0402

Q3

Q3 2N7002

2N7002

SOT23

C10

C0402

ns

0.047uF/16V,X7R

R382

R382 10K

10K

R0402

R16

R16 10K

10K

LVDS_VDDEN{31}

C C

EC_BKLT_PWM{43}

GPU_LVDS_BKLTCTL{21}

LVDS_BKLTCTL{25}

1

R19

R19 100K

100K

R0402

R381 0 R0402R381 0 R0402

FB14 0 R0402

ns

FB15 0 R0402

ns

D2

1

2

BAT54AD2BAT54A

AO6409

6

D

5

S

4

G

Q6

LVDS_VDDGON#

BKLT_PWM

C305

C305 100pF/50V,NPO

100pF/50V,NPO

C0402

12

3

1 2 3

0.01uF/16V,X7R

+V3.3S +V3.3AL

CAM_USB_PN3{26}

B B

CAM_USB_PP3{26}

LCDVDD

C4

10uF/6.3V,X5R

C0805

LCDVDD

R14

R14 100

100

R0603

3456

1

100pF/50V,NPOC6100pF/50V,NPO

R10 0 R0603 nsR10 0 R0603 ns R11 0 R0603R11 0 R0603

R383 0R0603R383 0R0603 R384 0R0603R384 0R0603

CHK2

1 2 4 3

L4_0805

90ohm@100MHz,0.5A

ns

EGA10603V05A1-B

4

C5

C0805

10UF/6.3V,X5R

ns

+VDC

R8 100KR8100K

C6

R9 100KR9100K

D15

ESDPAD_R0603

ns

BKLT_ON {43}

LCDVDD

R5

2.2K

R0402

ns

EDID PWR

C7

0.1UF/10V,X7R

C0402

LVDS_CAM_USB_PN3 LVDS_CAM_USB_PP3

D16

12

EGA10603V05A1-B

ESDPAD_R0603

ns

+VDC

F2 1.5A T-Fuse

R0603

1 2

FB16

100ohm@100MHz,3A

FB0805

3

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +VDC {40,46,48,49,50,51,52,55,56,57} +V3.3AL {6,23,24,26,27,29,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V5AL {29,36,48,49,50,53,56} +V5S {23,25,29,33,34,35,36,37,38,43,51,52,55,56}

LCDCON1

LCDCON2X20P_2

CNS40_LCDB

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930

31

33

35

37

39

41

32 34 36 38 40 42

41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

LVDS_CAM_USB_PN3 LVDS_CAM_USB_PP3

nsF2 1.5A T-Fuse

ns

LVDS_YAM0{31} LVDS_YAP0{31}

LVDS_YAM2{31} LVDS_YAP2{31}

EDID_DATA{31}

C307

C0603

0.1uF/25V,X7R

ns

LCDVDD

EDID_CLK{31}

LCDVDD

INVT_VDD

C306

0.1uF/25V,X7R

C0603

+5VAL_Camera BKLT_PWM

EDID PWR

BKLT_ON

2

LVDS_YAM1 {31} LVDS_YAP1 {31}

LVDS_CLKAP {31}

LVDS_CLKAM {31}

1

S46P VerB:LVDS CONN换为40pin立式 090710

+V5AL

+V5S

R7

R6

R6 0

0

R0805

ns

R2 0 R0805R2 0 R0805

2

R3

R3 10K

10K

R0402

ns

R1 10K

R0402

ns

3

Camera_ON{43}

1

R4

R4 100K

100K

R0402

ns

Q2

2

2N7002E-T1

SOT23

ns

VerB:Reverse Camera PWR control Circuit 071026

+5VAL_Camera

500mA

3

C2

Q1

0.1uF/10V,X5R

SOT23

C0402

AO3415

1

ns

Add +5S to CAM POWER

许沐锌

081111

C1

C1 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

E1

1

EMI

ns

1

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent

LVDS&Inverter CONN

LVDS&Inverter CONN C46

C46

1

A

32 59Friday, November 27, 2009

A

of

5

+V3.3S +V3.3S +V3.3S

R493

R492

4.7K

ns

GM/HDMI

D D

+V3.3S

0.01uF/25V,X7R

GM/HDMI

GND

MCH_CLK_D4+{25}

C C

Colay 8101 and 7318 by xiezx

B B

A A

MCH_CLK_D4-{25}

intel demo 499 and chro demo 1.2k by homy 1029

ns

+V3.3S

C179

0.01uF/25V,X7R

GM/HDMI

GND

C166

0.01uF/25V,X7R

C165

GM/HDMI

U25

IN_D0+{25} IN_D0-{25}

IN_D1+{25} IN_D1-{25}

IN_D2+{25} IN_D2-{25}

1.2K

CH7318

Colay 8101 and 7318 by xiezx

R535

R534

4.7K

8101

PC0

PC1

R530

4.7K

7318

GND

5

C156

0.01uF/25V,X7R

GM/HDMI

DDC_EN

CFG

DDCBUF_EN

31

36

33

34

35

32

G7

g6G6g7

GND6

GND7

VCC3V5

37 38 39 40 41 42 43 44 45 46 47 48

DDC_EN

GND8

FUNCTION3

FUNCTION4

IN_D1IN_D1+ VCC3V6 IN_D2IN_D2+ GND9 IN_D3IN_D3+ VCC3V7 IN_D4IN_D4+

GND1VCC3V2FUNCTION13FUNCTION24GND15ANALOG1(REXT)

CH7318

R201

GND

6

GND

PC0

PC1

GM/HDMI

GND

+V3.3S

R202

499,1%

PS8101

GND

+V3.3S+V3.3S

R537

2.2K

GM/HDMI

R0402

change 4.7k to 2.2k 080508 hads

5VDDCCK_HDMI

HDMIHP_C

5VDDCDA_HDMI

29

27

28

26

30

GND5

VCC3V4

SCL_SINK

SDA_SINK

HPD_SINK

OUT_D1-

OUT_D1+

OUT_D2-

OUT_D2+

OUT_D3-

OUT_D3+

OUT_D4-

OUT_D4+

HPD_SOURCE7SDA_SOURCE8SCL_SOURCE9ANALOG210VCC3V111GND2

GM_HDMI_DDC_CLK

GM_HDMI_DDC_DATA

MCH_HDMI_HPD

R536

2.2K

GM/HDMI

R0402

TMS_EN

G5

25

g4G4g5

G1

g1

49

gnd10

TMDS_EN

24

GND4

23 22 21

VCC3V3

20 19 18

GND3

17 16 15

VCC3V2

14 13 G2

g2

G3

g3

gnd18

12

G8

GND

C142

0.01uF/25V,X7R

GM/HDMI

+V3.3S

{25}

GM_HDMI_DDC_DATA {25} GM_HDMI_DDC_CLK {25}

CFG

IFPC_TXD2P IFPC_TXD2N

IFPC_TXD1P IFPC_TXD1N

IFPC_TXD0P IFPC_TXD0N

IFPC_TXC IFPC_TXC#

DDCBUF_EN

GND

DDC_EN

GM/HDMI

+V3.3S

4

R494

4.7K

GM/HDMI

R495

0

ns

GND GND

C178

0.01uF/25V,X7R

IFPC_TXD2P{20} IFPC_TXD2N{20}

IFPC_TXD1P{20} IFPC_TXD1N{20}

IFPC_TXD0P{20} IFPC_TXD0N{20}

4

IFPC_TXC{20}

IFPC_TXC#{20}

GM/HDMI

R498

4.7Kns

TMS_EN

R499

R499 0

0

GM/HDMI

C155

0.01uF/25V,X7R

3

AD+ {36,46,48} +V5S {23,25,29,32,34,35,36,37,38,43,51,52,55,56} +V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V3.3AL {6,23,24,26,27,29,32,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V3.3GPU {17,20,21,34,52,57}

R188

R188 0

0

R0402

PM/HDMI

3

+V5_HDMI

R497

2.2K

5VDDCCK_HDMI

GM/HDMI

Note:The ESD protection devices should be placed as close to the HDMI connector as possible so that when ESD strikes occur, the discharges can be quickly absorbed or diverted to the ground/power plane before it is coupled to another signal path nearby.

GU3

AZ1045

IFPC_TXD6P_esd

10

NC4

IFPC_TXD6N_esd

9

NC3 GND NC2

HDMI

GU4

NC4 NC3 GND NC2

HDMI

IFPC_TXD4P_esd

8 7 6

IFPC_TXD5N_esd

10 9 8 7 6

先断开

1

LINE_1

2

GC1450.1uF/10V,X7R

C0402

HDMI

GC146 0.1uF/10V,X7R

C0402

HDMI

+V5_HDMI

132

R183

4.7K

PM/HDMI

LINE_2

3

VDD

4

LINE_3 LINE_45NC1

1

LINE_1

2

LINE_2

3

VDD

4

LINE_3 LINE_45NC1

R199

D8

0

BAT54A

R0402

PM/HDMI

R192

4.7K

PM/HDMI

5VDDCCK_HDMI

C159

C159 10pF/50V,NPO

10pF/50V,NPO

C0402

PM/HDMI

GND_HDMI

5VDDCDA_HDMI

C143

C143 10pF/50V,NPO

10pF/50V,NPO

C0402

PM/HDMI

GND_HDMI GND_HDMI GND_HDMI

IFPC_TXD4N_esd

IFPC_TXD5P_esd

IFPC_TXC_esd IFPC_TXC#_esd

5VDDCCK_HDMI 5VDDCDA_HDMI

+V5_HDMI

GND和GND_HDMI,

HDMIHP_C

+V5_HDMI

R496

2.2K

5VDDCDA_HDMI

GM/HDMI

HDMI

R483 0 R0603

R483 0 R0603 R479 0 R0603

R479 0 R0603

HDMI

l4_0805 ns

CHK4 100M0.33A

4 3 1 2

CHK5

4 3 1 2

l4_0805

R502 0 R0603R502 0 R0603 R489 0 R0603R489 0 R0603

R523 0 R0603HDMIR523 0 R0603HDMI R521 0 R0603

R521 0 R0603

HDMI

l4_0805

CHK6 100M0.33A

4 3 1 2

CHK7 100M0.33A

4 3 1 2

l4_0805

R538 0 R0603

R538 0 R0603 R529 0 R0603

R529 0 R0603

HDMI

HDMI HDMI

HDMI

Colay COMCHK with 0ohm

+V3.3GPU +V3.3GPU

GR18

4.7K

R0402

PM/HDMI

HDMI_DDC_CLK{20}

HDMI_DDC_DATA{20}

PM/HDMI

+V3.3GPU +V3.3GPU

GR9

4.7K

R0402

PM/HDMI

GND_HDMI

ns

100M0.33A

ns

1

2

PM/HDMI

BSS138

BSS138 GQ4

GQ4

R205 0 R0402

ns

1

2

PM/HDMI

BSS138

BSS138 GQ3

GQ3

R169 0 R0402

IFPC_TXD6P_esd IFPC_TXD6N_esd

IFPC_TXD5P_esd IFPC_TXD5N_esd

IFPC_TXD4P_esd IFPC_TXD4N_esd

GND_HDMI

IFPC_TXC_esd IFPC_TXC#_esd

3

ns

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

GND_HDMIGND_HDMI

GND_HDMI

从一博回来后再开桥连上

GQ2

3

2N7002

SOT23

1

GR5

PM/HDMI

2

100K

R0402PM/HDMI

2

HDMI_CON1

D2+ D2 SHTELD D2D1+ D1 SHTELD D1D0+ D0 SHTELD D0CK+ CK SHTELD CKCEC RESERVED SCL SDA DCC/CEC_GND +5V HP_DET

HDMI

+V3.3GPU

GR7

GR7 10K

10K

R0402PM/HDMI

GQ1

3

2N7002

SOT23

PM/HDMI

2

GND1 GND2

GND3 GND4

HDMI_D_1A

HDMI_D_1A <Part Number>

+V3.3AL

1

GC36

C0402

PM/HDMI

100pF/50V,NPO

20 21

22 23

GND_HDMI

GR12

GR12 1K

1K

R0402

PM/HDMI

GR10

GR10 10K

10K

R0402

PM/HDMI

+V5S

FB6

D6

FB6

120ohm@100MHz,500mA

1 2

1N5819HW-F

SOD123

HDMI

GPU_HDMI_HPD {21,43}

120ohm@100MHz,500mA

1 2

FB0603

HDMI

IFPC_TXD6P_esd IFPC_TXD6N_esd

IFPC_TXD5P_esd IFPC_TXD5N_esd

IFPC_TXD4P_esd IFPC_TXD4N_esd

IFPC_TXC_esd IFPC_TXC_esd IFPC_TXC#_esd

+V5_HDMI

R154

C136

0.1UF/25V,Y5V

C0402

HDMI

Page Name

Page Name Size

Size

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

R154 100K

100K

R0402

HDMI

GND_HDMIGND_HDMI

D23

ns/HDMID23

ns/HDMI

DIODE_SCHTK MLSEP

5

6

IN4

OUT4

4

7

IN3

OUT3

3

8

GND

GND1

2

9

IN2

OUT2

1

10

IN1

OUT1

D24

1

10

IN1

OUT1

2

9

IN2

OUT2

3

8

GND

GND1

4

7

IN3

OUT3

5

6

IN4

OUT4

DIODE_SCHTK MLSEP

GND_HDMI

Project Name Rev

A2

1

IFPC_TXD6P_esd IFPC_TXD6N_esd

IFPC_TXD5P_esd IFPC_TXD5N_esd

IFPC_TXD4P_esd IFPC_TXD4N_esd

IFPC_TXC#_esd

ns/HDMI

TOPSTAR TECHNOLOGY

bent

HDMI CONN

C46

1

A

33 59Friday, November 27, 2009

of

5

DCC

A

CRT INTERFACE

4

3

2

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57 +V5S {23,25,29,32,33,35,36,37,38,43,51,52,55,56} +V3.3GPU {17,20,21,33,52,57}

1

D

CRT_RED{20}

CRT_RED_R{25}

CRT_GREEN{20}

CRT_GREEN_R{25}

CRT_BLUE{20}

CRT_BLUE_R{25}

B B

CRT_HSYNC_R{25}

CRT_VSYNC_R{25}

R569

R553 0 GMR553 0 GM

150ohm (From GPU to CONN)

CRT_HSYNC{20}

CRT_VSYNC{20}

Place close to VGA port

PM

0GR45PM0GR45

R571

GM

0

0GR44 PM0GR44 PM

GM

0

0GR43 PM0GR43 PM

电阻前走线阻抗

R219

0 GM

0GR17 PM0GR17 PM

0GR21 PM0GR21 PM

R2150GMR2150GM

5

50ohm

IR8

IR8 150,1%

150,1%

IR7

IR7 150,1%

150,1%

IR6

IR6 150,1%

150,1%

GND_VGA

ns

+V5_VGA

GND_VGA

+V5_VGA

R659

0

R0603

IC22

5.6pF/50V,NPO

R660

0

R0603

IC23

5.6pF/50V,NPO

R661

0

R0603

IC24

5.6pF/50V,NPO

IC10

0.1UF/25V,Y5V

reserved ciucuit possibility to Cost down 1G125 follow design guide--0929

VerC: Del VR7

IU2

IU2 74AHCT1G125

74AHCT1G125

SOT23_5

1

OE#

VCC

2

A GND3Y

IU1

IU1 74AHCT1G125

74AHCT1G125

SOT23_5

1

OE#

VCC

2

A GND3Y

VSYNC

3

ID1

ID1 BAT54SPT

BAT54SPT

SOT23

ID2

HSYNC

3

BAT54SPT

SOT23

IC17

5.6pF/50V,NPO

NV suggest:22pf

IC16

5.6pF/50V,NPO

IC14

5.6pF/50V,NPO

IC3

0.1UF/25V,Y5V

5

CRT_H_SYNC

4

5

CRT_V_SYNC

4

+V5_VGA

2

IC8

0.1UF/25V,Y5V

1

GND_VGA

+V5_VGA

2

IC5

0.1UF/25V,Y5V

1

GND_VGA

1 2

IC6

0.1UF/25V,Y5V

4

Cross moat place

IFB4

IFB4 47ohm/100MHz,500mA

47ohm/100MHz,500mA

FB0603

IFB3

IFB3 47ohm/100MHz,500mA

47ohm/100MHz,500mA

FB0603

IFB2

47ohm/100MHz,500mA

Near U5/U6 ASAP

IR2 39IR2 39 IR1 39IR1 39

IC18

5.6pF/50V,NPO

IC15

5.6pF/50V,NPO

IC13

5.6pF/50V,NPO

HSYNC

VSYNC

NV suggest:2pf

GND_VGA

FB0603IFB2

FB0603

GND_VGA

+V3.3S +V3.3S +V3.3S +V3.3S

IC2

0.1UF/25V,Y5V

Change the ESD diode connection by bent 091022

ROUT

ID8

BAT54SPT

SOT23

132

GND_VGA

ID7

BAT54SPT

SOT23

ID6

BAT54SPT

SOT23

IC1

0.1UF/25V,Y5V

GND_VGA

CRT_DDC_DATA_R{25}

CRT_DDC_CLK_R{25}

CRT_DDC_CLK{20}

+V5_VGA

132

+V5_VGA

132

+V5_VGA

CRT_DDC_DATA{20}

IC20

0.1UF/25V,Y5V

GOUT

BOUT

ESD: NV suggest use +3.3V Layout note:

1. +3.3V and GND Route >15mils trace width

2. No more than 75mils

3. ESD diode should no more than 10pf cap.

R595

+V5S

ID5

+V3.3S

IC21

0.1UF/25V,Y5V

R509

GM

0

R600

PM

0

R510

GM

0

VerC: Change to bat54s

PM

0

Demo has no voltage lever shifter

3

1 2

1N5819

SOD123

IC19

0.1UF/25V,Y5V

Cross moat place

IFB1

1 2

120ohm@100MHz,500mA

FB0603

+V3.3S

+V3.3GPU

R599

8.2K

R0402

PM

+V3.3S

+V3.3GPU

R596

8.2K

R0402

PM

GND_VGA

R259

8.2K

R0402

GM

R244

8.2K

R0402

GM

IC12

0.1UF/25V,Y5V

2

IR5

IR5 100K

100K

GND_VGA

Cross moat place

Q16

Q16 BSS138

BSS138

SOT23

3

1

Gate_vgaGate_vga

Q14

Q14 BSS138

BSS138

SOT23

3

1

+V5_VGA

GND_VGA

R598

0

R0402

PM

VGA CONNECTOR

CONNECTOR TOP VIEW

GND

6

R

1

GND

7

G

2

GND

8

B

3

NC

9

NC

4

GND

10

GND

5

shell

16 17

Assy

S46/

5VDDCDA

5VDDCCK

+V3.3S

R0402

GM

R597

+V3.3GPU

GND_VGA

VGA1

VGADMF

NC

11

SDA

12

HSYNC

13

VSYNC

14

CLK

15

shell

C10518-11505-L

修改成跟

IC11

IC11 15PF/50V,NPO

15PF/50V,NPO

ns

M21

一致的

+V5_VGA

IR4

IR3

2.2K

Page Name

Size

Project Name Rev

Custom

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

IC7

IC7 15PF/50V,NPO

15PF/50V,NPO

VGA Conn。LJ081223

ID4

2

3

1

BAT54SPT

SOT23

ID3

2

3

1

BAT54SPT

SOT23

IC4

IC4 15PF/50V,NPO

15PF/50V,NPO

+V5_VGA

VerC: Change to bat54s

GND_VGA

VerB:BAV99 for cost down 071016

+V5_VGA

GND_VGA

TOPSTAR TECHNOLOGY

bent

CRT Interface

C46

1

5VDDCDA

5VDDCCK

IC9

IC9 15PF/50V,NPO

15PF/50V,NPO

ns

GND_VGA

由

DIODES改为PHILIPS

34 59Friday, November 27, 2009

HSYNC VSYNC

of

的

A

5

4

3

2

+V5S {23,25,29,32,33,34,36,37,38,43,51,52,55,56} +V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58}

1

D D

+V3.3S

FB27 0 R0805

ns

4.7uF/10V,Y5VCT5

C0805

ns

+V5S

Average 1A,Peak 1.5A

FB26 0 R0805FB26 0 R0805

4.7uF/10V,Y5VCT4

C0805

C396

0.1UF/25V,Y5V

C397

0.1UF/25V,Y5V

V_HDD

V3.3_SATA

Close to connector as possible

SATA_TXP0{22} SATA_TXN0{22} SATA_RXN0{22} SATA_RXP0{22}

the same distance to connector

0.01uF/25V,X7R

C414

C0402C414

C0402

C413

C0402C413

C0402

0.01uF/25V,X7R

V_HDD

+V5S

FB20 0 R0805FB20 0 R0805

C C

Average 1A,Peak 1.5A

C330

4.7uF/10V,Y5VCT3

C0805

C330

0.1UF/25V,Y5V

V_ODD

C334

0.1UF/25V,Y5V

SATA_TXP1{22} SATA_TXN1{22}

SATA_RXN1{22} SATA_RXP1{22}

C344 0.01uF/25V,X7RC344 0.01uF/25V,X7R C342 0.01uF/25V,X7RC342 0.01uF/25V,X7R

V_ODD

B B

VerB:change the footprint the same as S46P

SATA_HDD1

2

TX

3

TX#

5

RX#

6

RX

8

VCC3_0

9

VCC3_1

10

VCC3_2

14

VCC5_0

15

VCC5_1

16

VCC5_2

18

REEVE

20

VCC12_0

21

VCC12_1

22

VCC12_2

SATA_HDD CONN

SATA_D_50B

C405

0.1UF/25V,Y5V

ns

GND0 GND1 GND2

GND3 GND4 GND5

GND6 GND7

GND23 GND24

SATA_CON1

S1

GND1

S2

A+

S3

A-

GND6

S4

GND2

S5

B-

S6

B+

S7

GND3

P1

DP

P2

+5V_1

P3

+5V_2

P4

MD

GND7

P5

GND4

P6

GND5

SATA_ODD CONN

SATA_S_50G

1 4 7

11 12 13

17 19 23

24

14

15

C406

0.1UF/25V,Y5V

ns

V3.3_SATA

ASSY

SATAHDD_B1

Screw 2*5mm

ASSY

SATAHDD_B2

Screw 2*5mm

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent SATA HDD&ODD

SATA HDD&ODD

C46

1

A

35 59Friday, November 27, 2009

A

of

5

A

USB Board CONN

D D

4

24pin 0.5mm bot FFC

24

23

22

21

20

USB_OC#5{26} USB_OC#2{26}

USB_PN11{26} USB_PP11{26}

USB_PN10{26} USB_PP10{26}

USB_PN4{26} USB_PP4{26}

+V5AL

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

USB_CONN1

3

+V5S {23,25,29,32,33,34,35,37,38,43,51,52,55,56} +V3.3AL {6,23,24,26,27,29,32,33,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V5AL {29,32,48,49,50,53,56} +VDC {32,40,46,48,49,50,51,52,55,56,57} AD+ {46,48}

26

25

2

+V5S +V5S

C401

0.01uF/25V,X7R

C0402

C395

0.01uF/25V,X7R

C0402

1

C C

+V3.3AL +V5S +V3.3AL +V5S

R163

1

Q11

Q11 2N7002E-T1

2N7002E-T1

2

TR2 0 R0402TR2 0 R0402

ns

3

R163 10K

10K

R0402

R0402 ns

ns

1

Q10

Q10 2N7002E-T1

2N7002E-T1

ns

3

TPDAT{43}TPCLK{43}

2

TR1 0 R0402TR1 0 R0402

B B

3

142

TLSW1

TLSW1 TMG-534-V

TMG-534-V

BUTTON4_S

3

142

TRSW1

TRSW1 TMG-534-V

TMG-534-V

BUTTON4_S

132

+V5S

132

+V5S

D14

BAT54SPT

D13

D13 BAT54SPT

BAT54SPT

1

2

3

7

3

7

4

5

8

5

8

6

CNS6_1_R1

Conn 6Pin

Conn 6Pin TP_CON1

TP_CON1

VerB:converse the connection of TP_CON1

+V5S

C125

C120

C0603

0.1UF/25V,Y5V

C0402

C0603

1UF/10V,Y5V

LEFT RIGHT

TP_TPDAT_R TP_TPCLK_R

TPDAT TPCLK

+V5S

R146

R146 47K

47K

R0402

R0402 ns

ns

Add pull res

R158

R158 47K

47K

R0402

R0402 ns

ns

+V3.3AL

C126

C0402

0.1UF/25V,Y5V

C283

100pF/50V,NPO

C281

100pF/50V,NPO

R153

R153 10K

10K

R0402

R0402 ns

ns

TP_TPDAT_RTPCLK TPDATTP_TPCLK_R

Ns pull up hear to avoid a leak of current.

LEFT

R358

R358 1K

1K

R0402

RIGHT

R352R04021KR352R0402 1K

power button Conn

PWRCONN1

21

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

Isense_SYSP{46,54}

PWR_SW_VCC2{39,43,48}

88242_2001

16

151516

18

171718

20

191920

22

CNS2x10_1_R

CNS2x10_1_R 620902010002

620902010002

Page Name

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

AD+AD+

LIDR# {32,43}

+V3.3AL

TOPSTAR TECHNOLOGY

bent

USB2.0&&LED CONN&Qkey CONN

C46

36 59Friday, November 27, 2009

A

of

A

5

D D

AZALIA_CODEC_RST#{22}

AZALIA_CODEC_BITCLK{22}

AZALIA_CODEC_SYNC{22}

AZALIA_CODEC_SDOUT{22}

GAIN0 GAIN1

AZALIA_SDATAIN0{22}

INT_MIC_L

JACK_DET_A

MIC2_L

MIC2_R

VCC5CDC VCC5CDC

GND_AUD

R343 51K R0402R343 51K R0402

BTL_BEEP{43}

R333 75K R0402R333 75K R0402

SPKR{22}

JACK_DET_B

R378 5.11K,1% R0402 nsR378 5.11K,1% R0402 ns

JACK_DET_A

C C

B B

A A

R354 5.11K,1% R0402R354 5.11K,1% R0402 R353 20K,1% nsR353 20K,1% ns

JACK_DET_B

R379 20K,1%R379 20K,1%

connecr mic1_jd to senseB and reserved route to senseA By Johan 071224

C275 1uF/10V,X7R

C0603

C276 1uF/10V,X7R

C0603

R341

R337

4.7K

All of JD resistors should be placed as close as possible to the sense pin of codec.

HP_DET MIC1_JD

GAIN0

00

10 1

FB13

1 2

C303 0.1UF/25V,Y5V

ns

5

C279

C279 100pF/50V,NPO

100pF/50V,NPO

VerA:follow the DEMO design in MIC1&MIC2 071108

Av(inv)

GAIN1

6dB

10dB

10

15.6dB

21.6dB

1

nsFB0805FB13

nsFB0805

300ohm@100MHz,1.5A

GND_AUD

R367

R367 10K

10K

ns

R368

R368 10K

10K

+V3.3S

GND_AUD

4

ICTP ns

ICTP ns ICTP ns

ICTP ns

R359 75 R0402R359 75 R0402 R364 75 R0402R364 75 R0402

T30ICTP nsT30ICTP ns T29ICTP nsT29ICTP ns

R374

R374 10K

10K

ns

R373

R373 10K

10K

4

C280

0.1UF/25V,Y5V

T27

A_GPIO0

T28

A_GPIO1

R348 33R348 33

C284 4.7uF/10V,X5R C0805C284 4.7uF/10V,X5R C0805 C289 4.7uF/10V,X5R C0805C289 4.7uF/10V,X5R C0805

C297 1uF/10V,Y5V C0603C297 1uF/10V,Y5V C0603 C296 1uF/10V,Y5V C0603C296 1uF/10V,Y5V C0603

INT_MIC_L_R

INT_MIC_L

R574 1KR574 1K

AMP_OUT_R

C286 0.22uF/10V,X7R

GND_AUD

AMP_OUT_L

C290 0.22uF/10V,X7R

IO_INTSPK1

CNS4_V

1

5

1

5

2

3

4

6

4

6

C0603

C278

0.1UF/25V,Y5V

2

GPIO0

3

GPIO1

11

REST#

6

BITCLK

10

SYNC

5

SDOUT

8

SDIN

12

PC-BEEP

13

JD1

14

LINE2-L

15

LINE2-R

16

MIC2-L

17

MIC2-R

18

CD-L

20

CD-R

21

MIC1-L

22

MIC1-R

23

LINE1-L

24

LINE1-R

SHUTDOWN# GAIN0 GAIN1

C274

C274 10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

9

38

VDD11VDD2

AVDD125AVDD2

ALC662

GND14GND27CD-GND19AGND126AGND2

42

T31

GND_AUD

ICTP

ns

FB25

FB0805

1 2

300ohm@100MHz,1.5A

D27

ESDPAD_R0603

EGA1-0603-V05

ns

0.47uF/25V,Y5V

C0603

C287 0.22uF/10V,X7R

+INTSPR

-INTSPR +INTSPL

-INTSPL

12

C391

100pF/50V,NPO

C0402

GND_AUD

INPUT:STEREO MIC-IN OUTPUT:CENT/LFE

onboard stereo microphone

R362 20KR362 20K

C292

R365 10KR365 10K

C0603

R366 20KR366 20K

3

C291

0.1UF/25V,Y5V

LINE1-VREFO-R

SIDESURR-OUT-L

SIDESURR-OUT-R

U21

U21 TPA6017A2

TPA6017A2

sop20_0d65_4d4g

17

RIN-

7

RIN+

9

LIN+

10

BYPASS

5

LIN-

12

NC SHDWN#19GND1

2

GAIN0

3

GAIN1

3

VCC5CDC

600ohm@100MHz,1.5A FB0805

C298

0.1UF/25V,Y5V

GND_AUD

FRONT-OUT-L FRONT-OUT-R

VREF

MIC1-VREFO-L

LINE1-VREFO-L

MIC2-VREFO

LINE2-VREFO

MIC1-VREFO-R

DCVOL

JD2

CEN-OUT

LFE-OUT

SPDIFI/EAPD

SPDIFO

SURR-OUT-L

JDREF

SURR-OUT-R

ALC662QFPS48_0D5_1D6

+

1 2

MIC1

MIC1 Microphone

Microphone

BZ_D6027

ASSY

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

16

VDD

6

PVDD1

15

PVDD2

1 11

GND2

13

GND3

20

GND4

21

GND5

FB12

1 2

C301

C301 10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

Cross moat place

U20

C302 4.7uF/10V,X5R

C0805

CT1

ns+CT1

ns

35

+

100uF/10Vct6032

CT2

ns+CT2

ns

36

+

100uF/10Vct6032

C304 4.7uF/10V,X5R

37

C0805

C0805 27 28

29 30 31 32 33 34 43 44 45 46 47 48

39 40 41

C299 0.1UF/25V,Y5VC299 0.1UF/25V,Y5V C300

VREFOUT

R370 4.7K R0402R370 4.7K R0402

MIC2_REF

R371 4.7K R0402

R372 10K nsR372 10K ns

EAPD SHUTDOWN#

R360 0 R0402

ns

AMP_OUT_L

R363 20K,1%R363 20K,1%

AMP_OUT_R

+INTSPR

-INTSPR +INTSPL

-INTSPL

C293

0.1UF/10V,X7R

0.1UF/10V,X7R C295

C295

0.1UF/10V,X7R

2

+V5S

Change to cap for esd

GND_AUD

3

2

AMP_SHDW{43}

PQ76

2N7002

SOT23

1

2

By Johan 071228

C288

0.1UF/25V,Y5V

C0805C300

C0805

10UF/6.3V,X5R

ns

VCC5CDC

PQ75

PQ75 2N7002

2N7002

SOT23

1

VCC5CDC

4.7uF/10V,Y5VC294

C0805

GND_AUD

SURR_OUT_L SURR_OUT_R

INT_MIC_L_R

JACK_DET_B

3

2

R375 75 R0402R375 75 R0402 R376 75 R0402R376 75 R0402

GND_AUD

AMP_SHDW AMP_SHDW

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V5S {23,25,29,32,33,34,35,36,38,43,51,52,55,56}

100pF/50V,NPO

SURR_OUT_L SURR_OUT_R

HP_DET

D39

ESDPAD_R0603

EGA1-0603-V05

ns

Headphone Jack

INPUT:HEADPHONE/LINE-OUT OUTPUT:FRONT L/R

MIC2_REF

1 2

MIC2_L

MIC2_R

MIC1_JD

D38

ESDPAD_R0603

EGA1-0603-V05

ns

Stereo Microphone Jack

INPUT:STEREO MIC-IN OUTPUT:CENT/LFE

SURR_OUT_RSURR_OUT_L

GND_AUD GND_AUD

R0402

100pF/50V,NPO

R637

R639

FB28 300ohm@100MHz,1.5A

1 2

FB30 300ohm@100MHz,1.5A

1 2

12

C428

0.1uF/10V,X7R

D35

1N4148WS

SOD323

D37

1N4148WS

SOD323

R638

R646

4.7K

R0402

FB29 300ohm@100MHz,1.5A

1 2

FB31 300ohm@100MHz,1.5A

1 2

12

GND_AUD GND_AUDGND_AUDGND_AUDGND_AUD

PQ70

2N7002

SOT23

1

0.1uF/10V,X7R

PQ71

3

2N7002

SOT23

1

2

R643

R643 10K

10K

GND

Page Name

Page Name Size

Size

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

GND_AUD GND_AUD

Solve audio curve cut issue By Johan 071224

12

D33

D34

ESDPAD_R0603

EGA1-0603-V05

ns

FB0805

FB0805 FB0805

FB0805

C423

C423 100pF/50V,NPO

100pF/50V,NPO

C0402

ns

GND_AUD GND_AUDGND_AUD GND_AUD

D32

ESDPAD_R0603

EGA1-0603-V05

ns

FB0805

FB0805 FB0805

FB0805

C430

MIC2_L

MIC2_R

GND_AUD GND_AUD

VCC5CDC

1

SOT23

GND_AUD

Project Name Rev

C

Date: Sheet

D33

ESDPAD_R0603

EGA1-0603-V05

ns

C422

C422 100pF/50V,NPO

100pF/50V,NPO

C0402

ns

used for enhancing Audio quality and ESD ability.

GND_AUD GND_AUD

Solve audio curve cut issue By Johan 071224

12

D36

ESDPAD_R0603

EGA1-0603-V05

ns

C420

100pF/50V,NPO

C0402

ns

change to ns for esd By Johan 071228

C429

100pF/50V,NPO

C0402

R640

R640 10K

10K

3

Q32

Q32 2N7002

2N7002

2

12

change to ns for esd By Johan 071228

GND_AUD

12

C424

C424 100pF/50V,NPO

100pF/50V,NPO

C0402

ns

add cap for esd By Johan 071228

C421

C421 100pF/50V,NPO

100pF/50V,NPO

C0402

SHUTDOWN#

R644

R644 100K

100K

TOPSTAR TECHNOLOGY

bent

bent AZALIA(ALC883)

AZALIA(ALC883)

C46

1

1 4 2 5 6 3 7 8

37 59Friday, November 27, 2009

LINE_OUT1

L

AZALIAJACK

AUDIO8B

MIC_IN1

L

AZALIAJACK

AUDIO8B

of

R

A

5

+V3.3S+V5S

Q13

Q13 AO3415

C215

C215 1000pF/50V,X7R

1000pF/50V,X7R

BT

R256 1KBTR256 1KBT

2

BT

AO3415

R230 0

3

BT

1

BT

TPCON_USB

CNS10_0D8_R

11

12

BT_CON

M46 VERB:CHANGE BT_CON THE SAME AS X01--XIEZX

BT

R227 0 R0805BTR227 0 R0805BT R224 0 R0805nsR224 0 R0805ns

R245

R245 100K

100K

BT

D D

BT_PWRON{43} BT_ON {32}

R265 0 nsR265 0 ns

R266 1KBTR266 1KBT

BT

BT_ON#

3

Q15

Q15 2N7002E-T1-E3

2N7002E-T1-E3

SOT23

1

BT

2

R267

R267 100K

100K

BT

TCM

R610

R610 10K

10K

TCM

R620

R620 10K

10K

ns

+V3.3S

R624

R624 10K

10K

TCM

LPCPD# LPCPP

PM_CLKRUN#

R618

R618 10K

10K

TCM

LPC_FRAME#{22,40,43}

BUF_PLT_RST#{8,17,26,39,40,41,43,44}

CLK_TCMPCI{26}

LPC_AD0{22,40,43} LPC_AD1{22,40,43} LPC_AD2{22,40,43} LPC_AD3{22,40,43}

INT_SERIRQ{22,43}

PM_CLKRUN#

LPCPD#

LPCPP

R622

R622 10K

10K

TCM

C C

C404

1uF/10V,X7R

C0603

TCM

U30

22

LFRAME#

16

LRESET#

21

LCLK

26

LAD0

23

LAD1

20

LAD2

17

LAD3

27

SERIRQ

15

CLKRUN#

28

LPCPD#

9

BA0

3

BA1

7

PP

14

NC-P

TCM

SOP28_0D65_6D1

1 2 3 4 5 6 7 8 9

10

+V3.3S_BT

1 2 3 4 5 6 7 8 9 10

BT

VDD1 VDD2 VDD3

GND1 GND2 GND3 GND4

4

NC1 NC2 NC3 NC4 NC5 NC6

BT C218

BT

NC

C218

0.1UF/10V,X7R

R233 0BTR233 0BT

R654 100KnsR654 100Kns

C214

0.22uF/10V,X7R

10 19 24

4 11 18 25

1 2 5 6 8 12 13

BT

10uF/6.3V,X5R

C409

TCM

R228 0 R0402BTR228 0 R0402BT R229 0 R0402BTR229 0 R0402BT

R655 0 R0402BTR655 0 R0402BT R656 0 R0402BTR656 0 R0402BT

+V3.3S_BT

后续要改, 发

R615 0

R0805 TCM

C411

0.1UF/25V,Y5V

TCM

BT_PWRON {43}

+V3.3S

BT_USB_PP2 {26} BT_USB_PN2 {26}

USB_PP5 {36}

USB_PN5 {36}

HW_RATIO_OFF# {43}

ECN 改BOM

C407

0.1UF/25V,Y5V

TCM

3

2

FAN Controller Circuit

H2

H1

HOLE

TH_200_132_118

1

R311KR31 1K

FAN1_V=3.30V,Vfan=5V FAN1_V=2.65V,Vfan=4V FAN1_V=1.98V,Vfan=3V

+V5S

12

Q28

Q28 BCP69-16

BCP69-16

SOT223

3 2

R341KR34 1K

1

12

C13

0.1UF/25V,Y5V

1122334455667

4

VCC_358

C12

0.1UF/25V,Y5V

1 2

1

R35

R35 100K

100K

4.7UF/10V,Y5V

FAN

ns

TH_230_132_118_6

7

R26

R26 10

10

R0603

U7A

LM358

84

so8_50_150

3

+

2

-

C17

C0805

Vfan

12

0.1UF/25V,Y5V

R37

5.11K,1%

R36

R36 10K,1%

10K,1%

R38

200K R0402

C15

0.1uF/25V,Y5V

C0402

1

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V5S {23,25,29,32,33,34,35,36,37,43,51,52,55,56} +V3.3AL {6,23,24,26,27,29,32,33,36,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V1.1S_VTT {8,10,11,27,28,29,50,51,55} +V1.5S {39,40,41,56}

+V3.3S

FAN_TACH_ON

C14

C14 10uF/6.3V,X5R

10uF/6.3V,X5R

+V3.3AL

CPUFAN1

1 2 3

CONN3_V

CNS3_V

55

R13

R12

10K

ns

FAN_BACK {43}

Q5

1

MMBT3904-F

SOT23

2 3

ns

4

1

4

2

5

3

5

65

FAN_FB

8060

R200R20

0

90 10050 9570 75

85

+V5S

R22

R22 10K

10K

ns

R21 1KnsR21 1K

D22

1N4148WS

SOD323

Shut-Down

Throttling/ Un-throttling

FAN1_V {43}

Middle-4V

ns

High-5V

Low-3V

C11

C11 1000pF/50V,X7R

1000pF/50V,X7R

ns

C16

1 2

+V3.3S

R39

4.7K

R0402

+V1.1S_VTT

R356

R356 1K,1%

1K,1%

R0402

2 3

MMBT3904-F

SOT23

SHDN#

5

Q25

R0402

1

R355 10KR355 10K

R357

R357 100K

100K

VIN

Throttling on

Throttling Off

VDC

B B

GPU_OVT#{21}

THERMTRIP#{8,27}

ALT_ON{43}

Use for temperature alarm driver.

A A

CPU

THRMTRIP#

AND

Thermal sensor

THERM_ALERT#

C285

C285 1000pF/50V,X7R

1000pF/50V,X7R

Shut Down

0

+V1.1S_VTT

3456

1

R369

R369 100K

100K

90

85

R361

R361 10K

10K

1

3

2

95

2

Q26

Q26 MMDT3904

MMDT3904

SC70_6

Q27

2N7002E-T1

100

SHDN_LOCK#

CPU Temperature

(Degree)

SHDN_LOCK# {53}

PCB1

PCB1 R20 MB

R20 MB

PCB

4

Del OVP CIRCUIT

VerA:Delete GMCH_TEMP signal and components 071026

PCBA1

PCBA1 R20 PCBA

R20 PCBA

PCBA

U7B

VCC_358

LM358

84

so8_50_150

5

+

6

-

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

C

7

3

2

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent MDC&BT/FAN/OTP

MDC&BT/FAN/OTP

C46

1

A

38 59Tuesday, January 05, 2010

A

of

5

+DATA4

D D

D26

ESDPAD_R0603

EGA1-0603-V05

ns

-DATA4

12

D25

ESDPAD_R0603

EGA1-0603-V05

ns

Keep USB2.0 Signal stub short

R550 0 R0402R550 0 R0402 R551 0 R0402R551 0 R0402

CHK8

90ohm@100M0.33A

l4_0805 ns

MINICARD_USB_PN1{26}

MINICARD_USB_PP1{26}

C C

CLK_PCIE_MINICARD#{23}

CLK_PCIE_MINICARD{23}

PCIE_TXN4_WLAN{23} PCIE_TXP4_WLAN{23}

PCIE_RXN4_WLAN{23}

PCIE_RXP4_WLAN{23}

+V3.3AL

+V3.3S

R586 0 R0603R586 0 R0603 R587 0

R587 0

ns

R0603

43 12

T60

ICTPns

T61

ICTPns

R588 0

R0603

4

-DATA4 +DATA4

+V3.3S +V3.3AL +V3.3S

R567

R567 0

0

R0603

ns

+V3.3S_PCIE +V3.3AL_PCIE

MPCIE2

MINIPCIE_half_r6

36

USB_D-

38

USB_D+

11

REFCLK-

13

REFCLK+

31

PETN0

33

PETP0

23

PERN0

25

PERP0

17

RESERVED0

19

RESERVED1

37

RESERVED_PCIE0

39

RESERVED_PCIE1

41

RESERVED_PCIE2

43

RESERVED_PCIE3

45

RESERVED_PCIE4

47

RESERVED_PCIE5

49

RESERVED_PCIE6

51

RESERVED_PCIE7

2

R561

R561 0

0

R0603

52

+3.3V0

R557

R557 0

0

R0603

+3.3V1

3

R556

+V1.5S

0

R0603

ns

24

48

28

6

+1.5V0

+1.5V1

+3.3VAUX

PCIE mini Card

+1.5V2

LED_WPAN#

LED_WLAN#

LED_WWAN#

PERST#

WAKE#

CLKREQ#

SMB_DATA

SMB_CLK

CHANNEL_CLK

CHANNEL_DATA

RESERVED_DISABLE

RESERVED_SIM0 RESERVED_SIM1 RESERVED_SIM2 RESERVED_SIM3 RESERVED_SIM4

ICTP

ns

46 44 42

ICTP

ns

22

minicard_Wake#

1

minicard_CLKREQ#_R

7

32 30

5 3

20

16 14 12 10 8

2

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V3.3AL {6,23,24,26,27,29,32,33,36,38,40,41,42,43,44,45,46,47,48,49,50,52,53,56,57} +V1.5S {40,41,56}

T57

T57 T54

T54

ns

ns ns

ns

T62

ICTP

T63

ICTP

T56

R565 0 nsR0402R565 0 nsR0402 R564 0 nsR0402R564 0 nsR0402 R563 0 nsR0402R563 0 nsR0402

T55

ICTP

R547 0 R0402

ns

R592 0 nsR0402R592 0 nsR0402 R584 0 nsR0402R584 0 nsR0402

R555 0 nsR0402R555 0 nsR0402 R554 0 nsR0402R554 0 nsR0402

R577 0 R0402R577 0 R0402

R562 0 R0402R562 0 R0402

Wireless_LED# {45}

CL_RST1# {23}

BUF_PLT_RST# {8,17,26,38,40,41,43,44} PCIE_WAKE# {24,40,41,43,44} minicard_CLKREQ# {23}

CL_DATA1 {23} CL_CLK1 {23}

+V3.3AL

R0402

10K

10K R578

R578

PWR_SW_VCC2 {36,43,48} EC_DEBG_UTXD {43} EC_DEBG_URXD {43}

minicard_Wake# minicard_CLKREQ#_R

HW_RATIO_OFF# {43}

1

+V3.3AL

R591

R591 10K

10K

R0402

ns

+V3.3S

ns

R585

R585 10K

10K

R0402

B B

GND0

GND1

GND2

GND5

GND4

GND3

9

15

21

35

29

27

+V1.5S

C203

C207

C207 10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

A A

5

C203

0.1UF/25V,Y5V

C0402

C206

0.1UF/25V,Y5V

C0402

C205

0.1UF/25V,Y5V

C0402

4

C204

0.1UF/25V,Y5V

C0402

GND11

GND10

GND9

GND8

GND7

GND6

GND1253GND1354GND1456GND1557GND1658GND1759GND1860GND1961GND20

PCIE MINI CARD

4

34

26

18

PCIE MINI CARD

50

40

ns R284,R295,R337,R341, Install R283 For chang PCIE SPEC to 1.1 Swain 081104

55

3

2

+V3.3S_PCIE

C390

C390 10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

C393

0.1UF/25V,Y5V

C0402

Page Name

Page Name Size

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

+V3.3AL_PCIE

C389

C389 10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

TOPSTAR TECHNOLOGY

bent

bent PCIE MINI SLOT 1

PCIE MINI SLOT 1

PCIE MINI SLOT 1 C46

C46

1

C392

0.1UF/25V,Y5V

C0402

A

39 59Friday, November 27, 2009

A

of

5

+DATA8

-DATA8

1

D29

D28

EGA10603V05A1-B

ESDPAD_R0603

MINICARD_USB_PN2{26} MINICARD_USB_PP2{26}

ESDPAD_R0603

CLK_PCIE_3G#{23}

CLK_PCIE_3G{23}

PCIE_TXN2_3G{23} PCIE_TXP2_3G{23}

PCIE_RXN2_3G{23}

PCIE_RXP2_3G{23}

+V3.3AL +V3.3S

PCI_CLK_DEBUG{26}

D D

C C

D28 EGA10603V05A1-B

EGA10603V05A1-B

ESDPAD_R0603

ns

2

Keep USB2.0 Signal stub short

R621 0 3GR621 0 3G R623 0 3GR623 0 3G

CHK9

90ohm@100M0.33A

l4_0805

R271 0 nsR0402R271 0 nsR0402

+VDC

注意后续不上

PICE_39

R280 0 DebugR0402R280 0 DebugR0402 R300 0 nsR0402R300 0 nsR0402

R296 0 R0402R296 0 R0402 R316 0 nsR0402R316 0 nsR0402

R321 0 R0402R321 0 R0402 R324 0 DebugR0402R324 0 DebugR0402 R326 0 DebugR0402R326 0 DebugR0402 R332 0 DebugR0402R332 0 DebugR0402 R336 0 DebugR0402R336 0 DebugR0402

BUF_PLT_RST#{8,17,26,38,39,41,43,44}

LPC_FRAME#{22,38,43}

LPC_AD0{22,38,43} LPC_AD1{22,38,43} LPC_AD2{22,38,43} LPC_AD3{22,38,43}

R304 0 R0603R304 0 R0603 R313 0 R0603 nsR313 0 R0603 ns

43 12

ns

DEBUG 3G

PICE_39

卡需要下拉

-DATA8 +DATA8

3.3PCIE2

MPCIE1

MINIPCIE_R6

3G

36

USB_D-

38

USB_D+

11

REFCLK-

13

REFCLK+

31

PETN0

33

PETP0

23

PERN0

25

PERP0

17

RESERVED0

19

RESERVED1

37

RESERVED_PCIE0

39

RESERVED_PCIE1

41

RESERVED_PCIE2

43

RESERVED_PCIE3

45

RESERVED_PCIE4

47

RESERVED_PCIE5

49

RESERVED_PCIE6

51

RESERVED_PCIE7

R0603

+V3.3AL+V3.3S

+V3.3AL

R627

R627 0

0

ns

R285

R629

0

R0603

3G

3.3ALPCIE2

24

52

2

+3.3V1

+3.3V0

+3.3VAUX

PCIE mini Card

GND0

GND1

GND2

GND5

GND4

GND9

GND8

GND3

GND7

GND6

9

4

15

21

35

29

34

26

27

18

+V1.5S

48

28

6

+1.5V0

+1.5V1

+1.5V2

LED_WPAN# LED_WLAN#

LED_WWAN#

CHANNEL_CLK

CHANNEL_DATA

RESERVED_DISABLE

RESERVED_SIM0 RESERVED_SIM1 RESERVED_SIM2 RESERVED_SIM3 RESERVED_SIM4

GND11

GND10

GND1253GND1354GND1456GND1557GND1658GND1759GND1860GND1961GND20

PCIE MINI CARD

50

40

4

PERST#

WAKE#

CLKREQ#

SMB_DATA

SMB_CLK

3

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,41,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5S {39,41,56} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,41,42,43,44,45,46,47,48,49,50,52,53,56,57}

D17

ESDPAD_R0603

EGA1-0603-V05

ns

12

D18nsD18

ns

C310

0.1UF/25V,Y5V

12

C0402

ns

+VDC {32,46,48,49,50,51,52,55,56,57}

SIM_PWR SIM_DATA

R385 8.2K

R0402

C309

0.1UF/25V,Y5V

C0402

C0402 ns

ns

C311

C0402

R386

R386 56

56

R0402

ns

SIM_PWR SIM_REST

SIM_VPP SIM_DATA

12

D19nsD19

ns

R0402

C308

1uF/10V,X7R

C0603

ns

12

SIM_CLK

D20nsD20

47pF/50V,NPO

SIMCARD1

C1

VCC1

C2

RESET

C3

CLK

C4

GND

C5

VPP

C6

IO

C7

GND1

C8

GND2

SIMCARD

3G

Add SIM card Swain 081111

C312

C312 100pF/50V,NPO

100pF/50V,NPO

C0402

C0402 ns

ns

HOLE0 HOLE1

12

D21nsD21

ns

G1 G2

PCIE_NUT1

PCIE_NUT1 Hole+Dowel

Hole+Dowel

3G

+V3.3AL

R594

R594 10K

10K

ns

WAKE#

MiniPCIE_REQ1#_R

R619 0 nsR619 0 ns R617 0 nsR617 0 ns

R614 0 3GR614 0 3G

R605 0R605 0

R628 0 nsR628 0 ns R626 0 nsR626 0 ns R625 0 nsR625 0 ns

R231 0 nsR231 0 ns

R246 0 nsR246 0 ns

SIM_VPP

3G_LED# {43,45}

BUF_PLT_RST# {8,17,26,38,39,41,43,44} PCIE_WAKE# {24,39,41,43,44}

MiniPCIE_REQ# {23}

SMB_DATA_S {6,15,16,23,41} SMB_CLK_S {6,15,16,23,41}

HW_RATIO_OFF_3G# {43}

R612

R613

10K

ns

3G

+V3.3S

+V3.3AL

46 44 42

22 1 7

32 30

5 3

20

16

SIM_REST

14

SIM_CLK

12

SIM_DATA

10

SIM_PWR

8

55

2

1

ns SIM card periphery current

许沐锌

081222

+V1.5S

C221

0.1UF/25V,Y5V

C254

C0402

1uF/10V,X7R

3G

C0603

3G

B B

+V3.3AL

A A

5

R377

R377 10K

10K

R0402

3G

C257

C410

0.1UF/25V,Y5V

C0402

3G

VerB:the SW1 controll the 3G_LED

3G_OFF{43}

3GVDD_ON

5

445

1

3

2

667

3G

7

R380 0 3GR380 0 3G

3G_SW1

1

LSS-12M-V-B

SW_W_S7A

2

2 3

3

3G

3.3PCIE2

C416

C416 10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

C394

0.1UF/25V,Y5V

C0402

3G

4

3.3ALPCIE2

C238

C238 1uF/10V,X7R

1uF/10V,X7R

C0603

3G

C239

0.1UF/25V,Y5V

C0402

3G

Add Option for 3G card Swain 080820

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

A2

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

the expressed written consent of TOPSTAR

bent USB Port

USB Port

C46

1

A

40 59Wednesday, January 20, 2010

of

5

+V3.3S +V1.5S

U17

U17 P2231

C272

+V3.3AL

C272

0.1uF/10V,X5R

C256

0.1uF/10V,X5R

Newcard_RST#

PM_SLP_S3#

PM_SLP_S4#

RCLKEN

C263

0.1uF/10V,X5R

D D

P2231

QFNS20_0D5_0D85G

12

1.5Vin1

14

1.5Vin2

3.3Vin123.3Vauxout

4

3.3Vin2

17

3.3Vauxin

1

STBY#

20

SHDN#

6

SYSRST#

16

NC

18

RCLKEN

19

OC#

3.3Vout1

3.3Vout2

1.5Vout1

1.5Vout2 PERST#

CPPE#

CPUSB#

GND2 GND3 GND1

3 5

15 11

13 8 10 9

G1 G2 7

add power sw

4

EXP_AUX_3.3V

EXP_RST# EXP_CPPE# CP_USB#

EXP_3.3V

EXP_1.5V

3

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,42,43,44,45,49,50,51,52,53,55,56,57,58} +V1.5S {39,40,56} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,42,43,44,45,46,47,48,49,50,52,53,56,57}

EP_MYLAR1

PVC

ASSY

BUF_PLT_RST#{8,17,26,38,39,40,43,44}

R349 0R349 0

Change mylar type follow ME advised By Johan 071228

EP_CON1

EP_CON1 Shield

Shield

ASSY

621000000002

Newcard_RST#

EP_B1

EP_B2

2

1

PM_SLP_S3#{24,43,53} PM_SLP_S4#{24,43,56}

C C

+V3.3AL

R322

R322 100K

100K

PM_SLP_S4#

ns

PCIE_TXP3_EXP{23} PCIE_TXN3_EXP{23} PCIE_RXP3_EXP{23}

B B

EXPCARD_USB_PP0{26}

EXPCARD_USB_PN0{26}

A A

PCIE_RXN3_EXP{23}

CLK_PCIE_EXPCARD{23}

CLK_PCIE_EXPCARD#{23}

EXP_RST#

PCIE_WAKE#{24,39,40,43,44}

SMB_DATA_S{6,15,16,23,40}

SMB_CLK_S{6,15,16,23,40}

R631 0 R0402R631 0 R0402

L4_0805

CHK10

R633 0

5

12 43

ns

90ohm@100MHz,0.5A

R0402

EGA1-0603-V05

ESDPAD_R0603

12

D31

ns

EXP_CPPE#

CP_USB#

EGA1-0603-V05

ESDPAD_R0603

25 24 22 21 19 18 17 13 11

8 7 4 3 2

12

D30

ns

PM_SLP_S3# PM_SLP_S4#

J3

CLKREQ#

PETp0 PETn0 PERp0 PERn0 REFCLK+ REFCLK-

RESV1

RESV2 +3.3VS_2 +3.3VS_1

CPPE# PERST#

+3.3VAUX

WAKE# SMB_DATA SMB_CLK CPUSB# USB_D+

+1.5V_1 +1.5V_2

USB_D-

G1G1G2

PECA00-000LBS4Z4N0

NEW_CARD3

G2

GND0

GND1

GND2 GND3 GND4

GND5

ASSY

Screw 2*5mm

+V3.3AL

16

6 5

1

2

D11

D11 BAT54S

BAT54S

SOT23

ns

3

EXP_3.3V

R310 0

Q22

2N7002E-T1-E3

SOT23

2

ns

1

RCLKEN

ns

3

ASSY

Screw 2*5mm

EXPCARD_CLKREQ# {23}

15 14

26

12

23

10 9

20 1 27

28

4

C248

0.1uF/10V,X5R

C267

0.1uF/10V,X5R

EXP_1.5V

C273

0.1uF/10V,X5R

Chang the CAP type from X7R to X5R

EXP_AUX_3.3V

10uF/6.3V,X5R

ns

C277

C252

10uF/6.3V,X5R

C260

10uF/6.3V,X5R

+V3.3AL

R350

R351

R351 100K

100K

CP_USB# EXP_CPPE# EXPCARD_CLKREQ#

3

100K

R320

R320 10K

10K

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

2

the expressed written consent of TOPSTAR

bent

EXPRESS CARD

C46

1

A

41 59Friday, November 27, 2009

A

of

5

4

3

2

1

All of by-pass capacitors must be closed to IC

RST

24 23 22 21 20

ClkSel

19

SM_D3

18 17 16 15 14

DGND

13

ClkSel

R293 0

D3.3V

RST

R329 0

R0402

R330

R330 30K

30K

R0402

C269

4.7uF/10V,X5R

C0805

C253

2.2uF/10V,X7R

C0805

PWR_SW2

D3.3V

C266

0.1UF/25V,Y5V

C0402

R0402

CLK_CR_48M {23}

Clk12M-out

+V3.3AL

R331 0 R0402R331 0 R0402 C265

C265

4.7uF/10V,X5R

C0805

Int-12MHz

+V3.3AL

C264

0.1UF/25V,Y5V

C0402

D3.3V

SM_WP

R309 0 nsR0402R309 0 nsR0402 C243

C243

2.2uF/10V,X7R

C0805

PWR_SW2

R283 0 R0402R283 0 R0402

VDD18REG18V

C268

C268 1uF/10V,X7R

1uF/10V,X7R

C0603

SD_CLK

+V3.3S

C251

0.1UF/25V,Y5V

C0402

C237

0.01uF/25V,X7R

C0402

3IN1 CONN

D3.3V

REG18V

DGND

29

30

TC

SM/SD/MS D5

SM_RNB

SM_D1

SM_D0

DGND

27

26

VSS

GPIO128GPIO4

SM_D2

+V3.3AL

25

REG33Vout

12

VDD18

REG5Vin

GPIO0/LED

SM/SD/MS D4

RST

GPIO3

ClkSel

SM/SD/MS D3

SM_CD

SM_ALE

PWR_SW

VDD33

VSS

use 48Mhz crystal

use 12Mhz crystal

XTALI

D D

Clk12M-out SM_CE SM_WP DGND

EE_SDA EE_SCL

USB_CR_PP8{26}

C C

USB_CR_PN8{26}

B B

D3.3V

DGND

EEprom Setting

U18

1

A0

VCC

2

A1

WP

3

A2

SCL

VSS4SDA

S-24CS02AFJ-TB-G

SO8_50_150

ns

S0=P12=EEP_SDA

C240

0.1UF/25V,Y5V

C0402

U16

37

GPIO7

38

Clk12M_out

39

SM_CE/SD_WP

40

SM_WP/SD_CLK/MS_CLK

41

VSS

42

SM_WR

43

EE_SDA

44

EE_CLK

45

AVDD33

46

DP

47

DM

48

AVSS

IT1337E-48

QFPS48_0D5_1D6

D3.3V

8 7

EE_SCL

6

EE_SDA

5

REG18V

34

32

33

31

36

35

GPIO6

GPIO5

REG33Vin

REG18Vout

SM/SD/MS D7

SM/SD/MS D6

IT1337E-48

SD/MS/xD

XTALO1XTALI2xD_CD3Clk48M4SM_WP_SW/SD_CMD/MS_BS

SM_RD/MS_INS6SM_RNB/SD_CD7SM/SD/MS D08SM/SD/MS D19SM_CLE10SM/SD/MS D211VDD18

5

SM_RD

XTALI

SM_WPSW

CLK_CR_48M

C235

0.1UF/25V,Y5V

C0402

ns

R327

R328

0

R0402

ns

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,43,44,45,49,50,51,52,5 +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,43,44,45,46,47,48,49,50,52,53,56,57}

IT1337E-48 PIN MUX

PINs

SM/xD

SM_WPSW

05 06 MS_INS

SM_RD SM_RNB

07

SM_D0

09

SM_D1

11

SM_D2 SM_D3

18

SM_D4

22 29

SM_D5 3208SM_D6 34

SM_D7 39

SM_CE 40

SM_WP

SM_D2 SM_D3 SM_WPSW

SD_CLK SM_D0

SM_D1 SM_RNB SM_CE

SD_CLK

SM_D3

SM_RD

SM_D2

SM_D0

SM_D1

SM_WPSW

10 11

14 15

16 17 18 19 20

2 3 4

7 9 1

SD/MMC

SD_CMD

SD_CD SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 SD_WP SD_CLK

J2A

DAT2_SD DAT3_SD CMD_SD

CLK_SD DAT0_SD

DAT1_SD CD_SD# WP_SD#

3IN1

3IN1 J2B

J2B

CLK_MS DAT3_MS

INS_MS DTA2_MS DTA0_MS DTA1_MS BS_MS

3IN1

VDD_SD

SD+MMC

VSS_SD2 VSS_SD1

VCC_MS

MS

VSS_MS1 VSS_MS2

GND1 GND2

MS

MS_BS

MS_D0 MS_D1 MS_D2 MS_D3 MS_D4 MS_D5 MS_D6 MS_D7

MS_CLK

6

8 5

13

12 21 22 23

PWR_SW2

C250

0.1uF/10V,X7R

PWR_SW2

C262

0.1uF/10V,X7R

C255

C255 1uF/10V,X7R

1uF/10V,X7R

C0603

C258

C258 1uF/10V,X7R

1uF/10V,X7R

C0603

S1=P13=EEP_SCK

TOPSTAR TECHNOLOGY

A A

Page Name

Size

Project Name Rev

Custom

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

TOPSTAR TECHNOLOGY

bent

Cardreader(ITE1337)

C46

1

A

42 59Friday, November 27, 2009

A

of

R342

Q19

8.2K

2N7002E-T1

1

2

D9 1N4148WS

1

SOD323

+V5S

Q20

Q20 2N7002E-T1

2N7002E-T1

1

R318

R318 10K

10K

2

D10 1N4148WS

1

SOD323

+V3.3AL

不用的

EC_IMVP_ON EC_IR_IN

BT_PWRON

PM_SUS_STAT#{24}

AMP_SHDW

PM_SLP_S4#

PM_SLP_S3#

C242

C242 100pF/50V,NPO

100pF/50V,NPO

上拉到

3

ns

3

+V3.3AL

ns

5

A20GATE

EC Output Signal!

R608 0

R339

RN1 4.7KnsRN1 4.7K

1 2 3 4 5 6 7 8

RN2 4.7KnsRN2 4.7K

1 2 3 4 5 6 7 8

+V3.3AL.

R2791KR279

5

RCIN#

R0402

4.7KR0402

SCANIN0 SCANIN1 SCANIN2 SCANIN3

ns

SCANIN4 SCANIN5 SCANIN6 SCANIN7

ns

Double confirmed By Johan 0711081231

1K

+V3.3AL

PWR_SW_VCC2{36,39,48}

R302 0 R0603R302 0 R0603

EC Input Signal!

EC_BUF_PLT_RST#

CLKREQ

EC_PMSUSStat#

R2720 R2720

add 0 OHM

EC_RUNTIME_SCI#{27}

CLK_591PCI{26}

INT_SERIRQ{22,38}

LPC_FRAME#{22,38,40}

LPC_AD0{22,38,40} LPC_AD1{22,38,40} LPC_AD2{22,38,40} LPC_AD3{22,38,40}

V1.8G_1.5G_ON{57}

AC_IN_PCH{24}

PM_SLP_S3#{24,41,53} PM_SLP_S4#{24,41,56}

IMVP_ON{55}

ALT_ON{38}

R295

R295 10K

10K

R0402

1000pF/50V,X7R

PM_RSMRST#{24,53}

LIDR#{32,36}

V1_5_ON{49}

ALWAYS_ON{48}

V1_1S_VTT_ON{50}

V0_75S_ON{49}

IMVP_PWRGD{55} MAIN_PWROK{24,53}

R651 0 PMR651 0 PM

PWRSW#

C241

C0402

R286 0 nsR286 0 ns

AC_IN{21,46}

PWRSW#

R3351.5K,1% R0402R3351.5K,1% R0402

MAIN_ON{56}

R263 0R263 0

BAT_LOW#{24}

PCIE_WAKE#{24,39,40,41,44}

CPU_VTT_PWG{8}

EC_DEBG_UTXD{39}

EC_DEBG_URXD{39}

GPU_HDMI_HPD{21,33}

VGACORE_PWRGD{52}

EC_IMVP_PWRGD{24}

+V3.3AL

3

Q21

1

2N7002E-T1

R319

2

1M

R0402

+V3.3S +V5S

R0402

H_A20GATE{27}

+V3.3S

D D

H_RCIN#{27}

BUF_PLT_RST#{8,17,26,38,39,40,41,44}

KBCON1

KBCON1 ACES 85201-2602

ACES 85201-2602

CNS26_1_R_2D5

26

25

SCANOUT15

24

SCANOUT10

23

SCANOUT11

22

SCANOUT14

21

SCANOUT13

20

SCANOUT12

19

SCANOUT3

18

SCANOUT6

17

SCANOUT8

16

SCANOUT7

15

SCANOUT4

14

SCANOUT2

13

SCANIN7

12

SCANOUT1

11

SCANOUT5

10

SCANIN4

9

SCANIN5

8

SCANOUT0

7

SCANIN2

6

28

C C

6

28

SCANIN3

5

27

5

27

SCANOUT9

4

SCANIN1

3

SCANIN0

2

SCANIN6

1

+V3.3AL

R292 10K nsR292 10K ns R298 10KR298 10K

+V3.3AL

R281 10K nsR281 10K ns

+V3.3AL

R254

10K

ns

B B

C247

C247 100pF/50V,NPO

100pF/50V,NPO

A A

A20GATE RCIN#

EC_RESET#

EC_PCI_RST#

CLKREQ

SCANIN7 SCANIN6 SCANIN5 SCANIN4 SCANIN3 SCANIN2 SCANIN1 SCANIN0

R2840 R2840

SCANOUT15 SCANOUT14 SCANOUT13 SCANOUT12 SCANOUT11

SCANOUT10

SCANOUT9

SCANOUT8 SCANOUT7 SCANOUT6

SCANOUT5 SCANOUT4 SCANOUT3 SCANOUT2 SCANOUT1 SCANOUT0

EC_PMSUSStat#

PCIE_WAKE#_EC

R290 1KR290 1K

R294 1KR294 1K

EC_IR_IN EC_IMVP_ON

R291 0R291 0

PROCHOT#

The 0ohm RES will across the isolate island of anolog GND and digital GND

EC_PROCHOT#{8}

4

C246

0.1UF/25V,Y5V

1

GA20/GPIO00

2

KBRST#/GPIO01

20

SCI#/GPIO0E

37

ECRST#

12

PCICLK

3

SERIRQ

4

LFRAME#

10

LAD0

8

LAD1

7

LAD2

5

LAD3

13

PCIRST#/GPIO05

38

CLKRUN#/GPIO1D

62

KSI7/GPIO37

61

KSI6/GPIO36

60

KSI5/GPIO35

59

KSI4/GPIO34

58

KSI3/GPIO33

57

KSI2/GPIO32

56

KSI1/GPIO31

55

KSI0/GPIO30/E51_TXD(ISP)

82

KSO17/GPIO49

81

KSO16/GPIO48

54

KSO15/GPIO2F/E51_RXD(ISP)

53

KSO14/GPIO2E

52

KSO13/GPIO2D

51

KSO12/GPIO2C

50

KSO11/GPIO2B

49

KSO10/GPIO2A

48

KSO9/GPIO29

47

KSO8/GPIO28

46

KSO7/GPIO27

45

KSO6/GPIO26

44

KSO5/GPIO25

43

KSO4/GPIO24

42

KSO3/GPIO23/TP_ISP

41

KSO2/GPIO22/TP_ANA_TEST

40

KSO1/GPIO21/TP_PLL

39

KSO0/GPIO20/TP_TEST

6

GPIO04

14

GPIO07/i_clk_8051

15

GPIO08/i_clk_peri

16

GPIO0A/CIR_RX2

17

GPIO0B/ESB_CLK

18

GPIO0C/ESB_DAT_O/ESB_DAT_I

19

GPIO0D

32

GPIO18

36

GPIO1A/NUMLED#

73

GPIO40/CIR_RX

74

GPIO41/CIR_RLC_TX

89

GPIO50

127

GPIO59/TEST_CLKSPICLKI

68

GPO3C

70

GPO3D

71

GPO3E

72

GPO3F

76

GPI43

75

GPI42

90

E51CS#/GPIO52

30

E51TXD/GPIO16

31

E51RXD/GPIO17/E51CLK

92

E51TMR0/GPIO54/WDT_LED#

93

E51INT0/GPIO55/SCROLED#

91

E51TMR1/GPIO53/CAPSLED#

95

E51INT1/GPIO56

+V5S

2

R268 0 nsR268 0 ns

4

FB11

120ohm/100MHz,500mA FB0603

1 2

C245

0.1UF/25V,Y5V

V18R

124

67

V18R

AVCC

MSIC

LPC

KB

AGND

69

R2990R0603R2990R0603

+V3.3AL

R604 4.7K R0402

ns

Q17

1

2N7002E-T1

EC Input Signal!

PROCHOT#

3

111

VCC

VCC96VCC

KB3926

GPXIOA

GPIO

8051

GND

GND35GND24GND

GND

94

113

33

22

9

125

VCC

ADC PWM

AD2/GPI3A AD3/GPI3B

PWM0/GPIO0F PWM1/GPIO10 PWM2/GPIO11 PWM3/GPIO19

FAN

FANFB0/GPIO14

FANFB1/GPIO15 FANPWM0/GPIO12 FANPWM1/GPIO13

PSCLK1/GPIO4A/P80CLK PSDAT1/GPIO4B/P80DAT

PSCLK2/GPIO4C

PS2

PSDAT2/GPIO4D PSCLK3/GPIO4E PSDAT3/GPIO4F

SMBUS

SDA1/GPIO47 SCL1//GPIO46 SDA0/GPIO45

SCL0/GPIO44

GPXIOA00/SDICS# GPXIOA01/SDICLK

GPXIOA02/SDIMOSI

GPXIOD0/SDIMISO

GPXIOD

SPI

SPICLK/GPIO58

change to DG By Johan 071224

CLK

XCLK32K/GPIO57

11

EC_BUF_PLT_RST#

1 2

U14

AD0/GPI38 AD1/GPI39

GPXIOA03 GPXIOA04 GPXIOA05 GPXIOA06 GPXIOA07 GPXIOA08 GPXIOA09 GPXIOA10 GPXIOA11

GPXIOD1 GPXIOD2 GPXIOD3 GPXIOD4 GPXIOD5 GPXIOD6 GPXIOD7

MISO MOSI

SPICS#

XCLKI

XCLKO

KB3926

+V3.3AL

R630

R630 0

0

R0805

63 64 65 66

21 23 25 34

28 29 26 27

83 84 85 86 87 88

80 79 78 77

97 98 99 100 101 102 103 104 105 106 107 108

109 110 112 114 115 116 117

EC_BUF_PLT_RST#

118

119 120 126 128

121 122 123

+V3.3S

R609 4.7K R0402

R611 4.7K R0402

ns

R6070

R0402

R606

R606 10K

10K

R0402

ns

3

+V3.3AL

SYS_I_Sense

HDD_ZOUT HDD_YOUT HDD_XOUT

R303 1K

PM_STATE

SML1DATA SML1CLK

GPXIOA00

R650 0R650 0

HW_OFF_BKLT#

PCB_Mark0 PCB_Mark1 PCB_Mark2

EC_32XCLK1 EC_32XCLK0

ns

EC_PCI_RST#

3

BTL_BEEP {37} SET_I {54}

V3G_1.05G_ON {57}

FAN1_V {38}

R0402

TPCLK {36} TPDAT {36}

HW_RATIO_OFF# {39}

VGPU_ON {52}

SML1DATA {23} SML1CLK {23} SM_BAT_SDA2 {47} SM_BAT_SCL2 {47}

CHG_LED# {45} BTL_LED# {45} PM_PWRBTN# {24} AMP_SHDW {37}

CHG_ON {54} 3G_LED# {40,45} HW_RATIO_OFF_3G# {40}

EC_SPI_MISO

EC_SPI_MOSI SPI_SCK SPI_CS#

VTT_PWG {50,53}

V18REC_V3.3ALEC_V3.3AL

C400

0.1UF/25V,Y5V

C0402

EC_FAN_BACK

Camera_ON {32}

BT_PWRON {38}

HW_OFF_BKLT# {32} AC_OFF {46} EC_GPU_RST# {17}

3G_OFF {40} ALW_PWROK {48}

C270

4.7UF/10V,Y5V

C0805

R340

100

R0402

R345

R345 10K

10K

R0402

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,44,45,49,50,51,52,53,55,56,57,58} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,44,45,46,47,48,49,50,52,53,56,57} +V5S {23,25,29,32,33,34,35,36,37,38,51,52,55,56}

C415

10UF/6.3V,X5R

C0805

Should have a 0.1uF capacitor close to every GND-VCC pair + one

Vin>=1.5V turn on the cup FAN.

swap for DG By Johan 071224

R308

R308 100K

100K

EXTSMI# {27}

ALW_ACK {24}

GPXIOA00

BT_ON {32}

SPI_CS# EC_SPI_MISO

4.7K

R602

R0402R602

R0402

EC_V3.3AL

Q24

1

MMBT3904-F

2 3

R269 121K,1%R269 121K,1%

R258

10M

R0402

larger cap on the supply.

SYS_I_Sense

D12

1

1N4148WS

SOD323

WP#1 VSS

12

C402

C402 1uF/10V,X7R

1uF/10V,X7R

C0603

SYS_I_Sense {54}

POWERLED# {45} EC_BKLT_PWM {32}

R2740ns R2740ns

R273

0

ns

EC_V3.3AL

BATT_IN# {47}

BKLT_ON {32}

EC_32XCLK0

EC_32XCLK1

2

EC_V3.3AL

CHG_ON

R253 10KR253 10K

ALW_PWROK need move to other place.pin110&111 follow the sequence of R18EC

C271

3300pF/50V,X7R

C0402

FAN_BACK {38}

10KR255 10KR255

U28

1

8

CS#

VCC

2

7

Q

HOLD#

3

6

W#

CLK

5

VSS4D

W25X80A

SOIC8_50_208

VCC_SPI WP#1 HOLD#1

R325

R325 10K

10K

R0402

EC_RESET#

C261

0.01uF/16V,Y5V

C0402

C225

C0402

Y2

15pF/50V,NPO

32.768KHz

xd3_2X6

3

ASSY

C224

C0402

15pF/50V,NPO

2

C403

0.1UF/25V,Y5V

+V3.3AL

VCC_SPI

HOLD#1 SPI_SCK EC_SPI_MOSI

8 3 7

R338

R338 0

0

R0402

ns

SPI_CS# EC_SPI_MOSI EC_SPI_MISO SPI_SCK

SM_BAT_SDA2 SM_BAT_SCL2 LIDR#

BAT_LOW#

PCIE_WAKE#_EC PM_STATE

ALT_ON

R234

R235

10K

ns

R250

R251

10K

R601 4.7K

R0402

U27

VDD WP# HOLD#

W25X40 ns

SO8_50_150

R603 0

R0603

C408

C399

0.1UF/25V,Y5V

HDD_ZOUT HDD_YOUT HDD_XOUT PM_STATE

change to DG By Johan 071224

R236

R236 10K

10K

PCB_Mark0 PCB_Mark1 PCB_Mark2

R252

R252 10K

10K

ns

change vera to verb hads

BIU configuration should match flash speed used

EC_V3.3AL

5

SI

2

SO

1

CE#

6

SCK

VSS

4

VSS

C408

C398

0.1UF/25V,Y5V

R334 10KR334 10K R315 10KR315 10K R312 10KR312 10K R664 10KGMR664 10K

GM

R593 10K

R593 10K R248 10K

R248 10K R249 10K

R249 10K

ns

R583 10K

ns

ns ns

ns

R287 5.6KR287 5.6K R289 5.6KR289 5.6K R288 10KR288 10K

R257 10KR257 10K

R282 10KR282 10K R665 10K

R665 10K

PM

R270 10K nsR270 10K ns

Fuction P.M2 P.M1 P.M0 VerA

VerB

Verc

EC_SPI_MOSI EC_SPI_MISO

SPI_CS# SPI_SCK

VerB Colay tow roms

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

1

C412

0.1UF/25V,Y5V

+V3.3AL

0 0 0

0 0 1

0 1 0

LABEL1

Topstar Soft

BIOS Ver: X.XX

EC Ver: X.XX

XXXX年XX月XX

日

XXXX年XX月XX

日

EC/BIOS Label

ASSY

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

Custom

Date: Sheet

Date: Sheet of

bent KBC(PC87541L)

KBC(PC87541L)

C46

1

43 59Friday, November 27, 2009

A

of

5

Layout Note:

VDD3D3_LAN

D D

VerC:Delete Caps followed demo board by Robin 080418

CTRL18

C C

DVDD15

Place close to VDD33_LAN PINS. (PIN16,PIN37,PIN46 and PIN53)

C56

C61

C0402

0.1UF/25V,Y5V

C54

10UF/6.3V,X5R

8101E

0.1UF/25V,Y5V

C91

0.1UF/25V,Y5V

C0402

C0805

0.1UF/25V,Y5V

C85

C85 10UF/6.3V,X5R

10UF/6.3V,X5R

C0805

8101E

C80

0.1UF/25V,Y5V

C0402

C73

C0402

0.1UF/25V,Y5V

FB2 0 R0805FB2 0 R0805

C55

C0402

0.1UF/25V,Y5V

R68 0 R0805

8101E

C60

0.1UF/25V,Y5V

C0402

Layout Note: Place close to DVDD15 PINS (PIN15,PIN21,PIN43,PIN49 and PIN58)

4

100M Lan(RTL8101E/8102E)

VerD:LAN Delete Caps and change some options followed demo board and colay 8102E By K' 080522

Layout Note: Place close to AVDD33 PINS. (PIN2)

Layout Note: Place close to AVDD18 PINS. (PIN5,PIN8)

AVDD18

是

1.2V

C57

C0402

C62

C74

C0805

C0402

1uF/25V,Y5V

0.1UF/25V,Y5V

8101E

C68

0.1UF/25V,Y5V

C0402

1uF/25V,Y5V

8102E

C83

0.1UF/25V,Y5V

C0402

EVDD18

DVDD15

C71

0.1UF/25V,Y5V

C0402

Layout Note: Place close to EVDD18 PINS. (PIN22,PIN28)

8101E

C84

C0402

AVDD33

C58

C0402

FB12

0.1UF/25V,Y5V

C82

0.1UF/25V,Y5V

C0402

RTL8111B/RTL8101E时为1.8V RTL8111C

8101E

C70

C0402

3

+V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,45,46,47,48,49,50,52,53,56,57}

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,45,49,50,51,52,53,55,56,57,58}

+V3.3AL

120ohm/100MHz,500mA FB0603

3.3V

1.2V

0.1UF/10V,X7R

RSET

C67

C0402

0.1UF/25V,Y5V

8101E

LAN_TX0-

R393

49.9,1%

R0402

8101E

C0402C324

C0402

120ohm/100MHz,500mA FB0603

RTL8101E-GR

Power domain chart

RTL8101E

R443

3.3V

1.8V

1.5V

1KR442 R04021KR442 R0402

15K

C0603

1uF/10V,Y5V

0.01UF/25V,Y5V

AVDD33

AVDD18 EVDD18 DVDD15

PCIE_GLAN_CLKP{23} PCIE_GLAN_CLKN{23}

PCIE_TXP1_LAN{23} PCIE_TXN1_LAN{23} PCIE_RXP1_LAN{23} PCIE_RXN1_LAN{23}

BUF_PLT_RST#{8,17,26,38,39,40,41,43}

PCIE_WAKE#{24,39,40,41,43}

+V3.3S

RTL8102E

C324

C326

C0402C326

C0402

0.1UF/10V,X7R

R040215K

R0402

R410 2.49K,1% R0402

8102E

R395 2K,1% R0402

8101E

C69

8101E

Layout Note: place close to IC

LAN_TX0+

R394

49.9,1%

R0402

8101E

C317

C0402

8101E

VDD3D3_LAN

U23

26 27

23 24 29 30

20 19 36 54

55 56 57

64

62

46

37

53

VDD33_03

VDD33_02

VDD33_04

REFCLK_P REFCLK_N

HSIP HSIN HSOP HSON

PERSTB LANWAKEB ISOLATEB LED3

LED2 LED1 LED0

RSET

GVDD

FB3

1 2

AVDD33

16

59

VDD33_01

EGND1

EGND2

25

31

33

58

52

49

2

VDD15_09

VDD15_10

VDD15_08

VDD15_07

AVDD33_01

AVDD33_02

GND1G1GND2G2GND3G3GND4G4GND5G5GND6G6GND7G7GND8G8GND9

C97 330PF/50V,X7R

C97 330PF/50V,X7R C103 4.7uF/10V,Y5V

C103 4.7uF/10V,Y5V C319 330PF/50V,X7R

C319 330PF/50V,X7R C314 330PF/50V,X7R

C314 330PF/50V,X7R

2

VDD3D3_LAN

43

41

38

VDD15_06

VDD15_05

VDD15_04

G9

C0603

C0603 C0805

C0805 C0603

C0603 C0603

C0603

21

32

VDD15_03

NC951NC8

50

DVDD15

15

VDD15_02

VDD15_01

NC7

42

47

45

48

EEDI

EESK

EEDO

EVDD18_02 EVDD18_01

AVDD18_04 AVDD18_03 AVDD18_02 AVDD18_01

VCTRL15 VCTRL18

MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3

CKTAL2 CKTAL1

NC640NC5

NC435NC3

39

34

TP2

EECS

EEDO

44

EECS

28 22

14 11 8 5

63 1

3 4 6 7 9 10 12 13

61 60

NC2

NC1

18

17

TP1

ICTP

ns

IO_CASE_GND

R109 3.6K R0402R109 3.6K R0402

10KR108 R0402

ns

1

CS

EESK

2

SK

EEDI/AUX

3

DI

4

DO

U24

U24 AT93C46-10SU-2.7

AT93C46-10SU-2.7

SO8_50_150

FB12

DVDD15 CTRL18

LAN_TX0+

LAN_TX0-

LAN_TX1+

LAN_TX1-

LAN_XTALOUT LAN_XTALIN

Y3 25MHz

1 2

XS2_3d3

C323

C0402

27pF/50V,NPO

Layout Note: place close to transformer

0.01UF/25V,Y5V

1

VDD3D3_LAN

10K is used only when 93C56 is used.

8

VCC

7

NC1

6

NC2

5

GND

EVDD18

AVDD18

C59

C0402

0.01uF/25V,X7R

VerC:Add 0.01uF followed demo for better EMI performance by Robin 080417

R392

49.9,1%

R0402

8101E

C316

C0402

8101E

C92

C0402

0.1UF/10V,X7R

Layout note:

0.01uf caps need to be placed close to PIN5

C322

C0402

27pF/50V,NPO

LAN_TX1-

LAN_TX1+

R391

49.9,1%

R0402

8101E

RN3

B B

GND

A A

IO_GND

5

IH1

HOLE

1 TH_315_118

TH_315_118

ns

IO_CASE_GND

4

R390 0 R0402

C0402

0.01UF/25V,Y5V

C315

VDACAVDD18

8101E

13

N4

12

VDAC

LAN_TX0-

LAN_TX0+ LAN_TX1-

LAN_TX1+

C318

C0402

0.01UF/25V,Y5V

RJ45_TX0+

RJ45_TX0- RJ45_TX1+

N3

9

TD-

11

TDC

10

TD+

15

RD-

14

RDC

16

RD+

6

1

3

U9

TRAN16_50_272

1CT:1CT

5

2

IO_CASE_GND

N2 N1

TX-

CMT

TX+

RXRXC RX+

AZC099-04S

4

5 4

8 6 7 2 3 1

SOT23_6

ns

3

RJ45_TX1-

D3

TX0MCT5 TX0+ TX1MCT6 TX1+

1 2 3 4 5 6 7 8

CHK3

TX1TX1+

3

TX0-

2

TX0+

1

90ohm@100MHz

CMC8

Layout Note: Colay CHOCK AND RN

MCT5 MCT6 RJ45_TX2+ RJ45_TX2RJ45_TX3+ RJ45_TX3-

RN3 0x4

0x4

RA0603_8

L2+4L3+ L2L1+ L1-

R125

R125 75

75

R0402

IO_CASE_GND

RJ45_TX0+

L3-

L4+

L4-

R0402

R122

R122 75

75

7 8

ns

R115

R115 75

75

R0402

IO_CASE_GND

2

RJ45_TX0RJ45_TX0+

R91

R107

75

R0402

C86

C1206

1000pF/2000V

R0402

R90

R90 75

75

RJ45_TX1-

5

RJ45_TX1+

6

RJ45_TX0RJ45_TX1+ RJ45_TX2+ RJ45_TX2RJ45_TX1RJ45_TX3+ RJ45_TX3-

1 2 3 4 5 6 7 8

Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained with the

to others or used for any purpose other than that for which it was obtained with the

to others or used for any purpose other than that for which it was obtained with the expressed written consent of TOPSTAR

expressed written consent of TOPSTAR

RJ45

TX0+

TX0+ TX0-

TX0TX1+

TX1+ TX2+

TX2+ TX2-

TX2TX1-

TX1TX3+

TX3+ TX3-

TX3-

IO_CASE_GND

910

RJ1

RJ1 RJ45

RJ45

RJ45_S

TX0+

TX0+ TX0-

TX0TX1+

TX1+ TX2+

TX2+ TX2-

TX2TX1-

TX1TX3+

TX3+ TX3-

TX3-

Topstardigital

bent

PWR/Lan/USB/RJ45 Board

C46

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44 59Friday, November 27, 2009

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5

4

+V3.3S

3

2

1

WIRELS1 BL-HGB35A-TRB

WIRELESS_LED#{39}

D D

C C

3G_LED#{40,43}

SATA_LED#{22}

CHG_LED#{43}

BTL_LED#{43}

POWERLED#{43}

220R641 R0603220R641 R0603 220R642 R0603220R642 R0603

220R645 R0603220R645 R0603

12

LED2_0805

Blue color

3G_LED1 BL-HGB35A-TRB

12

LED2_0805

HDD1 BL-HGB35A-TRB

12

LED2_0805

C434

1000pF/50V,X7R

C0402

S46/LED

的颜色换成了蓝色

CHARGE_LED

BAT_STATE_LED

4 3

HA1GE33B AMB/GREEN

LED4_1210A

PWR_LED

S46/加上LED

灯，只有4个

1000pF/50V,X7R

C0402

CHARGE1

G

Blue Color

R

LED

3G+

IDE+

1000pF/50V,X7R

C433

C0402

12

Red color

POWER1

12

BL-HGB35A-TRB

LED2_0805

，包括一个双色的

C432

220R648

R0402

220R649

R04023G

150R647

R0402

+V3.3AL

LED，Blue

C431

0.1UF/10V,X7R

C0402

SATA_LED#

WIRELESS_LED#

CHARGE_LED

BAT_STATE_LED

PWR_LED

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,49,50,51,52,53,55,56,57,58} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,46,47,48,49,50,52,53,56,57}

ESD4 EGA1-0603-V05

1 2

ESDPAD_R0603ns

1 2

ESDPAD_R0603ns

1 2

ESDPAD_R0603ns

1 2

ESDPAD_R0603ns

1 2

ESDPAD_R0603ns

C426 1000pF/50V,X7R C0402C426 1000pF/50V,X7R C0402 C425 1000pF/50V,X7R C0402C425 1000pF/50V,X7R C0402 C427 1000pF/50V,X7R C0402C427 1000pF/50V,X7R C0402

BAT_STATE_LED CHARGE_LED PWR_LED

ESD5 EGA1-0603-V05

ESD1 EGA1-0603-V05

ESD2 EGA1-0603-V05

ESD3 EGA1-0603-V05

B B

A A

TOPSTAR TECHNOLOGY

bent

Page Name

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

bent

LED&Touch PAD&QuickButton

C46

1

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45 59Friday, November 27, 2009

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6

PR39

PR39 51K

51K

R0402

R0402 S_Top

S_Top

1

、执行

battery learning

2、S0下，EC

这两种情况，

+V3.3ALAD+

PR42

3

75K

R0402

R0402 S_Top

S_Top

1

2

PC20

PC20 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

监测到电池过压信号，

EC发出AC_OFF

时电池放电过程，

PQ5

PQ5 2N7002

2N7002

SOT23

S_Top

PR28

PR28 1K

1K

PR27

R0402

20K

S_Top

R0402

R0402 S_Top

S_Top

AC_OFF{43}

高电平信号。

AD+

C+ C-

AC_IN {21,43}

PR18

AC_OFF#

PR21

PR22

2K,1%

49.9k,1%

R0402

S_Top

1

PQ2

PQ2 2N7002

2N7002

SOT23

PR25

S_Top

10K

S_Top

3

+

2

-

0 R0402

S_Top

VCC393

84

ns

3

2

1

PU1A

PU1A LM393

LM393

SO8_50_150

SO8_50_150 S_Top

S_Top

AD+

BATT+

PR23

PR23 15K,1%

15K,1%

R0402

R0402 S_Top

S_Top

18.5-19V/4A

4A

AD+

PC11

1000pF/50V,X7R

C0402

S_Top

PR10

PR10 10

10

R0402

R0402 S_Top

S_Top

AC_OFF#

PR7

PR7 2K

2K

R0402

2

S_Top

1

PD1

PD1 BAT54C

BAT54C

SOT23

SOT23 S_Top

S_Top

BATT+

PR17

49.9k,1%

PC16

0.01UF/25V,X7R

C0402

ns

S_Top

49.9k,1%

R0402

R0402 S_Top

S_Top

AD+

PR13

PR13 51K

51K

R0402

R0402 S_Top

S_Top

PR14

PR14 51K

51K

R0402

R0402 S_Top

S_Top

3

PR9

PR9 10K

10K

R0402

ns

S_Top

PR16

PR16 15K,1%

15K,1%

R0402

R0402 S_Top

S_Top

VB:Add PC212.

PR15

PR15 51K

51K

R0402

R0402 S_Top

S_Top

PD2

1

1N4148WS

SOD323

SOD323 S_Top

S_Top

PQ1

PQ1 2N7002

2N7002

SOT23

S_Top

PC10

PC10 1000pF/50V,X7R

1000pF/50V,X7R

S_Top

PC212

0.22uF/10V,X7R

C0603

C0603 S_Top

S_Top

PQ41

PQ41 AO4419

AO4419

SO8_50_150

SO8_50_150 S_Bot

S_Bot

1 2 3

S

G

1

C0402

VCC393

PC8

0.01uF/25V,X7R

C0402

C0402 S_Top

S_Top

C+ C-

PC12

0.1uF/10V,X7R

C0402

C0402 S_Top

S_Top

Co-lay.

8 7 6 5

D

4

PR12

PR12 51K

51K

R0402

R0402 S_Top

S_Top

3

2

9-12.6V/6A

84

5

+

6

-

AD++

PQ40

PQ40 AO4419

AO4419

SO8_50_150

SO8_50_150 S_Bot

S_Bot

BATT+

7

PU1B

PU1B LM393

LM393

SO8_50_150

SO8_50_150 S_Top

S_Top

PD28

PD28 SSM34PT

SSM34PT

SMA

SMA S_Bot

S_Bot

1

PD29 SBM54PT

1

8 7 6 5

D

PR37

PR37 51K

51K

R0402

R0402 S_Top

S_Top

S_Bot

S

G

4

1N4148WS

S_Top

AD++

SMB

ns

1 2 3

SOD323

PR35

PR35 0

0

R0402

R0402 S_Top

S_Top

ns

PR40

PR40 51K

51K

R0402

R0402 S_Top

S_Top

PD3

PR11

51K

R0402

S_Top

4A

1

PQ43

AP4407

SO8_50_150

S_Bot

2N7002

SOT23

S_Top

PR31

300K

R0402

R0402 S_Top

S_Top

Isense_SYSN{54}

Isense_SYSP{36,54}

0.01UF/25V,X7R

S_Top

PD4

PD4 SSM34PT

SSM34PT

SMA

SMA S_Top

S_Top

8 7 6 5

D

PR30

PR30 10

10

R0402

R0402 S_Top

S_Top

PQ3

PC9

C0402

1

+VDC {32,40,48,49,50,51,52,55,56,57} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,47,48,49,50,52,53,5 AD+ {36,48} BATT+ {47,54}

PR222

0.025,1%

R2512

R2512 S_Bot

S_Bot

PC139

0.1UF/25V,X7R

C0603

ns

S_Bot

C0603

4A

VDC1

VDC1 TestP

8 7 6 5

SOT23

TestP

ns

TPC60

TPC60 S_Bot

S_Bot

+VDC

9V-19V/6A

46 59Friday, November 27, 2009

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B

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4

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2

S

PR29

PR29 300K

300K

R0402

ns

S_Top

PQ44

PQ44 AP4407

AP4407

SO8_50_150

SO8_50_150 S_Bot

S_Bot

PR45

PR45 51K

51K

R0402

R0402 S_Top

S_Top

1 2 3

S

1

PC29

PC29 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

D

G

4

PR44

PR44 10K

10K

R0402

R0402 S_Top

S_Top

3

PQ6

PQ6 2N7002

2N7002

S_Top

2

TOPSTAR TECHNOLOGY

bent

ADAPTER IN

M12

6A

1 2 3

PR32

PR32 51K

51K

R0402

R0402 S_Top

S_Top

PR36

PR36 100K

100K

R0402

R0402 S_Top

S_Top

PR46

PR46 51K

51K

R0402

R0402 S_Top

1

SHDN#{53}

PR33

2 3

PQ4

PQ4 MMBT3904-F

MMBT3904-F

SOT23

SOT23 S_Top

S_Top

PR33 100K

100K

R0402

R0402 S_Top

S_Top

1

S_Top

PR49

PR49 51K

51K

R0402

R0402 S_Top

S_Top

Page Name

Page Name Size

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

BATT+

SM_BAT_SDA2{43} SM_BAT_SCL2{43}

PR6 0 R0402

PR5 0 R0402

PR8 0 R0402

PC6

PFB1

PFB1 100ohm@100MHz,3A

100ohm@100MHz,3A

1 2

S_Top

FB0805

PFB2 100ohm@100MHz,3A

1 2

S_Top

FB0805

PFB3

6A 6A

PC14 1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

SM_BAT_SDA2

SM_BAT_SDA2 SM_BAT_SCL2

PC2

PC4

5.6pF/50V,NPO

C0402

C0402 S_Top

S_Top

PC2

5.6pF/50V,NPO

C0402

C0402 S_Top

S_Top

PFB3

1 2

100ohm@100MHz,3A

FB0805

FB0805 S_Top

S_Top

内层桥接走线,宽度保证有

0.1uF/25V,X7R

C0603

S_Top

PC7

0.1uF/25V,X7R

C0603 ns

C0603 ns S_Top

S_Top

100PR4

R0402

R0402 S_Top

S_Top

100

PR3 R0402

S_Top

240mils.

GND_BAT

PC6

PF1

PF1 8A

8A

FUSE1206

S_Top

1 2

SM_BAT_SDA SM_BAT_SCLSM_BAT_SCL2

+V3.3AL

PR2

PR2 300K

300K

R0402

R0402 S_Top

S_Top

GND_BAT

R0402

PC5

0.1uF/25V,X7R

C0603

ns

S_Top

BATCON1

7

6 5 4 3 2 1

6A

1KPR1

S_Top

BATT+

BATT+ KEY

KEY SDAT

SDAT SCLK

SCLK TEMP

TEMP

BAT_IN#

GND

GND GND

GND

8

SK-C103A3-100A

9

BATT_IN# {43}

PC3

0.1uF/25V,Y5V

C0402

S_Top

+V3.3AL

BAT54SPT

S_Top

2

1

PZD2

BATT+ {46,54} AD+ {36,46,48} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,48,49,50,52,53,56,57}

+V3.3AL

BAT54SPT

S_Top

2

3

PC1

0.1uF/25V,Y5V

C0402

S_Top

1

PZD1

SM_BAT_SCLSM_BAT_SDA

3

GND_BAT

TOPSTAR TECHNOLOGY

bent

Page Name

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent BATTERY IN

BATTERY IN

M12

47 59Friday, November 27, 2009

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B

5

4

3

2

+V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,49,50, +VDC {32,40,46,49,50,51,52,55,56,57} AD+ {36,46} +V5AL {29,32,36,49,50,53,56} EC_RTC {22}

1

1.输入电容要靠近MOSFET漏极

2.MOS管尽量靠近IC芯片

3.芯片的Thermal GND用至少5个过孔连到信号地,用来散热

PR210

4.信号地和电源地在输出电容的负极连到一起

10K

R0402

R0402 S_Top

S_Top

PQ72

AO4468

S_Bot

567

D

4

G

S

567

D

4

G

S

PQ73

PQ73 AO4468

AO4468

SO8_50_150

S_Bot

PR219

PR219 10K

10K

R0402

R0402 S_Top

S_Top

SO8_50_150

5A

R0402

R0402 S_Bot

S_Bot

2

PC205

PC205 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Bot

S_Bot

PC204

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

PC206

4.7uF/25V,X7R

C1206

C1206 S_Bot

S_Bot

8

PC131

PL12

5.2uH/5.5A

123

8

1

PD31

1N5819

123

SOD123

SOD123 S_Bot

S_Bot

PD30

PD30 SSM34PT

Co-lay.

SSM34PT

SMA

ns

S_Bot

Page Name

Size

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5.2uH/5.5A

LS2_1051

LS2_1051 S_Bot

S_Bot

LL2

1

PR220

2.2

R0805

R0805 S_Top

S_Top

PC129

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

Project Name Rev

12

1

PC208

220UF/6.3V,OSCON

CAP6_6x7_3

S_Bot

PC131

4.7uF/25V,X7R

C1206

C1206 S_Top

S_Top

12

ns

1

+

PC216

CT7343_19

S_Top

220UF/2.5V,POSCAP

TOPSTAR TECHNOLOGY

bent

bent +V3.3AL/+V5AL

+V3.3AL/+V5AL

C46

1

+VDC

PC155

PC155 10uF/ 25V,X7R

10uF/ 25V,X7R

C1210

ns

S_Bot

BZT52C5V6S-F/5.6

1 2

PC132

PC132 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

48 59Friday, November 27, 2009

of

V5AL1

V5AL1 TestP

TestP

ns

TPC60

TPC60 S_Bot

S_Bot

+V5AL

5A5A

PZ4

SOD323

S_Top

B

PR204

PR204 200K

200K

R0402

R0402 S_Top

S_Top

PC125

0.1uF/25V,X7R

PC127

PC127 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805 S_Top

S_Top

GND_TPS51125

+V3.3AL

GND_TPS51125

C0603 S_Top

PR218

2.2 R0402

S_Top

PR310

PR310 0

0

R0402

R0402 S_Bot

S_Bot

PR295 0

D D

GND_TPS51125

PR202

PR202 10K,1%

10K,1%

R0402

R0402 S_Top

S_Top

2

VFB1

17

VREG5

PC128

4.7uF/10V,X5R

C0805

C0805 S_Top

S_Top

ALW_PWROK{43}

PR208

PR208 15K,1%

15K,1%

R0402

R0402 S_Top

S_Top

ENTRIP1

1

VO1

ENTRIP1

PGOOD

VBST1

DRVH1

LL1

DRVL1

GND1

VCLK

18

GND_TPS51125

ENTRIP1

PC118

0.1uF/25V,Y5V

C0402

ns

S_Top

24

23

22

21

20

19

G1

+VDC

2A 2A

PC207

4.7uF/25V,X7R

C1206

C1206 S_Bot

S_Bot

C C

V3R3AL1

V3R3AL1 TestP

TestP

ns

TPC60

TPC60 S_Top

S_Top

+V3.3AL

PC134

4.7uF/25V,X7R

C1206

C1206 S_Top

S_Top

12

1

+

1 2

PZ5

PZ5 BZT52C3V6S-F/3.6

BZT52C3V6S-F/3.6

SOD323

SOD323 S_Top

S_Top

B B

VB:调整Always

A A

PC133

PC133 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

AD+

PR207

PR207 100K

100K

R0402

R0402 S_Top

S_Top

电上电波形。

5

PC209

PC209 220UF/6.3V,OSCON

220UF/6.3V,OSCON

CAP6_6x7_3

CAP6_6x7_3 S_Bot

S_Bot

PWR_SW_VCC2{36,39,43}

ALWAYS_ON{43}

PR206

PR206 15K

15K

R0402

R0402 S_Top

S_Top

PC210

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

PL11

3.3uH/4.8A

LS2_8836

LS2_8836 S_Bot

S_Bot

1

12

PR221

1

ns

2.2

+

R0805

R0805 S_Top

S_Top

PC130

PC130 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

PC215

CT7343_19

220UF/2.5V,POSCAP

2

1

PC121

0.22uF/10V,X7R

C0603

C0603 S_Top

S_Top

1

1N5819

PC211

1000pF/50V,X7R

C0402

S_Bot

PD27

SOD123

SOD123 S_Top

S_Top

PD26

PD26 1N4148WS

1N4148WS

SOD323

SOD323 S_Top

S_Top

3

PD25

PD25 BAT54C

BAT54C

SOT23

SOT23 S_Top

S_Top

PR209

5.11K,1%

R0402

R0402 S_Top

S_Top

PR203

PC120

10uF/6.3V,X5R

C0805

C0805 S_Top

S_Top

PC124

0.1uF/25V,X7R

S_Top

S_Bot

PR203

R0402

200K

S_Top

C0603

PR312

2.2 R0402

S_Bot

GND_TPS51125

EC_RTC

GND_TPS51125

567

8

123

8

1

123

D

S

567

D

S

PQ74

S

PQ74 AO4468

AO4468

SO8_50_150

SO8_50_150 S_Bot

S_Bot

PQ77

AO4468

SO8_50_150

S_Bot

4

G

PR311

PR311 10K

10K

R0402

R0402 S_Bot

S_Bot

4

G

PR309 0

R0402

5A

PR215 1K

R0402 ns

S_Top

PR217

PR217 1K R0402

1K R0402

ns

S_Top

PR212

PR212 10K

10K

R0402

R0402 S_Top

S_Top

PR211

PR211 30K

30K

R0402

ns

S_Top

4

PR213

PR213 100K

100K

R0402

ns

S_Top

GND_TPS51125

PC122

0.1uF/10V,X7R

C0402

ns

S_Top

7

8

9

10

11

12

G2

EN0_AL

1

ENTRIP1

VO2

VREG3

VBST2

DRVH2

LL2

DRVL2

GND2

VREG5

2 3

PQ38

MMBT3904-F

SOT23

SOT23 S_Top

S_Top

PR201

7.68K,1%

R0402

S_Top

S_TopPC210

R0402

R0402 S_Bot

S_Bot

5

6

ENTRIP2

EN0

13

PR308

0

R0402

S_Bot

VREF

PC126

0.022uF/16V,X7R

C0402 ns

S_Top

GND_TPS51125

PR216

4.7K

R0402

R0402 S_Top

S_Top

1

PR214

PR214 30K

30K

R0402

R0402 S_Top

S_Top

PC200

0.22uF/16V,X7R

C0603

C0603 S_Bot

S_Bot

PR296

PR296 0

0

VREF

4

3

VFB2

TONSEL

PU9

PU9 TPS51125

TPS51125

S_Top

VREF

SKIPSEL14GND15VIN16VREG5

+VDC

PR205

PR205 1K

1K

R0402

R0402 S_Top

S_Top

3

PQ37

PQ37 2N7002

2N7002

SOT23

SOT23 S_Top

S_Top

2

3

+V0.75S {15,16,56}

3

+V5AL {29,32,36,48,50,53,56} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,50,52,53,56,57} +VDC {32,40,46,48,50,51,52,55,56,57} +V1.5 {8,11,15,16,56,57} +V1.8S {11,26,28,29,31,56,57}

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,50,51,52,5

+V3.3AL

PU4

PU4 tps51218

tps51218

QFN10_0D5_0D8G

PR98

S_Top

4.7K

R0402

R0402 S_Top

12

PR90

PR90 2K

2K

R0402

R0402 S_Top

V1_5_ON{43}

S_Top

PJ2

JOPEN

JOPEN RESISTOR_1

RESISTOR_1

ns

S_Top

DDR_PWG{53}

PR97

PR97 147K,1%

147K,1%

R0402

R0402 S_Top

S_Top

0.7V

PR314

PR314 100K

100K

R0402

R0402 S_Top

S_Top

PR96

PQ17

PQ17 2N7002

2N7002

SOT23

SOT23 S_Top

S_Top

PR96 10K,1%

10K,1%

R0402

R0402 S_Top

S_Top

PU10

PU10 APL5331

APL5331

SOP8_1D27_4G

SOP8_1D27_4G S_Bot

S_Bot

1

VIN

2

GND

3

REFEN

4

VOUT

PC150

PC150 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805 S_Bot

S_Bot

PGND

9

TPC60

TestP

V0_75S1

ns

S_Bot

PC151

PC151 10uF/6.3V,X5R

10uF/6.3V,X5R

C0805

C0805 S_Bot

S_Bot

Set Fsw 290K

VCNTL

PC37

0.022uF/16V,X7R

C0402

ns

S_Top

1A-2A

+V1.5

PC149

4.7uF/10V,X5R

C0805

C0805 S_Bot

S_Bot

PC147

0.1UF/10V,X7R

C0402

S_Bot

+V3.3AL

PR57

PR57 10K

10K

R0402

R0402 S_Top

V0_75S_ON{43}

S_Top

PR56

PR56 30K

30K

R0402

ns

S_Top

1

PC32

0.022uF/16V,X7R

C0402

ns

S_Top

PC148

0.1UF/10V,X7R

C0402

C0402 S_Bot

S_Bot

PR55

4.7K

R0402

R0402 S_Top

S_Top

PQ18

PQ18 MMBT3904-F

MMBT3904-F

S_Top

2 3

PR54

PR54 2K,1%

2K,1%

R0402

R0402 S_Top

S_Top

PR53

PR53 2K,1%

2K,1%

R0402

R0402 S_Top

S_Top

3

1

2

PR95

PR95 470K

470K

R0402

R0402 S_Top

S_Top

NC3 NC2

NC1

1

2

3

4

5

PGOOD

TRIP

EN

VFB

RF

8 7 6 5

TPS51218

PC38

0.022uF/16V,X7R

ns

C0402

C0402 S_Top

S_Top

+V3.3AL

+V5AL

PR103

PR103 0

0

R0402

R0402 S_Top

S_Top

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

GND

11

PR91

11.5K,1% R0402

S_Top

PC142

4.7uF/10V,X5R

C0805

C0805 S_Bot

S_Bot

PR92

PR92 20K

20K

R0402

R0402 S_Top

S_Top

+V0.75S

PC52

4.7uF/10V,X5R

C0805

C0805 S_Top

S_Top

ns

1A-2A 2A Max +/-15mV DC +/-65mV DC+AC Linear

PC50

0.1uF/25V,X7R

C0603 S_Top

PR229

2.2

R0402

S_Bot

PR231

0

R0402

S_Bot

8.2m ohm@4.5V/AO4706

4.3m ohm@4.5V/AOL1718

PR230

PR230 10K

10K

S_Bot

PQ50

PQ50 AO4706

AO4706

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

56789

D

4

G

S

56789

D

4

G

S

PC74

10uF/6.3V,X5R

C0805

C0805 S_Top

S_Top

PQ49

PQ49 SI4892DY

SI4892DY

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

123

1

123

PD11

PD11 SSM34PT

SSM34PT

SMA

SMA S_Top

S_Top

PD15 1N4148WS

SOD323

ns

1

S_Top

VIN3VOUT

Vo

ADJ/GND

PU6

1

APE1117C

SOT223

SOT223 S_Top

S_Top

PC53

0.1uF/25V,X7R

C0603

C0603 S_Top

S_Top

PR119

2.2

R0805

R0805 S_Top

S_Top

PC58

PC58 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

2 4

PL5

1.0uH/11A

LS2_6530

1

S_Bot

PC160

PC160 220UF/6.3V,OSCON

220UF/6.3V,OSCON

CAP6_6x7_3

CAP6_6x7_3 S_Bot

S_Bot

PR140

PR140 220

220

R0402

R0402 S_Top

S_Top

PR141

PR141 100,1%

100,1%

R0402

R0402 S_Top

S_Top

PC41

PC41 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

12

1

+

加强此器件散热。

PC57

10uF/6.3V,X5R

C0805

C0805 S_Top

S_Top

PC49

4.7uF/25V,X7R

C1206

C1206 S_Top

S_Top

12A

1

220UF/6.3V,OSCON

1A Max

PC60

10uF/6.3V,X5R

C0805

C0805 S_Top

S_Top

+VDC

2A

PC43

PC43 10uF/ 25V,X7R

10uF/ 25V,X7R

C1210

C1210 S_Top

S_Top

V1R5

V1R5 TestP

TestP

TPC60

ns

S_Top

12

+

PC156

CAP6_6x7_3

S_Bot

S_Top

PC55

0.1uF/10V,X7R

C0402

C0402 S_Top

S_Top

PZ2

PZ2 BZT52C2V0S-F/2.0V

BZT52C2V0S-F/2.0V

SOD323

1 2

ns

S_Top

V1R8S1

V1R8S1 TestP

TestP

TPC60

ns

S_Top

OCP>14A +/-3.3% DC 5% DC+ AC Switcher

+V1.8S+V3.3S

+V1.5

12A

1A

PR142

PC71

10uF/6.3V,X5R

C0805

C0805 S_Top

S_Top

Page Name

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

PR142 1K

1K

R0402

ns

S_Top

TOPSTAR TECHNOLOGY

bent

bent +V1.8/+V0.9S DDR

+V1.8/+V0.9S DDR

M12

49 59Friday, November 27, 2009

of

B

+VDC {32,40,46,48,49,51,52,55,56,57} +V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,51,52,53,55,56,57,58} +V5S {23,25,29,32,33,34,35,36,37,38,43,51,52,55,56} +V1.05S {22,23,24,28,29,56,57,58} +V1.5S {39,40,41,56} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,52,53,56,57}

+V3.3S

PU3

PU3 tps51218

PR84

4.7K

R0402

R0402 S_Top

VTT_PWG{43,53}

12

PJ1

PR315

PR315 100K

100K

R0402

R0402 S_Top

S_Top

PJ1

JOPEN

JOPEN RESISTOR_1

RESISTOR_1

ns

S_Top

PC33

0.022uF/16V,X7R

C0402

C0402 S_Top

S_Top

PR61

PR61 2K

2K

R0402

R0402 S_Top

V1_1S_VTT_ON{43}

S_Top

PR83

PR83 147K,1%

147K,1%

R0402

R0402 S_Top

S_Top

ns

0.7V

PR58

71.5K,1%

R0402

R0402 S_Top

PR82

PR82 10K,1%

10K,1%

R0402

R0402 S_Top

S_Top

tps51218

QFN10_0D5_0D8G

QFN10_0D5_0D8G S_Top

S_Top

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

PR81

PR81 470K

470K

R0402

R0402 S_Top

S_Top

Set Fsw 290K

3

2N7002

S_Top

2

TPS51218

PC34

0.022uF/16V,X7R

C0402 ns

C0402 ns S_Top

S_Top

PQ7

SOT23

1

MMBT3904-F

S_Top

+V5AL

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

GND

11

PR59 4.99K,1%

R0402

S_Top

PQ19

2 3

PR85

PR85 0

0

R0402

R0402 S_Top

S_Top

PC145

4.7uF/10V,X5R

C0805

C0805 S_Bot

S_Bot

PR60 20K

R0402 ns

S_Top

PR76

1

PC35

0.1uF/25V,X7R

C0603

C0603 S_Top

S_Top

47KR0402

S_Top

PR78

PR78 100K

100K

R0402

R0402 S_Top

S_Top

ns

+V3.3S

PR77

PR86

2.2

R0603

S_Top

PR93

0

R0603

S_Top

PQ46

PQ46 AO4706

AO4706

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

PR88

0

R0603

R0603 S_Top

S_Top

10KR0402

S_Top

56789

D

4

G

S

PR87

PR87 10K

10K

S_Top

56789

D

4

G

S

VTT_SELECT {10}

高电平为

1.05V/1.1V.

PQ45

PQ45 AOL1426

AOL1426

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

123

56789

D

4

G

S

123

PQ47

PQ47 AO4706

AO4706

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

8.2m ohm@4.5V/AO4706

4.3m ohm@4.5V/AOL1718

PC144

PC143

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

PC144 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Bot

S_Bot

Co-lay.

1

123

PD8

PD7

PD7 SSM34PT

SSM34PT

SBM54PT

SMA

SMB

S_Top

ns

S_Top

VTT_SELECT Vo Arrandale: High 1.05V Clarksfield: Low 1.1V

+V5AL {29,32,36,48,49,53,56} +V1.1S_VTT {8,10,11,27,28,29,38,51,55}

PC146

PC146 10uF/ 25V,X7R

10uF/ 25V,X7R

C1210

C1210 S_Bot

S_Bot

PL4

220UF/6.3V,OSCON

CAP6_6x7_3

12

1

+

PC157

CAP6_6x7_3

S_Bot

CAP6_6x7_3 S_Bot

S_Bot

1

1.0uH/18A

LS2_1040

LS2_1040 S_Bot

S_Bot

PR89

2.2

R0805

R0805 S_Top

S_Top

PC36

PC36 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

220UF/6.3V,OSCON

PC161

12

1

+

220UF/6.3V,OSCON

PC152

PC152 10uF/ 25V,X7R

10uF/ 25V,X7R

C1210

C1210 S_Bot

S_Bot

20A

PC166

C0402

0.1uF/10V,X7R

12

S_Bot

1

+

PC158

CAP6_6x7_3

S_Bot

V1_1SVTT1

V1_1SVTT1 TestP

TestP

TPC60

ns

S_Bot

1 2

+VDC

3A

PZ7

PZ7 BZT52C2V0S-F/2.0V

BZT52C2V0S-F/2.0V

SOD323

ns

S_Bot

+V1.1S_VTT

18-20A

ICCmax=23A +/-2% DC, 3% AC+ripple Switcher

GND

VBST

DRVH

V5IN

DRVL

+V5AL

PC70

PC70 10uF/ 25V,X7R

10uF/ 25V,X7R

C1210

C1210 S_Top

S_Top

+VDC

2A

V1_05S1

V1_05S1 TestP

TestP

TPC60

ns

S_Top

PZ6

PZ6 BZT52C2V0S-F/2.0V

BZT52C2V0S-F/2.0V

SOD323

1 2

ns

S_Bot

+V1.05S

8A +/-5% Switcher

TOPSTAR TECHNOLOGY

bent

Page Name

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent +V1.5S/+V1.05S CHIPSET

+V1.5S/+V1.05S CHIPSET

M12

50 59Friday, November 27, 2009

of

B

PR139

Co-lay.

PR139 0

0

R0402

R0402 S_Top

S_Top

PC72

0.1uF/25V,X7R

C0603

10

9

8

SW

7

6

PC73

4.7uF/10V,X5R

C0805

C0805 S_Top

S_Top

PR129

PR129 20K

20K

R0402

ns

S_Top

C0603 S_Top

S_Top

PQ51

PQ51 AO4468

AO4468

SO8_50_150

S_Bot

PR233

2.2

R0603

S_Bot

PR138

0

R0603

S_Top

PQ26

PQ26 AO4468

AO4468

SO8_50_150

S_Top

22m ohm@4.5V/AO4468

4

PR232

PR232 10K

10K

S_Bot

4

567

8

D

G

S

123

567

8

D

G

S

1

1N5819

123

SOD123

SOD123 S_Top

S_Top

Co-lay.

PD12

PC66

0.1uF/25V,X7R

C0603

C0603 S_Top

S_Top

PD13

PD13 SSM34PT

SSM34PT

1

SMA

ns

S_Top

PC62

PC62 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

PL6

1.0uH/11A

LS2_6530 S_Bot

1

PR135

2.2

R0805

R0805 S_Top

S_Top

PC63

PC63 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

PC69

4.7uF/25V,X7R

C1206

ns

S_Top

8A

12

1

+

PC162

220UF/6.3V,OSCON

CAP6_6x7_3

CAP6_6x7_3 S_Bot

S_Bot

PC163

C0402

0.1uF/10V,X7R

S_Bot

+V3.3AL

PU7

PU7 tps51218

tps51218

QFN10_0D5_0D8G

PR131

S_Top

4.7K

R0402

R0402 S_Top

PR134

PR134 10K,1%

10K,1%

R0402

R0402 S_Top

S_Top

PR132

PR132 270K

270K

R0402

R0402 S_Top

S_Top

1

2

3

4

5

PR136

PR136 200K

200K

R0402

R0402 S_Top

S_Top

Set Fsw 340K

TPS51218

PGOOD

TRIP

EN

VFB

RF

PC67

0.022uF/16V,X7R

C0402

C0402 S_Top

S_Top

11

PR128

4.99K,1% R0402

S_Top

ns

V1.05S_PWG{53}

12

PJ3

PR124

JOPEN

2K

RESISTOR_1

R0402

ns

S_Top

V1_1S_VTT_ON{43}

S_Top

0.7V

PR316

PR316 100K

100K

R0402

R0402 S_Top

S_Top

0.022uF/16V,X7R

PC64

C0402

ns

S_Top

GFXVR_EN{11}

5

高电平为

1.05V/1.1V.

PR152

PR152 10K

10K

R0402

R0402 S_Top

S_Top

PR151

PR151 30K

30K

R0402

ns

S_Top

PJ4 JOPEN

RESISTOR_1

ns

1 2

S_Top

PC79

0.022uF/16V,X7R

C0402

ns

S_Top

PR176

PR176 470K

470K

R0402

ns

S_Top

GND_ISL62881

VGFXVCCSEN{11}

VGFXVSSSEN{11}

+V3.3AL

PR157

PR157 47K

47K

R0402

R0402 S_Top

S_Top

1

PQ29

1

MMBT3904-F

SOT23

2 3

S_Top

PC100

100pF/50V,NPO

C0402

S_Top

+VGFX

+V3.3S

PR248

4.7K

R0402

R0402 S_Bot

S_Bot

PC90

0.022uF/16V,X7R

3

C0402

ns

S_Top

PQ30

PQ30 2N7002

2N7002

2

SOT23

SOT23 S_Top

S_Top

GFXVR_PWRGD{53}

PC93 1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

PR177

PR178

PR178 75K

75K

R0402

R0402 S_Top

S_Top

R0402

10K,1%

S_Top

PC94

PC94 3300pF/50V,X7R

3300pF/50V,X7R

C0402

C0402 S_Top

S_Top

PR173

2.37K,1%

R0402

R0402 S_Top

S_Top

PR179

6.98K,1%

R0402

R0402 S_Top

S_Top

PR252 10

R0402

PR253 0

R0402

PR251 10

R0402

PR175 0

R0402

250KHz

S_Bot

S_Top

GFXVR_VID_0{11}

GFXVR_VID_1{11}

GFXVR_VID_2{11}

GFXVR_VID_3{11}

GFXVR_VID_4{11}

GFXVR_VID_5{11}

GFXVR_VID_6{11}

GFXVR_DPRSLPVR{11}

+V3.3S

PR171

PR171 2K

2K

R0402

R0402 S_Top

S_Top

VGFX_ON

PR172 47K R0402

PC95

270pF/25V,X7R

C0402

C0402 S_Top

S_Top

GND_ISL62881

PC174

PC174 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Bot

S_Bot

GND_ISL62881

PR250 10K R0402

ns S_Bot

PR170

PR170 2K

2K

R0402

ns

S_Top

PC177

PC177 270pF/25V,X7R

270pF/25V,X7R

C0402

C0402 S_Bot

S_Bot

PR166 0 R0402

S_Top

1

CLK_EN#

2

PGOOD

3

RBIAS

4

VW

5

COMP

6

FB

7

VSEN

PR241

PR243

2.2K

R0402

ns

S_Bot

PR246

2.2K

R0402

ns

S_Bot

28

27

26

VID525VID6

VR_ON

DPRSLPVR

PU8

PU8 ISL62881

ISL62881

S_Top

QFNS28_0D4_1G

RTN8ISUM-9ISUM+10VDD11VIN

PR169

82.5,1%

R0402

R0402 S_Top

S_Top

PC96

0.01uF/25V,X7R

C0402

C0402 S_Top

S_Top

PR174

PR174 100

100

R0402

ns

S_Top

+V1.1S_VTT

PR240

2.2K

R0402

R0402 S_Bot

S_Bot

24

IMON13BOOT

12

PC89

0.22uF/10V,X7R

C0603

C0603 S_Top

S_Top

PC92

0.047uF/50V,X7R

C0603

C0603 S_Top

S_Top

PR180

4.02K,1%

R0402

R0402 S_Top

S_Top

PC99

470pF/25V,X7R

C0402

ns

S_Top

ns

PR160

0

R0402

ns

S_Top

VID222VID323VID4

VID1

VID0

VCCP

LGATE

VSSP

PHASE

UGATE

GND2 GND1

14

PR163 1

R0402 S_Top

GND_ISL62881

PC91

0.1uF/25V,X7R

C0603

C0603 S_Top

S_Top

PR237

PR237 0

0

R0402

ns

S_Bot

21

20

19

18

17

16

15 G2

G1

GND_ISL62881

+V5S

PC172

PC172 1uF/10V,X7R

1uF/10V,X7R

C0603

S_Bot

PR161 100

R0402

+V5S

PC176

0.01uF/25V,X7R

C0402

C0402 S_Bot

S_Bot

PC175

0.1uF/10V,X7R

C0402

C0402 S_Bot

S_Bot

GND_ISL62881

PR153

PR153 0

0

R0402

R0402 S_Top

S_Top

PR249

PR249 10K,1%

10K,1%

R0402

R0402 S_Bot

S_Bot

PR236

2.2

R0402

S_Bot

PC87

0.22uF/16V,X7R

C0603

C0603 S_Top

S_Top

PR159

22.1K,1%

R0402

R0402 S_Top

S_Top

PR239 0

R0402

PC173

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

GND_ISL62881

4

G

PR235

PR235 10K

10K

S_Bot

PR234

2.2

R0402

S_Bot

4

G

PQ52

PQ52 AOL1718

AOL1718

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

G

PC88

0.22uF/10V,X7R

C0603

C0603 S_Top

S_Top

PC213

0.22uF/10V,X7R

C0603

C0603 S_Top

S_Top ns

ns

S_Bot

PR247

2.49K,1%

R0402

R0402 S_Bot

S_Bot

PR143

PR143 10K,1%

10K,1%

R0603

R0603 S_Top

S_Top

NTC thermistor

度下，

10K

25

度下，

3.05K

60

度下，

1.71K

80

放于电感背面。

56789

D

S

56789

D

S

VGFXVSSSEN {11}

+VDC

3.57K,1%

S_Bot

。

PC78

0.1uF/25V,X7R

C0603

C0603 S_Top

S_Top

PQ53

PQ53 AOL1426

AOL1426

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

123

1

123

PD16

PD17

PD17 SSM54PT

SSM54PT

SSM34PT

SMA

ns

S_Top

VGFX_IMON1

VGFX_IMON1 TestP

TestP

TPC60

ns

S_Top

PR244

R0402

+V1.1S_VTT {8,10,11,27,28,29,38,50,55} +V5S {23,25,29,32,33,34,35,36,37,38,43,52,55,56} +V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,52,53,55, +VGFX {11} +VDC {32,40,46,48,49,50,52,55,56,57} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,49,50,52,53,56,57}

PC80

PC80 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

+VDC

2A

PC168

PC170

10uF/ 25V,X7R

C1210

S_Bot

Co-lay.

+VGFX

12

1

+

PC164

220UF/6.3V,OSCON

CAP6_6x7_3

S_Bot

VGFX2

VGFX2 TestP

TestP

TPC60

ns

14A

S_Bot

PC167

C0402

0.1uF/10V,X7R

12

1

S_Bot

+

PC165

220UF/6.3V,OSCON

CAP6_6x7_3

CAP6_6x7_3 S_Bot

S_Bot

TOPSTAR TECHNOLOGY

+V1.5AL

C46

14A LL=7 mOhm

+VGFX

1 2

PZ3

PZ3 BZT52C2V0S-F/2.0V

BZT52C2V0S-F/2.0V

SOD323

ns

S_Top

51 59Friday, November 27, 2009

of

PR145

2.2

R0805

R0805 S_Top

S_Top

1

Co-lay.

PC77

PC77 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

VGFX_IMON {11}

A3

10uF/ 25V,X7R

S_Bot

PL8

1.0uH/18A

LS2_1040 S_Bot

1

PL7

1.0uH/11A

LS2_6530

ns

S_Bot

Page Name

Size

Project Name Rev

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

B

5

D D

PU5

PU5 ISL62872

ISL62872

QFNR20_0D4_0D5

500mA

LGATE

PC48

0.1uF/10V,X7R

PR104

12

PR110

4.99K,1%

R0402

PM

S_Top

PC54

0.1uF/10V,X7R

C0402

PM

S_Top

GND_62872

PR123

1K

S_Top

S_Top R0402

R0402

PM

5

PR104 30K

30K

R0402

PM

S_Top

PR112

PR112 10K,1%

10K,1%

R0402

R0402 S_Top

S_Top

PM

PR100 0 R0402

C0402

ns

S_Top

PR122

10K

R0402

R0402 S_Top

S_Top

PM

GND_62872

PR113

45.3K,1%

R0402

PM

S_Top

PM

PQ22

PQ22 2N7002

2N7002

SOT23

PM

S_Top

PC59

0.1uF/10V,X7R

C0402

ns

S_Top

VID0

GND_62872

+V3.3S

1

PR101

PR101 2K

2K

R0402

VGPU_ON{43}

+V3.3AL

C C

B B

GPU_VID0{21}

A A

R0402

PM

S_Top

J1

JOPEN

JOPEN RESISTOR_1

RESISTOR_1

ns

GND_62872

PR114

PR114 220K

220K

R0402

PM

S_Top

3

2

PR108

10K

R0402

R0402 S_Top

S_Top

PM

1

LGATE

2

PGND

3

GND

4

EN

5

VID1

6

VID0

7

SREF

8

SET0

9

SET1

10

SET2

PR154

10K

R0402

R0402 S_Top

S_Top

PM

PM S_Top

+V3.3S

VID0

4

PVCC

VCC

BOOT

UGATE

PHASE

OCSET

PGOOD

PR115

PR115 10K

10K

R0402

PM

S_Top

VGACORE_PWRGD{43}

3

PC42

0.1uF/10V,X7R

C0402

PM

S_Top

PR99

2.2

20

19

18

17

2.2

R0402

PM

S_Top

PC46

0.1uF/25V,X7R

C0603 PM

C0603 PM S_Top

S_Top

16

15

NC

14

13

VO

12

FB

PC44

PC44 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

S_Top

PC45

PC45 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

S_Top

500mA

LGATE

500mA

11

PR109 100,1%

R0402

PM

S_Top

PR111 2.49K,1%

R0402 PM

PR116

4.02K,1%

R0402

PM

S_Top

GND_62872

PR127

1K

GPU_VID1{21}

R0402

PM

1K

S_Top

+V5S

PR94

2.2

R0402

PM

S_Top

PR228

2.2

R0402

PM

S_Bot

SO8_50_150_PPAK

PC56

PC56 3300pF/50V,X7R

3300pF/50V,X7R

C0402

PM

S_Top

PR130

10K

R0402

PM

S_Top

PQ48

PQ48 AOL1718

AOL1718

PM

S_Bot

+V3.3S

1

PC65

0.1uF/10V,X7R

C0402

ns

S_Top

3

4

3

2

D

G

D

G

PR106

10K

R0402

R0402 S_Top

S_Top

56789

S

56789

S

PM

PQ21

PQ21 2N7002

2N7002

SOT23

PM

S_Top

PQ20

PQ20 AOL1426

AOL1426

SO8_50_150_PPAK

PM

S_Top

123

Co-lay.

1

123

PD9

PD9 SSM54PT

SSM54PT

SMA

ns

S_Top

VID1

PR155

10K

R0402

R0402 S_Top

S_Top

PM

PR102

R0805

PM

PD10

PD10 SSM34PT

SSM34PT

1

SMA

PM

S_Top

PC47

1000pF/50V,X7R

C0402

S_Top

PC40

0.1uF/25V,X7R

C0603

PM

S_Top

2.2

S_Top

PR105

9.31K,1%

R0402

PM

S_Top

PC51

0.047uF/50V,X7R

C0603 PM

C0603 PM S_Top

S_Top

PM

VID1 VID0 Vo 0 0 1.03V 0 1 0.85V 1 1 0.8V

PL2

1.0uH/11A

LS2_6530

ns

1

S_Bot

PL3

1.0uH/18A

LS2_1040

1

S_Bot

9.31K,1%

9.31K,1% PR107

PR107

S_Top

2

+VGA_CORE {17} +VDC {32,40,46,48,49,50,51,55,56,57} +V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,53,55,56,57,58} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,53,56,57} +V5S {23,25,29,32,33,34,35,36,37,38,43,51,55,56}

+V3.3GPU {17,20,21,33,34,57}

+VDC

1

2A

PC39

PC153

PC153 10uF/ 25V

10uF/ 25V

C1210

PM

S_Bot

Co-lay.

PM

R0402

PM

PD14

1

1N5819

SOD123

ns

S_Top

2

PC154

PC154 10uF/ 25V

10uF/ 25V

C1210

PM

S_Bot

12

1

+

PC159

PC159 220uF/2.5V,POSCAP

220uF/2.5V,POSCAP

CT7343_19

PM

S_Bot

PR137

PR137 10

10

R0402

ns

S_Top

PC39 1000pF/50V,X7R

1000pF/50V,X7R

C0402

PM

S_Top

PR117

PR117 10

10

R0402

PM

S_Top

1

GC2

GC2 220uF/2.5V,POSCAP

220uF/2.5V,POSCAP

CT7343_19

PM

S_Top

+V3.3GPU+VGA_CORE

Page Name

Page Name Size

Size

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

NVVDD_SENSE {17}

13A

12

+

Project Name Rev

+VGA_COREVID1

PZ1

PZ1 BZT52C2V0S-F/2.0V

BZT52C2V0S-F/2.0V

SOD323

1 2

ns

S_Top

TOPSTAR TECHNOLOGY

bent

+VGA_CORE

S46

+VGA_CORE

VGA_CORE1

VGA_CORE1 TestP

TestP

TPC60

ns

S_Top

52 59Friday, November 27, 2009

of

1

13A

B

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,

5

+V5AL {29,32,36,48,49,50,56} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,56,57} +V1.05S {22,23,24,28,29,50,56,57,58} +V1.5S {39,40,41,56} +VCC_CORE {10,55}

SHDN#{46}

PQ69

PQ69 MMBT2907

MMBT2907

SOT23

SOT23 S_Bot

R0402

R0402 S_Bot

S_Bot

1

2 3

PR307 10K

SHDN_LOCK#{38}

PQ66

MMBT3904-F

SOT23

S_Bot

23

PR304

PR304 100

100

R0402

R0402 S_Bot

S_Bot

+V5AL

+V3.3AL

PZ9

PZ9 BZT52C5V6S-F/5.6

BZT52C5V6S-F/5.6

SOD323

SOD323 S_Bot

S_Bot

PZ8

1 2

PC203

PC203 1uF/10V,X7R

1uF/10V,X7R

C0603

C0603 S_Bot

S_Bot

PZ8 BZT52C3V6S-F/3.6

BZT52C3V6S-F/3.6

SOD323

1 2

S_Bot

Power Good Logic CIRCUIT

+V3.3S

PR194

PR194 10K

10K

R0402

R0402 S_Top

S_Top

AD+ {36,46,48}

VTT_PWG{43,50}

V1.05S_PWG{50}

PR195

R0402

GFXVR_PWRGD{51}

DDR_PWG{49}

PM_RSMRST#{24,43}

PM_SLP_S3#{24,41,43}

R0402

0

S_Top GM

R323 1K

R0402

S_Top

1

2

PD33

PD33 1N5819

1N5819

SOD123 GM

PD32

PD32 1N5819

1N5819

SOD123

1

2

C259

0.1UF/10V,X7R

C0402

S_Top

3

PD21

PD21 BAT54A

BAT54A

S_Top

1

3

PD23

PD23 BAT54A

BAT54A

S_Top

SOT23

MAIN_PWROK {24,43}

TOPSTAR TECHNOLOGY

bent

Page Name

Size

Project Name Rev

A4

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent Power Good Logic/OVP

Power Good Logic/OVP

M12

53 59Tuesday, January 05, 2010

of

B

BATT+ {46,47}

SET_I 充电电流

0V 0A

0.4V 0.4A

1.2V 1.2A 2V 2A

SYS_I_Sense

500mV

1.5V

1.67V

Isense_SYSP{36,46}

Isense_SYSN{46}

SET_I{43}

SYS_CURRENT

1A 3A

3.33A

CHG_GND

CHG_ON{43}

PR226 10K

PC21

PC21 1uF/10V,X7R

1uF/10V,X7R

C0603

C0603 S_Top

S_Top

1uF/10V,X7R

S_Top

PR47

10 R0402

S_Top

CHG_GND

S_Bot

PR225

15.4K,1%

R0402

ns

S_Bot

设置适配器限流值为

82mV/25m ohm=3.28A.

PC31

C0603

PC24

PR52

4.7

R0402

R0402 S_Top

S_Top

PC26

PC26 1000pF/25V,X7R

1000pF/25V,X7R

C0402

S_Top

10KR0402

S_Top

3.3V

PC140

PC140 1uF/10V,X7R

1uF/10V,X7R

C0603

S_Bot

VDDP

5V_internal_LDO

PC25

0.1uF/25V,X7R

C0603

C0603 S_Top

S_Top

PC27

PC27 5600pF/50V,Y5V

5600pF/50V,Y5V

C0603

S_Top

PC23 0.01uF/25V,X7R

C0402

S_Top

2.39V_Vref

PR41

10.5K,1%

R0402

R0402 S_Top

S_Top

0.643Vref

PR38

PR38 20K,1%

20K,1%

R0402

R0402 S_Top

S_Top

CHG_GND

15

1

19

20

5

6

11

3

9

8

10

23

CHG_GND

VDDP

VDD

CSIP

CSIN

ICOMP

VCOMP

VADJ

EN

CHLIM

VREF

ACLIM

ACPRN

PU2

PU2 ISL6251HAZ

ISL6251HAZ

S_Top

SSOP24_25_150

PR34 0

R0402

S_Top

ACSET

DCIN

UGATE

BOOT

PHASE

LGATE

PGND

CSOP

CSON

CELLS

GND

ICM

PR50 0

2

R0402

24

17

16

18

14

13

21

22

PR227 0 R0402

4

7

12

CHG_GND

S_Top

0.1uF/25V,X7R

S_Top

PC141

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

PR43

100 R0402

S_Top

CHG_GND

PC30

C0603

PR224 2.2

R0402

PD5

1N5819

SOD123

SOD123 S_Top

S_Top

PC28

PC28 1uF/10V,X7R

1uF/10V,X7R

C0603

S_Top

S_Bot

1

phase

PR19

R0402

CHG_GND

VDDP

0

S_Top

PC22

3300pF/50V,X7R

C0402

C0402 S_Top

S_Top

PC137

PC137 1000pF/50V,X7R

D1D1

1000pF/50V,X7R

C0402

C0402 S_Bot

S_Bot

PQ42

PQ42 AO4932

AO4932

SO8_50_150

SO8_50_150 S_Bot

S_Bot

7 6

PL1

phase

1

15uH/3.6A

PR26

LS2_1040

2.2

S_Bot

R0805

ns

S_Top

PC15

0.01uF/25V,X7R

C0402

ns

S_Top

PR48

2.2 R0402

S_Top

PD6

SOD323

PD6

SOD323

1N4148WS

1

ns

S_Top

PR51 0

R0402

PR223

8

10K

G1

R0402

R0402 S_Bot

S_Bot

5

3

SYS_I_Sense {43}

S_Top

2

D2

S2G2

4

1

S1

Layout note: Far away from critical signal trace

1.5A

PC138

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

PC13

PC13 10uF/ 25V

10uF/ 25V

C1210

S_Top

PC136

4.7uF/25V

C1206

C1206 S_Bot

S_Bot

PR24

PR24 50mOHM,1%

50mOHM,1%

R2512

R2512 S_Top

S_Top

2A

PC135

PC135 10uF/ 25V

10uF/ 25V

C1210

ns

S_Bot

PC19

10uF/ 25V

C1210

S_Top

Isense_SYSN {46}

Co-lay.

PC17

0.1uF/25V,X7R

C0603

C0603 S_Top

S_Top

PC18

PC18 1uF/25V,Y5V

1uF/25V,Y5V

C0805

C0805 S_Top

S_Top

BATT+

12.63V 2A Max

SYS_CURRENT

>3.6A >1.8V <3A

SYS_I_Sense

<1.5V

SYS_I_Trip

High Low

Cells status Battery Pak

Float 2S GND 3S VDD 4S

TOPSTAR TECHNOLOGY

bent

Page Name

Page Name Size

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

bent CHARGER

CHARGER

M12

54 59Friday, November 27, 2009

of

B

5

H_VID0{10} H_VID1{10} H_VID2{10} H_VID3{10} H_VID4{10} H_VID5{10}

+V1.1S_VTT

PR282

PR282 2K R0402

2K R0402

S_Bot

PR286

PR286 2K R0402

2K R0402

S_Bot

IMVP_PWRGD{43}

PR292

PR292 147K,1%

147K,1%

R0402

R0402 S_Bot

S_Bot

VR_PROCHOT#{8}

PR185

PR185 470K,1% R0603

470K,1% R0603

S_Top

PR303

PR303 10

10

R0402

R0402 S_Bot

S_Bot

PC202

PC202 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Bot

S_Bot

PC117

PC117 1000pF/50V,X7R

1000pF/50V,X7R

C0402

C0402 S_Top

S_Top

CPU_GND

1000pF/50V,X7R

S_Top

PR193

0

R0603

R0603 S_Top

S_Top

H_VID6{10}

PR287 470 R0402

S_Bot

10KPR284

R0402 ns

CK505_CLK_EN#{6}

S_Bot

NTC

PC198

C0402

PC198

C0402

100pF/50V,NPO

S_Bot

ISEN2

PC112

0.22uF/16V,X7R

C0603

CPU_GND

S_Top

PC116 0.22uF/16V,X7R

ISUM-

PC113

C0402

CPU_GND

39

40

1

PGOOD

CLK_EN#

2

PSI#

3

RBIAS

4

VR_TT#

5

NTC

6

VW

7

COMP

8

FB

9

FB2

10

ISEN2

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD16VIN17IMON18BOOT119UGATE1

G2G2G1G1G3

G3

C0603

S_Top

ISEN1

D D

IMVP_ON{43}

+V1.1S_VTT

PM_PSI#{10}

CPU_GND

C C

NTC thermistor放到板面最热的地方

B B

VCCSENSE{10}

1uF/10V,X7R

S_Top

VSSSENSE{10}

A A

PR279 2K R0402

PR279 2K R0402 PR278 1K R0402

PR278 1K R0402

10KPR291 R0402

S_Bot

PC196

1000pF/50V,X7R

PR300

S_Bot

4.02K,1%

R0402

R0402 S_Bot

S_Bot

PR301

PR301 PC197

PC197

C0402

1000pF/50V,X7R

S_Bot

PC201

100pF/50V,NPO

C0402

S_Bot

PC115

0.1UF/10V,X7R

C0603

S_Top

ns

S_Bot

S_Bot S_Bot

S_Bot

+V3.3S

ns

10KPR289 R0402

S_Bot

CPU_GND

C0402

R0402

6.98K,1%

S_Bot

3300pF/50V,X7R

S_Bot

PR293

3.01K,1%

R0402

R0402 S_Bot

S_Bot

PR294

PR294 10

10

R0402

R0402 S_Bot

S_Bot

PR198

PR198 10

10

R0402

R0402 S_Top

S_Top

PC114

C0402

PR196

PR196 0

0

R0402

R0402 S_Top

S_Top

5

PM_DPRSLPVR{10}

PC199

C0402

PR302

PR302 75K

75K

R0402

R0402 S_Bot

S_Bot

CPU_GND

38

VR_ON

DPRSLPVR

4

37

PU11

PU11 ISL62882HRTZ

ISL62882HRTZ

S_Bot

QFNS40_0D4_1G

PR280

82.5,1%

R0402

R0402 S_Bot

S_Bot

PC193

0.01uF/25V,X7R

C0402

C0402 S_Bot

S_Bot

PR290

PR290 100

100

R0402

ns

S_Bot

4

PR266

PR266 100

100

R0402

R0402 S_Bot

S_Bot

PR267

PR267 10K,1%

10K,1%

R0402

R0402 S_Bot

S_Bot

PC183

0.22uF/10V,X7R

C0603

C0603 S_Bot

S_Bot

PR288

1.58K,1%

R0402

R0402 S_Bot

S_Bot

PR275

PR275 1K

1K

R0402

ns

S_Bot

PC105

0.22uF/16V,X7R

C0603

C0603 S_Top

S_Top

PC191

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

PC194

470pF/25V,X7R

C0402

ns

S_Bot

PR147 1K R0402

PR147 1K R0402 PR148 1K R0402

PR148 1K R0402 PR149 1K R0402

PR149 1K R0402 PR269 1K R0402 ns

PR269 1K R0402 ns PR273 1K R0402 ns

PR273 1K R0402 ns PR276 1K R0402

PR276 1K R0402

PR270

PR270 1K

1K

R0402

R0402 S_Bot

S_Bot

CPU_GND

G9

G8

VID031VID132VID233VID334VID435VID536VID6

G7

30

BOOT2

29

UGATE2

28

PHASE2

27

VSSP2

LG2

26

LGATE2

25

VCCP

24

LGATE1b

23

LGATE1a

22

VSSP1

21

PHASE1

G4G4G5G5G6

20

G6

CPU_GND

PR277 10 R0402

S_Bot

PC188 1uF/10V,X7R C0603

S_Bot

PC185 0.1uF/25V,X7RC0603

PR274

PR274 10

10

R0402

R0402 S_Bot

S_Bot

Vcore_IMON {10}

Vcore_IMON1

Vcore_IMON1 TestP TPC60

TestP TPC60

ns

PC190

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

CPU_GND

PC192

0.01uF/25V,X7R

C0402

C0402 S_Bot

S_Bot

GND_ISL62881

PR268

PR268 1K

1K

R0402

R0402 S_Bot

S_Bot

PC101

0.22uF/16V,X7R

C0603

C0603 S_Top

S_Top

0PR182 R0603

S_Top

0PR255 R0603

S_Bot

UG1

+V5S

+VDC

PC195

0.1uF/10V,X7R

C0402

C0402 S_Bot

S_Bot

PR150

PR150 1K

1K

R0402

R0402 S_Top

S_Top

UG2

Phase1

3

S_Top

S_Top S_Top

S_Top

S_Bot

S_Bot S_Bot

S_Bot

PR242

PR242 0

0

R0603

R0603 S_Bot

S_Bot

Phase2

PR263

PR263 0

0

R0603

R0603 S_Bot

S_Bot

PR265

PR265 0

0

R0603

R0603 S_Bot

S_Bot

PQ61

PQ61 AOL1426

AOL1426

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

3

+V1.1S_VTT

PQ55

PQ55 AOL1426

AOL1426

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

4

G

PR245

PR245 10K

10K

R0402

R0402 S_Bot

S_Bot

4

G

0PR262 R0603

S_Bot

LG1a

PR283

PR283 10K,1%

10K,1%

R0402

R0402 S_Bot

S_Bot

4

PR264

PR264 10K

10K

R0402

R0402 S_Bot

S_Bot

4

G

PQ57

PQ57 AOL1718

AOL1718

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

SO8_50_150_PPAK

AOL1718

AOL1718 PQ58

PQ58

S_Bot

56789

D

S

56789

D

S

LG1b

S

D

56789

S

D

56789

PC180

PC180 10uF/ 25V

10uF/ 25V

C1210

C1210 S_Bot

S_Bot

PQ56

PQ56 AOL1718

AOL1718

123

SO8_50_150_PPAK

SO8_50_150_PPAK S_Bot

S_Bot

4

123

PC106

1uF/10V,X7R

C0603

S_Top

PC107

PC107 1uF/10V,X7R

1uF/10V,X7R

C0603

C0603 S_Top

S_Top

123

4

SO8_50_150_PPAK

123

AOL1718

AOL1718 PQ59

PQ59

S_Bot

PC110

PC109

10uF/ 25V

C1210

S_Top

PR281

2.49K,1%

R0402

R0402 S_Bot

S_Bot

PR238

PR238 10K,1%

10K,1%

R0603

R0603 S_Bot

S_Bot

NTC thermistor

度下，

10K

25

度下，

3.05K

60

度下，

1.71K

80

放于电感背面。

D

G

D

。

56789

S

56789

PC181

PC181 10uF/ 25V

10uF/ 25V

C1210

C1210 S_Bot

S_Bot

PD19

PD19 SBM54PT

SBM54PT

SMB

SMB S_Top

S_Top

1

123

+V5S

PD20

SBM54PT

SMB

S_Top

123

1

PC187

0.1uF/25V,X7R

C0603

C0603 S_Bot

S_Bot

0.01uF/25V,X7R

S_Bot

3A

ISUM+

ISUM-

2

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,56,57,58} +V5S {23,25,29,32,33,34,35,36,37,38,43,51,52,56} +VDC {32,40,46,48,49,50,51,52,56,57} +VCC_CORE {10}

+V1.1S_VTT {8,10,11,27,28,29,38,50,51}

3A

PC102

0.1uF/25V,X7R

C0603

S_Top

PR167

2.2

R0805

ns

S_Top

PC98

0.01uF/25V,X7R

C0402

ns

S_Top

PC97

0.01uF/25V,X7R

C0402 ns

C0402 ns S_Top

S_Top

PR168

2.2

R0805

ns

S_Top

PC104

0.01uF/25V,X7R

C0402

S_Top

3.57K,1%

S_Bot

PC184

C0402

+VDC

2

0.01uF/25V,X7R

S_Bot

PR257

R0402

+VDC

PC182

C0402

ISEN2

ISEN1

PC103

0.01uF/25V,X7R

C0402

S_Top

PC83

220UF/2.5V,POSCAP

PL9

1

0.36uH/30A

LS2_1040

LS2_1040 S_Bot

S_Bot

PR256

PR256 10K

10K

R0402

PR258

S_Bot

10

R0402

R0402 S_Bot

S_Bot

PR259

PR261

PR261 10K

10K

10

R0402

S_Bot

PL10

1

0.36uH/30A

LS2_1040

LS2_1040 S_Bot

S_Bot

PR260

3.57K,1%

R0402

R0402 S_Bot

S_Bot

Page Name

Size

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

220UF/2.5V,POSCAP

25A

S_Top

PC169

1uF/10V,X7R

C0603

S_Bot

CT7343_19

+

220UF/2.5V,POSCAP

S_Top

25A

Project Name Rev

1

PC86

220UF/2.5V,POSCAP

CT7343_19

S_Top

12

1

PC82

CT7343_19

220UF/2.5V,POSCAP

S_Top

TOPSTAR TECHNOLOGY

bent

bent +VCC_CORE

+VCC_CORE

C46

12

1

+

PC84

CT7343_19

ns

12

1

+

220UF/2.5V,POSCAP

S_Top

1

VCORE1

VCORE1 TestP

TestP

TPC60

ns

S_Top

+VCC_CORE

12

1

+

PC85

CT7343_19

12

1

+

PC81

220UF/2.5V,POSCAP

CT7343_19

ns

S_Top

55 59Friday, November 27, 2009

of

50A

12

+

B

5

D D

+VDC

PR186

PR186 100K

100K

R0402

R0402 S_Top

S_Top

PR184

PR184 1K

1K

R0402

R0402 S_Top

MAIN_OFF

C C

MAIN_ON{43}

PR183

PR183 1K

1K

R0402

R0402 S_Top

S_Top

PR181

PR181 510K

510K

R0402

R0402 S_Top

S_Top

3

1

2

+V1.5S

PQ31

PQ31 2N7002

2N7002

S_Top

SOT23

4

2 3

PC108

0.01uF/25V,X7R

C0402

C0402 S_Top

S_Top

PQ33

DTB114EK

SOT23

1

S_Top

PR187

PR187 10K

10K

R0402

R0402 S_Top

S_Top

+V1.05S +V0.75S

PR200

PR200 33K

33K

R0402

R0402 S_Top

S_Top

PC119

0.01uF/25V,X7R

C0402

S_Top

3

2

+VDC {32,40,46,48,49,50,51,52,55,57} +V5S {23,25,29,32,33,34,35,36,37,38,43,51,52,55} +V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49, +V5AL {29,32,36,48,49,50,53} +V3.3AL {6,23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,57} +V1.05S {22,23,24,28,29,50,57,58} +V1.5 {8,11,15,16,49,57} +V1.8S {11,26,28,29,31,49,57} +V0.75S {15,16,49} AD+ {36,46,48} BATT+ {46,47,54} +V1.5S {39,40,41}

1

+V3.3AL

PD24

PD24 1N4148WS

1N4148WS

SOD323

SOD323 S_Top

S_Top

1

4

PR197

PD18

PD18 1N4148WS

1N4148WS

SOD323

SOD323 S_Top

S_Top

PR20

PR20 100K

100K

R0402

R0402 S_Top

S_Top

PR197 51K

51K

R0402

R0402 S_Top

S_Top

PC111

0.01uF/25V,X7R

C0402

S_Top

1

PR144

PR144 100K

100K

R0402

R0402 S_Top

S_Top

PC75

0.01uF/25V,X7R

C0402

S_Top

PQ28

PQ28 AO4468

AO4468

SO8_50_150

SO8_50_150 S_Top

S_Top

dri1.5

4

PR199

PR199 20K

+V5AL

PQ65

567

8

AO4468

D

SO8_50_150

SO8_50_150 S_Bot

4

S_Bot

G

S

123

PC189

1uF/10V,X7R

C0603

S_Bot

V5S1

V5S1 TestP

TestP

TPC60

ns

S_Bot

+V5S

20K

R0402

R0402 S_Top

S_Top

PR146

PR146 10K

10K

R0402

R0402 S_Top

S_Top

+V1.8S

PQ39

PQ39 AO4468

AO4468

567

8

SO8_50_150

D

S_Top

G

S

123

PC123

PC123 1uF/10V,X7R

1uF/10V,X7R

C0603

C0603 S_Top

S_Top

V3_3S1

V3_3S1 TestP

TestP

TPC60

ns

S_Top

+V3.3S

+V1.5

PQ27

567

8

D

G

S

dri1.5

4

123

PC76

PC76 1uF/10V,X7R

1uF/10V,X7R

C0603

C0603 S_Top

S_Top

PQ27 AO4468

AO4468

567

8

SO8_50_150

D

ns

S_Top

G

S

123

+V1.5S

+V1.5+V3.3S+V5S

+VDC

B B

PR192

PR192 100

100

R0402

R0402 S_Top

S_Top

PR189

PQ34

PQ34 2N7002

2N7002

SOT23

ns

1

S_Top

PR189 100

100

R0402

ns

S_Top

PR190

PR190 100

100

R0402

R0402 S_Top

S_Top

3

2

PR188

PR188 100

100

R0402

ns

1 2

PQ36

3

2N7002

SOT23

S_Top

1

ns

S_Top

2

PR191

PR191 100

100

R0402

R0402 S_Top

S_Top

1 2

PQ35

3

2N7002

SOT23

S_Top

1

2

PR79

PR79 100

100

R0402

ns

1 2

S_Top

3

PQ15

PQ15 2N7002

2N7002

SOT23

1

SOT23

ns

S_Top

2

PQ16

PQ16 2N7002

2N7002

SOT23

SOT23 S_Top

S_Top

1

PR80

PR80 100

100

R0402

R0402 S_Top

S_Top

1 2

3

2

PQ14

PQ14 2N7002

2N7002

SOT23

S_Top

1

PR75

PR75 100

100

R0402

R0402 S_Top

S_Top

1 2

V1_8DISCHG

3

10KPR306

PM_SLP_S4#{24,41,43}

10KPR306

R0402

R0402 S_Bot

S_Bot

2

PQ68

PQ68 2N7002

2N7002

SOT23

S_Bot

1

PR298

PR298 100

100

R0402

R0402 S_Bot

S_Bot

3

2

PR297

PR297 100

100

R0402

ns

1 2

S_Bot

PQ67

3

2N7002

SOT23

S_Bot

V1_8DISCHG

1

2

PR305

PR305 510K

510K

R0402

R0402 S_Bot

S_Bot

PR299

200K

R0402

R0402 S_Bot

S_Bot

MAIN_OFF

A A

Page Name

Size

Project Name Rev

A3

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

TOPSTAR TECHNOLOGY

bent

bent SYSTEM/DISCHARGE

SYSTEM/DISCHARGE

M12

1

B

56 59Friday, November 27, 2009

B

of

5

4

+VDC

PR317

PR317 51K

51K

R0402

3

2

+VDC

3

2

R0402

PM

S_Top

PR121

PR121 51K

51K

R0402

PM

S_Top

D D

+VDC

PR64

PR64 51K

51K

PR65

R0402

PM

10

S_Top

R0402 PM

PQ9

PQ9 2N7002

2N7002

SOT23

3

PM

S_Top

V3G_1.05G_ON

{43}

C C

B B

A A

PR62

PR62 1K

1K

R0402

PM

S_Top

1

PR63

PR63 510K

510K

R0402

PM

S_Top

2

5

R0402 PM S_Top

S_Top

PR158

PR158 51K

51K

R0402

PM

S_Top

1

PQ79

PQ79 2N7002

2N7002

SOT23

PM

S_Top

1

PQ24

PQ24 2N7002

2N7002

SOT23

PM

S_Top

PR319

PR319 510K

510K

R0402

PM

S_Top

PR126

PR126 200K

200K

R0402

PM

S_Top

PR318

PR318 10

10

R0402

PM

S_Bot

PR254

PR254 10

10

R0402

PM

S_Bot

4

567

D

4

G

S

PC214

0.01uF/25V,X7R

C0402

PM

S_Bot

PC61

PC61 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

S_Bot

V3GPU_OFF

567

D

4

G

S

PC179

0.01uF/25V,X7R

C0402

PM

S_Bot

+V3.3S

PQ78

PQ78 AO4468

AO4468

8

SO8_50_150

PM

S_Bot

123

1

PQ11

PQ11 2N7002

2N7002

SOT23

PM

S_Top

+V1.05S

PQ60

PQ60 AO4468

AO4468

8

SO8_50_150

PM

S_Bot

123

PC171

PC171 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

S_Bot

PR67

PR67 220

220

R0402

PM

S_Top

3

V3_3GPU1

V3_3GPU1 TestP

TestP

TPC60

ns

S_Top

+V3.3GPU

3.5A

PR68

PR68 220

220

R0402

PM

1 2

4

PM

S_Top

PQ54

PQ54 AO4468

AO4468

SO8_50_150

ns

S_Bot

567

D

G

S

V1.8G_1.5G_ON{43}

PM

8

123

PQ10

PQ10 2N7002

2N7002

SOT23

1

S_Top

PR66

PR66 100

100

R0402

PM

S_Top

PR70

PR70 1K

1K

R0402

PM

S_Top

V1_05GPU1

V1_05GPU1 TestP

TestP

TPC60 ns

S_Top

0.53A 峰值可为2.5A

1 2 3

2

3

+V1.05GPU

1 2

3

2

PQ8

PQ8 2N7002

2N7002

SOT23

PM

S_Top

1

PR69

PR69 510K

510K

R0402

PM

S_Top

+VDC

3

2

PR71

PR71 51K

51K

R0402

PM

S_Top

PR72

PR72 10

10

R0402 PM

R0402 PM S_Top

S_Top

PR156

PR156 51K

51K

R0402

PM

S_Top

+V1.8S

+V3.3S

1

PQ64

PQ64 2N7002

2N7002

SOT23

SOT23 S_Bot

S_Bot

2

PR133

PR133 0

0

R0402 S_Top

PM

PR120

PR120 0

0

R0402

ns

S_Top

+VDC

PR285

PR285 51K

51K

R0402

PM

S_Bot

3

2

PM

2

1

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41, +V1.05S {22,23,24,28,29,50,56} +V1.5 {8,11,15,16,49,56} +V1.8S {11,26,28,29,31,49,56} +V3.3GPU {17,20,21,33,34} +V1.05GPU {17,18,19,20} +V1.8GPU {20} +V1.5GPU {18,19} +VDC {32,36,40,46,48,49,50,51,52,55,56} +V5S {23,29,32,33,34,35,36,37,38,43,51,52,55,56}

V1_8GPU1

1

PQ63

PQ63 AO4468

AO4468

SO8_50_150

PM

S_Bot

4

PC186

C0402

PM

3

PQ25

PQ25 AO3415

AO3415

SOT23

PM

S_Top

D

G

1uF/10V,X7R

S_Top

+V1.5

567

S

PC68

C0603

PM

8

4

123

PC178

PC178 1uF/10V,X7R

1uF/10V,X7R

C0603

PM

S_Bot

TOPSTAR TECHNOLOGY

bent

bent SYSTEM/DISCHARGE

SYSTEM/DISCHARGE

M12

PR73

PR73 100

100

R0402

PM

1 2

S_Top

3

PQ12

PQ12 2N7002

2N7002

SOT23

8

123

PR74

PR74 100

100

R0402

PM

S_Top

57 59Friday, November 27, 2009

SOT23

PM

S_Top

2

PQ62

PQ62 AO4468

AO4468

SO8_50_150

PM

S_Bot

1 2 3

2

of

1

567

D

G

S

PQ13

PQ13 2N7002

2N7002

SOT23

PM

1

S_Top

1

2

PR125

PR125 20K

20K

R0402

ns

S_Top

PR272

PR272 10

10

R0402 PM

R0402 PM S_Bot

S_Bot

PR271

PR271 200K

200K

R0402

S_Bot

PM

0.01uF/25V,X7R

S_Bot

Page Name

Page Name Size

Size

Project Name Rev

B

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

TestP

TPC60

ns

S_Bot

+V1.8GPU

<0.5A

V1_5GPU1

+V1.5GPU

3A

TestP

TPC60

ns

S_Bot

B

5

D D

H19

HOLE

1

TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

H22

HOLE

1

TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

GND GND GNDGND GND GND GND GNDGND_AUD

C C

H15

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

4

H23

H18

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

H23

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

H20

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

H16

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

3

H21

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

H17

HOLE

1 TH_197_118

TH_197_118 ns

ns S_Top

S_Top

H24

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

H25

HOLE

1 TH_315_118_P

TH_315_118_P ns

ns S_Top

S_Top

2

+V3.3S {6,8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57} +V1.05S {22,23,24,28,29,50,56,57}

1

GND GND

+V3.3S +V3.3S

C219

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

+V1.05S +V1.05S +V1.05S +V1.05S

C115

C228

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

C133

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

C115

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

C99

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

+V3.3S +V3.3S

C121

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

+V3.3S +V3.3S

C202

C194

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

B B

C202

0.1UF/10V,X7R

C0402

C0402 S_Top

S_Top

E6

E4

1

EMI

1

ns

ns S_Top

S_Top

1

EMI

1

ns

S_Top

E2

E7

E4

E6

E5

1

EMI

1

ns

ns S_Top

S_Top

1

EMI

1

ns

ns S_Bot

S_Bot

Add for EMI By Johan 071228

E9

E10

1

EMI

1

ns

S_Bot

S_Top

GND

FD2

FD1

FD4

FD8

FD7

1

FMARKS

ns

FD10

FD9

1

FMARKS

ns

A A

5

4

FD4

1

FMARKS

ns

FD11

FD12

1

FMARKS

ns

FD5

FD6

1

FMARKS

ns

FD14

FD13

1

FMARKS

ns

FD2

FD3

1

FMARKS

ns

FD15

1

FMARKS

ns

1

FMARKS

ns

FD16

1

FMARKS

ns

TOPSTAR TECHNOLOGY

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Page Name

Page Name Size

Size

Project Name Rev

C

Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

3

2

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SYSTEM/DISCHARGE

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58 59Friday, November 27, 2009

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CLOCK Distribution:

MEM_CHA_CLK0 MEM_CHA_CLK#0

MEM_CHA_CLK2

Auburndale

D D

BCLK_CPU

MEM_CHA_CLK#2

MEM_CHA_CLK1 MEM_CHA_CLK#1

MEM_CHA_CLK3 MEM_CHA_CLK#3

14.318MHz

SODIMM0

SODIMM1

FBA_CLK0 FBA_CLK0#

200MHz

FBA_CLK1 FBA_CLK1#

100MHz

33MHz

48MHz

24MHz

25MHz

Audio Codec ALC662

GDDR3 1

64Mb*16bit*4

GDDR3 2

EXPRESS CARD

Mini PCIE

PCIE LAN

EC(KB3926)

Card Reader (IT1337E)

25MHz

32.768KHz

DMI 100 MHz

133MHz

CPU_0# CPU_0

DOT96# DOT96

SRC0#/SATA SRC0/SATA

SRC1#

C C

SRC1

REF/FS

Pin22 Pin23

Pin4 Pin3

Pin11 Pin10

Pin14 Pin13

Pin30

133MHz

100MHz

14.318MHz

CLK_BUF_BCLK_N CLK_BUF_BCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

IBEX_PEAK

CLK_BUF_SATA_N CLK_BUF_SATA_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_REF14

BCLK 133MHz

DP 120MHz

32.768KHz

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

100MHz

27NSS

27SS

B B

Pin6

Pin7

27MHz

XTAL_IN

XTAL_SSIN

100MHz

N11

A A

TOPSTAR TECHNOLOGY

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Page Name

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Project Name Rev

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Date: Sheet

PROPERTY NOTE: this document contains information confidential and property to

PROPERTY NOTE: this document contains information confidential and property to TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without

to others or used for any purpose other than that for which it was obtained without the expressed written consent of TOPSTAR

the expressed written consent of TOPSTAR

5

4

3

2

the expressed written consent of TOPSTAR

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N10M PCIE&PWR&GND

C46

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CCE T546P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual