Calogic LLC J112, J111, J113 Datasheet
CORPORATION
N-Channel JFET Switch
J111 - J113 / SST111 – SST113
FEATURES
Low Cost
••
Automated Insertion Package
••
Low Insertion Loss
••
No Offset or Error Volt ag e Gener at ed By Cl ose d Switc h
••
Purel y R esisti ve
-
High Isolation Resistance From Driver
-
Fast Switching
••
Short Sampl e and Hol d Ape rt ure T ime
••
PIN CONFIGU R ATION
SOT-23
G
TO-92
D
S
PRODUCT MARKING (SOT-23)
SST11 1 11 1
SST112 1 12
SST113 1 13
5001
G
S
D
APPLICATIONS
Analo g Sw it c h es
••
Choppers
••
Commutators
••
ABSOLUTE MAXIMUM RATINGS
= 25oC unless otherwise specified)
(T
A
Gate-Drain or Gate-So urce Voltage . . . . . . . . . . . . . . . . -35V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperatur e Ra nge. . . . . . . . . . . . . -55
Operating Temperatur e Ra nge . . . . . . . . . . . -55
Lead Temperature (Soldering, 10se c). . . . . . . . . . . . . +300
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Derate above 25
NOTE: Stresses above those listed under "Absolute Maxi mum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
o
C . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC
o
C to +150oC
o
C to +135oC
o
ORDERING INFORMATION
Part Package Temperature Range
o
J1 11-113 Plastic SOT-23 -55
SST111-113 Plastic SOT- 23 -55
C to +135oC
o
C to +135oC
For Sorted Chips in Carr iers see 2N4391 series.
C
ELECTRICAL CHARACTERISTIC S (T
SYMBOL P ARAMETER
I
GSSR
V
GS(off)
BV
GSS
I
DSS
I
D(off)
r
DS(on)
C
dg(off)
C
sg(off)
C
dg(on)
+ C
t
d(on)
t
r
t
d(off)
t
f
NOTES: 1. Approximately doubles for every 10
Gate Reverse Current (Note 1) -1 -1 -1 nA VDS = 0V, VGS = -15V
Gate Source Cutoff Voltage -3 -10 -1 -5 -0.5 -3
Gate Source Breakdown Voltage -35 -35 -35 VDS = 0V, IG = -1µA
Drain Saturation Current (Note 2) 20 5 2 mA VDS = 15V, VGS = 0V
Drain Cutoff Current (Note 1) 1 1 1 nA VDS = 5V, VGS = -10V
Drain Source ON Resistance 30 50 100 Ω VDS = 0.1V, VGS = 0V
Drain Gate OFF Capacitance 5 5 5
Source Gate OFF Capacitance 5 5 5
Drain Gate Plus Source Gate ON
Capacitance
sg(on)
Turn On Delay Time 7 7 7
Rise Time 6 6 6
Turn Off Delay Time 20 20 20
Fall Time 15 15 15
2. Pulse test duration 300µs; duty cycle ≤3%.
3. For design reference only, not 100% tested.
= 25oC unless otherwise sp ecif ied)
A
111 112 113
MIN TYP MAX MIN TYP MAX MIN TYP MAX
28 28 28
o
C increase in TA.
UNITS TEST CONDITIONS
VDS = 5V, ID = 1µA
V
VDS = 0,
V
= -10V
GS
(Note 3)
pF
V
DS
(Note 3)
Switching Time Test
Conditions (Note 3)
ns
V
DD
V
GS(off)
R
L
= VGS = 0
J111 J112 J113
10V 10V 10V
-12V -7V -5V
0.8kΩ 1.6kΩ 3.2kΩ
f = 1MHz
CALOGIC CORPOR ATION, 237 Whitney Plac e, Fremont, California 94539, Telephone: 510-656-290 0, FAX: 510-651-1076
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