Calogic LLC BS170L, 2N7000 Datasheet
CORPORATION
BOTTOM VIEW
1
2
3
1
2
3
SOURCE
GATE
DRAIN
1
2
3
2N7000
BOTTOM VIEW
1
2
3
1
2
3
DRAIN
GATE
SOURCE
3
2
1
BS170L
N-Channel Enhancement-Mode
MOS Transistor
2N7000 / BS170L
DESCRIPTION
The 2N7000 utilizes Calogic’s vertical DMOS technology. The
device is well suited f or switching applications where B
of
V
60V and low on resistance (under 5 ohms) are required. The
2N7000 is housed in a plastic TO -92 pac kage .
PIN CONFIGU R ATION
TO-92
(TO-226AA)
3
2
1
ORDERING INFORMATION
Part Package Temperature Range
o
2N7000 Plastic TO-92 -55
BS170L Plastic T O -92 -55
X2N7000 Sorted Chips in Carriers -55
C to +150oC
o
C to +150oC
o
C to +150oC
CD5
PRODUCT SUMMAR Y
V
P/N
2N7000 60 5 0.2
BS170 60 5 0.5
(BR)DSS
(V)
r
DS(ON)
(Ω)
I
(A)
D
2N7000 / BS170L
CORPORATION
ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise specified)
SYMBOL PARAM ETERS LIMITS UNITS TEST CONDITIONS
V
DS
V
GS
I
D
I
DM
P
D
T
J
stg
T
L
THERMAL RESISTANCE RA TING S
NOTE: 1. Pulse width limited by maximum junction temperature.
SPECIFICA TIONS
SYMBOL PARAMETER MIN TYP
STATIC
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
I
D(ON)
r
DS(ON)
V
DS(ON)
g
FS
g
OS
DYNAMIC
C
iss
C
oss
C
rss
SWITCHING
t
ON
t
OFF
Drain-Source Voltage 60
Gate-Source Voltage ±40
Continuous Drain Current
Pulsed Drain Current
Power Dissipation
1
1
0.2
0.13 T
0.5
0.4
0.16 T
V
T
= 25oC
A
A
W
= 100oC
A
TA = 25oC
= 100oC
A
Operating Junctio n Temperature Range -55 to 150
o
Storage Temperature Range -55 to 150
CT
Lead Temperature (1/16" from case for 10 sec.) 300
SYMBOL THERMAL RESISTANCE LIMITS UNITS
R
thJA
1
Drain-Source Breakdown Voltage 60 70
Gate-Thresho ld Voltage 0.8 1.9 3 VDS = VGS, ID = 1mA
Junction-to-Ambient 312.5 K/W
2
MAX UNIT TEST CONDITIONS
ID = 10µA, VGS = 0V
V
Gate-Body Leakage ±10 nA VGS = ±15V, VDS = 0V
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Drain-Source On-Voltage
Forward Transconductance
3
3
3
3
Common Source Output Conductance
1
1000 T
75 21 0 mA VDS = 10V, VGS = 4.5V
4.8 5.3
2.5 5 V
4.4 9 T
0.36 0.4
1.25 2.5 V
2.2 4.5 T
100 170 mS V
3, 4
500 µSVDS = 5V, ID = 50mA
µA
V
= 48V, VGS = 0V
DS
4
VGS = 4.5V, ID = 75mA
Ω
V
= 10V, ID = 0.5A
GS
4
VGS = 4.5V, ID = 75mA
= 10V, ID = 0.5A
GS
= 10V, ID = 0.2A
DS
C
C
C
Input Capacitance 16 60
Output Capacitance
4
11 25
pF V
= 25V, VGS = 0V, f = 1MHz
DS
Reverse Transfer Capacitance 2 5
V
= 15V, RL = 25Ω, ID = 0.5A
Turn-On Time 7 10
nS
Turn-Off Time 7 10
DD
V
= 10V, RG = 25Ω
GEN
(Switching time is essentially
independent of operating temperature)
= 125oC
= 125oC
= 125oC
4
NOTES: 1. T
2. For design aid only, not subject to productio n testin g.
3. Pulse test; PW = ≤300µS, duty cycle ≤3%.
4. This p aram eter not registered with JEDEC.
= 25oC unless otherwise specified.
A
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