Calogic SST174, SST174, SST175, SST175, SST176 Schematics
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P-Channel JFET Switch
J174 – J177 / SST174 – SST177
CORPORATION
FEATURES
Low Insertion Loss
••
No Offset or Error Gener at ed By Cl ose d Sw itch
••
Purel y R esistive
-
High Isolation Resistance From Driver
-
Short Sampl e and Hol d Ape rt ure T ime
••
Fast Switching
••
APPLICATIONS
Analo g Sw it c h es
••
Choppers
••
Commutators
••
PIN CONFIGU R ATION
TO-92
D
S
S
G
D
5508
PRODUCT MARKING (SOT-23)
SST174 P04
SST175 P05
SST176 P06
SST177 P07
G
SOT-23
ABSOLUTE MAXIMUM RATINGS
= 25oC unless otherwise specified)
(T
A
Gate-Drain or Gate-So urce Voltage . . . . . . . . . . . . . . . . . 30V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Tem per at ure R a nge. . . . . . . . . . . . . -55
Operating Temperatur e Ra nge . . . . . . . . . . . -55
Lead Temperature (Soldering, 10se c). . . . . . . . . . . . . . 300
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350mW
Derate above 25
NOTE: Stresses above those listed under "Absolute Maxi mum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
Part Package Temperature Range
J174-J177 Plastic TO-92 -55
SST174-SST177 Plastic SOT-23 -55
For Sorted Chips in Carr iers see 2N5114 series.
o
C . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC
o
C to +150oC
o
C to +135oC
o
C to +135oC
o
C to +135oC
o
C
CORPORATION
ELECTRICAL CHARACTERISTIC S (TA = 25oC unless otherwise sp ecif ied)
SYMBOL PARAMETER
Gate Reverse
I
GSS
Current
(Note 1)
V
GS(off)
Gate Sou r ce
Cutoff Voltage
Gate Sou r ce
GSS
Breakdown
BV
Voltage
Drain
I
DSS
Saturation
Current
(Note 2)
Drain Cutoff
I
D(off)
Current
(Note 1)
r
DS(on)
Drain-Source
ON Resistance
Drain-Gate
C
dg(off)
OFF
Capacitance
Source-Gate
C
sg(off)
OFF
Capacitance
Drain-Gate
C
+ C
dg(on)
sg(on)
Plus Source
Gate ON
Capa ci tance
t
d(on)
t
r
t
d(off)
t
f
Turn On Delay
Time
Rise Time
Turn Off Delay
Time
Fall Time
NOTES: 1. Approximately doubles for every 10
2. Pulse test duration -300µs; duty cycle ≤3%.
3. For design reference only , not 100% tested.
J174 J175 J176 J177
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
1111nA
5 10 3 6 1 4 0.8 2.25
30 30 30 30 V
-20 -135 -7 -70 -2 -35 -1.5 -20 mA V
-1 -1 -1 -1 nA V
85 125 250 300 Ω V
5.5 5.5 5.5 5.5
5.5 5.5 5.5 5.5
32 32 32 32
2 5 15 20
5 102025
5 101520
10 20 20 25
o
C increase in TA.
UNITS TEST CONDITIONS
V
= 0, VGS = 20V
DS
V
= -15V, ID = -10nA
DS
V
= 0, IG = 1µA
DS
= -15V, VGS = 0
DS
= -15V, VGS = 10V
DS
= 0, VDS = -0.1V
GS
= 0,
V
DS
V
= 10V
GS
pF
V
= VGS = 0
DS
f = 1MHz (Note 3)
Switching Time Test Conditions
(Note 3)
J174 J175 J176 J177
ns
V
V
R
V
-10V -6V -6V -6V
DD
12V8V3V3V
GS(off)
560Ω 12kΩ 5.6kΩ 10kΩ
L
GS(on)
0V 0V 0V 0V
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