California Micro Devices PACVGA201Q Datasheet

CALIFORNIA MICRO DEVICES

VGA PORT COMPANION CIRCUIT

PACVGA201

Features

Pin Diagram

 7 channels of ESD protection for all VGA port

connector pins meeting IEC-61000-4-2 Level-4 ESD

requirements (8KV contact discharge)

 Very low loading capacitance from ESD protection

diodes on VIDEO lines, 4pF typical

 TTL to CMOS level-translating buffers with power

down mode for HSYNC and VSYNC lines

 Three power supplies for design flexibility

 Compact 16-pin QSOP package

16-PIN QSOP PACKAGE

Product Description

The PACVGA201 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection

is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-

2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current

pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.

Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low

voltage video controller ICs and provide design flexibility in multiple-supply-voltage environments.

An internal diode (D1, in schematic below) is provided such that V

power supply input.) In applications where V

DDC_OUT pins back to the powered down V

may be powered down, diode D1 blocks any DC current path from the

CC3

rail via the upper ESD protection diodes.

CC3

is derived from V

CC2

CC3

. (V

does not require an external

CC2

Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).

These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V

CC3

.

When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current

from the V

supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.

CC3

Schematic Diagram

© 2000 California Micro Devices Corp. All rights reserved.

4/00

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

PAC VGA201 is a trademark of California Micro Devices Corp.

C0651299

1

CALIFORNIA MICRO DEVICES

PACVGA201

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Note 1: These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP.

Note 2: These parameters apply only to SYNC_OUT1 and SYNC_OUT2.

Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V

a low impedance ground plane with a 0.2uF or greater, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied

between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1,

VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the

industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).

Note 4: This parameter is guaranteed by design and characterization.

©2000 California Micro Devices Corp. All rights reserved.

2

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

CC1

, V

CC2

and V

must be bypassed to GND via

CC3

4/00