California Micro Devices PACVGA200Q Datasheet
CALIFORNIA MICRO DEVICES
VGA PORT COMPANION CIRCUIT
PACVGA200
Features
Pin Diagram
7 channels of ESD protection for all VGA port
connector pins meeting IEC-61000-4-2 Level-4 ESD
requirements (8KV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
75 Ω termination resistors for VIDEO lines (matched
to 1%typ.)
Bi-directional level shifting N-channel FETs provided for
DDC_CLK & DDC_DATA channels
Compact 24-pin QSOP package
24-PIN QSOP PACKAGE
Product Description
The PACVGA200 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-1000-4-
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.
Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage
Video Controller ICs and provide design flexibility in multi-supply-voltage environments.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V
drivers have nominal 60Ω output impedance to match the characteristic impedance of the HSYNC & VSYNC lines of the video
. These
CC4
cables typically used in PC applications.
Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage
than the monitor.
Three 75Ω termination resistors suitable for terminating the video signals from the video DAC are also provided. These
resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and
the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching for the R/G/B
signals.
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current
from the V
An internal diode (D1 in schematic below) is also provided so that V
to V_BIAS. In applications where V
back to the powered down V
supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.
CC3
can be derived from V
may be powered down, diode D1 blocks any DC current paths from the DDC_OUT pins
CC4
rail via the top ESD protection diodes.
CC4
CC3
, if desired, by connecting V
CC4
CC3
Schematic Diagram
© 2000 California Micro Devices Corp. All rights reserved.
4/00
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
PACVGA200 is a trademark of California Micro Devices Corp.
C0641299
1
CALIFORNIA MICRO DEVICES
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Note 1: These parameter applies only to the HSYNC and VSYNC channels.
Note 2: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V
to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins
are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD
protected to the industry standard 2kV per the Human Body model (MIL-STD-883, Method 3015).
Note 3: This parameter is guaranteed by design and characterization.
©2000 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
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, V
and V
CC1
CC3
8.0-V
4CC
Ω
µA
µA
01
µA
01
µA
must be bypassed
CC4
4/00
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